JOURNAL OF COMPUTING, VOLUME 3, ISSUE 12, DECEMBER 2011, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.

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A Method for Routing Packets Across Multiple Paths for increase communication load in 2D and 3D Network on Chip Architectures

Mohammad Reza Nouri Rad

Department of Computer Engineering Islamic Azad University Khorramabad Branch, Iran

Reza Kourdy
Department of Computer Engineering Islamic Azad University Khorramabad Branch, Iran

Abstract Combination of Multi-path routing with equal hop count can increase Communication load of the cores in network on chip. We used an Arbiter that forwarding data packet to destination node in round-robin Manner, so that we can use the more than one link bandwidth to increasing the communication load of the cores. The equal hop count for each portion of flows caused to we have no packet reordering in destination node. We compare the performance of two and three dimensional Mesh and Torus architectures using Multipath routing in the sense of on chip network design methodology. The simulations of each of the architectures are done with IP and Multi-path routing, two-dimensional and three-dimensional topologies. We also carry out the high level simulation of on chip network using NS2 to verify the analytical analysis. Keywords- Network-on-Chip, increase communication load, Bandwidth utilization, 2D and 3D Mesh and torus, Multipath Routing.

A new chip design paradigm called Network on Chip (NOC) offers a promising architectural choice for future systems on chips [4]. Moore's law predicts that by 2008, it will be possible to integrate over a billion transistors on a single chip. Current core based on SOC methodologies will not respond to the needs of the billion transistor era. Network on Chip (NOC), a new chip design paradigm concurrently proposed by many research Groups [5], [6], [7] is expected to be an important architectural choice for future SOCs. We would use the tool, Network Simulator ns-2 [8],[9] which has been extensively used in the research for design and evaluation of public domain computer network, to evaluate various design options for NOC architecture, including the design of router, communication protocol and Routing algorithms. NS-2 is an open source, object-oriented and discrete event driven network simulator written in C++ and OTcl. It is a very common and widely used tool to simulate small and large area networks [10]. II. BACKGROUND

I.

INTRODUCTION

With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip and multi-core architectures. Another trend for such architectures is network-on-chip (NoC) becoming a standard for on-chip global communication. In an earlier work, a generic fault tolerant routing algorithm in the context of NoCs has been presented [1], [2]. Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent of multiprocessor Systems-on-chip (SoCs) makes it even more challenging for programmers to utilize the full potential of the computation resources on the chips. In the mean time, the complexity of the chip design creates new reliability challenges. As a result, chip designers and users cannot fully exploit the tremendous silicon resources on the chip. This research proposes a Proto type which is composed of a fault-tolerant multiprocessor SoC and a coupled single program, multiple data (SPMD) programming framework[3].

A. Fault Model There exist several dimensions in classifying the possible fault occurrences during the life cycle of an MPSoC. We list the classification as follows: Duration In terms of duration, the faults can be classified into transient faults and permanent faults [11]. In the case of the MPSoC, both types of fault can occur in the chip life cycle. Crash failures are permanent faults which occur when a tile halts prematurely or a link disconnects, after having behaved correctly until the failure. Transient faults can be either omission failures, when links lose some messages and tiles intermittently omit to send or receive, or arbitrary failures (also called Byzantine or malicious), when links and tiles deviate arbitrarily from their specification, corrupting or even generating spurious messages [12]. Location In general, MPSoC designs consist of two integrated parts, the Processing Elements (PEs) and Network-on-Chip (NoC). Faults can occur in both parts. In

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the case that a fault occurs in the PEs, the computation results will be erroneous. Dynamic fault detecting and masking actions are needed to make sure the erroneous results will not contaminate the application environment. In the case that a fault occurs in the communication path, such as link failure and scrambled messages, a fault-tolerant communication protocol suite, including error-resilient coding schemes, are needed to ensure the reliable delivery of on-chip messages on top of an unreliable on-chip communication substrate. Time to Failure Faults can occur throughout the lifetime of an IC. Using the point when the chip is packaged and tested as the watershed event, we distinguish between before-shelf faults and after-shelf faults. Currently, chips with before shelf faults, i.e., defects which are discovered during testing, are invariably discarded. Only dies with no discovered defects are shipped out as products. With the shrinking feature size, it is becoming increasingly difficult to achieve decent yield with reasonable cost. The low yield problem will become more acute for the 90nm technology and beyond. On the other hand, the potential yield of the manufacturing process can increase tremendously if some defects on the die can be tolerated in the ICs after-shelf life. Static fault masking and isolation techniques, both hardware and software based, can be used to use these previously deemed Bad chips in commercial products, such as Pico Chip [13]. For after-shelf faults, dynamic fault detection and recovery means are needed to ensure the correct function of the chip as long as possible. Furthermore, graceful degradation of system performance is necessary for some mission-critical Applications. B. Quality of Service in Network on Chip Network on Chip is likely to become an attractive alternative for implementing SoCs for many application areas like real time multi-media applications. This implies that the underlying on-chip communication network will be required to provide deterministic bounds on delays and throughput for communication among some pairs of cores on the chip. [14] III. SYSTEM ARCHITECTURE

round robin manner that shown in monitor part of the network animator (NAM).

Figure 1- proposed scheme

As shown in fig. 1, when three packets with different sequence numbers (40081, 40082 and 40083) reach to the switch 111 this switch forward each packet in different link toward destination node. This means that the traffic between resource and first switch that directly connected to the resource (ingress) was distributed between the switch links. But this scheme has another specification, this specification is that the links between of Ingress and Egress switches must to have an equal hops count (min hop count in 2 or 3 paths) in order to have no packet reordering in destination node.

A. Propose scheme If we use one path in order to send data between cores in network on chip, the communication load between the cores was limited to one link bandwidth. But in some communication like the multimedia we want the more bandwidth than one link bandwidth, thus we used an Arbiter that forwarding data packet to destination node in roundrobin Manner so that we can use the more than one link bandwidth to increasing the communication load of the cores. As shown in Fig. 1, we increase the bandwidth utilization by using sequence number in header of packets in

Figure 2 -Equal hop count between ingress , egress in torus NoCs.

As shown in fig. 2, when two packets reach to ingress switches these packets was distributed between two paths in round robin manner, and these two paths (green and yellow path) have an equal hop count specification.

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B. Hardware Architectures Our NOC is a scalable packet switched communication platform for single chip systems. The NOC architecture consists of two topologies mesh and torus of switches with some resources in 2Dimentional and 3D. Resources Are Heterogeneous or can be homogeneously. A resource can be an intellectual property (IP). We know that because of each switch connects to a node or resource, this type of network is directed network. We consider mesh and torus architectures of 3Dimensional 4*4*4 and 2Dimensional 8*8 architectures with equal switches that shown in Fig.2, Fig.3, Fig.4 and Fig.5 the square nodes stand in IPs and the circle nodes stand in switches. This topology is easily scaled to different sizes.
Figure 5- 3D mesh with 64 switches.

As shown in Fig.2, Fig.3, Fig.4 and Fig.5, one of the widely used NoC topologies is the Mesh and Torus architecture. We analyze the performance of a Mesh and Torus based NoC with proposed scheme in presence of permanent faults With IP routing are adopted. IV. EVALUATIONS

Figure 3- nostrum mesh model for NoC with 64 switches.

We reduce the all parameters as multiply of 1000 in order to support the simulation time. In order to compare of these architectures in term of packet forwarding we consider that the bandwidth between switches is 1Megabit/Sec and the bandwidth between resources and switches is ten times bigger than the bandwidth of switches to switches, this is because of that there is maybe that the other resources communicated with this resources through the network, and the other bandwidth must to be supported by link of resource to switch. We consider that the type of traffic source for each communicated core was UDP, and the bandwidth of the two cores that want to communicate with each other equal to 3Megabit/Sec. thus the bandwidth of one link can't support the traffic between of two cores. We consider that the delay of switch to switch or resource to switch was equal to 10 milliseconds. We consider four parameters communication load, Fault-Tolerant, End to End Delay and Hop count consumption are defined for our evaluation of performance of these architectures. A. Communication Load We consider that two resources node 64 and node 127 was communicate with each other that has the max diameter of the our NoC mesh Architectures, as shown in fig. 3, the traffic that these two core needs can supported in 3 dimensional Mesh and some deal 3 dimensional torus.

Figure 4- three dimensional -torus topology with 64 switches.

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Figure 6- supported bandwidth in 2D 3D Mesh and Torus NoC.

scheme can be consider in first switch (Ingress) that directly connected to traffic source or in all switches. If this scheme just used in ingress switch and a permanent fault was occur near this switch, the bandwidth of the traffic in two dimensional architectures was limited to the one communication path. This means that the bandwidth of one path was dropped, and communication load between the cores was limited to the sum of the bandwidth of the other path that have an equal hop count specification. If this scheme used in all switches, and a fault was occur in middle of network there maybe that no fault occurs, This is because that each of the switch that used this scheme, distribute an incoming traffic into their links toward destination node, thus in middle of the network have the less traffic related to the other portion of the network. C. End to End Delay End to end delay is another parameter that we consider for evaluation the performance of these architectures.

As shown in fig. 6, because of a permanent fault in time 1.2 second occurs, the communication load between of mentioned Resources was reduces, and two Dimentioal architectures using proposed schema just supports the communication load that was twice bigger than one link bandwidth, and triple bandwidth just supports in three dimensional architectures. B. Fault-Tolerant The faults that occur in NoC have two types as below: Permanent Faults: crash failures are permanent faults which occur when a node halts prematurely or a link disconnects, unlike the other network that the resources or link can be replaces or repair, in NoC these faults was permanent fault and can't be replaces or repair thus the traffic must to be rerouted to the other path. Transient Faults: In our simulation, since transient faults can be effectively corrected using the built-in checker processor during run-time, only static permanent faults are modeled and we consider that the transient faults are negligible.

Figure 8- Average end to end delay in four architecture.

As shown in fig.8, the average end to end delay between of mentioned cores in 2D and 3D torus was the less than mesh architecture. This means that the data travels in torus architecture is faster than mesh architectures, with equal switches and resources. D. Hop count Hop count refers to the number of switches through which a data packet passes from source to the destination. Equal hop count in our scheme was considered to we have not packet reordering in destination node. Minimum hop count is cause to faster data transmission between the cores and cause to one architecture was better related to others. The difference of average hop count in these architectures was shown in fig.9.

Figure 7- Lost packets in four architecture.

As shown in fig.7, when a permanent fault occurs in communication path, the number of lost packets in 3D mesh and 3Dtorus architecture was the less than the others. This

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[12] A. Dumitras, "On-Chip Stochastic Communication", Electrical and Computer Engineering, May 1st, 2003 [13] W. Robbins. Redundancy and binning of picoChip processors. Fall Processor Forum, 2004, San Jose, CA. [14] L. Singh Sayana, Prof.M.R.Bhujade, Seminar Report on Network On Chip, Computer Science and Engineering, IIT Bombay, April 1,2008

Figure 9- Average hop count in four architectures.

As shown in fig. 9, the Torus with 2Dimensional has the fewer hops count related to the other architectures. These hop count has not effect on fault or bandwidth. The effect of minimum hop count was in the time to transfer the data and caused to faster data transmission between cores. V. CONCLUSIONS AND FUTUREWORK

This paper, a novel routing for increase communication load between the cores in networks-on-chip has been reported. All of these features make the proposed scheme was suitable for a wide range of applications that need more bandwidth than one link bandwidth. The triple than on link bandwidth can easily support in 3Dimentional NoC. REFERENCES
S. D. Mediratta, J. Draper, Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router , 2007 IEEE [2] S.D. Mediratta, J. Draper, Characterization of a Fault-tolerant NoC Router, 2007 IEEE. [3] X. Zhu, W. Qin, Prototyping a Fault-Tolerant Multiprocessor SoC with Run-time Fault Recovery , DAC 2006, July 2428, 2006, San Francisco, California, USA. [4] Y-R. Sun, S. Kumar, and A. Jantsch, "Simulation and evaluation of a network on chip architecture using ns-2", In Proceedings of the IEEE NorChip Conference, November 2002. [5] M. Sgroi, et al, "Addressing the System-on-a-Chip Interconnect Woes Through Communication-based Design", 38th Design Automation Conference, June, 2001. [6] Luca Benini, Giovanni De Micheli, "Network on Chips: A new SoC Paradigm", IEEE computer, Jan., 2002. [7] Shashi Kumar, et. al, "A Network on Chip Architecture and Design Methodology", IEEE Computer Society Annual Symposium on VLSI, Pittsburgh,Pennsylvania, USA, April 2002. [8] LBNL Network Simulator, http://www-nrg.ee.lbl.gov/ns/ [9] The network simulator ns-2, available at http://www.isi.edu/nsnam/ns/ [10] M. Ali, M. Welzl, A. Adnan, and F. Nadeem, "Using the NS-2 network simulator for evaluating network-on-chips (NoC)," in Proc. IEEE 2nd Int. Conf. Emerging Technol., Nov. 2006, pp. 506-512. [11] D. K. Pradhan. Fault-Tolerant Computer System Design. PrenticeHall, Inc., 1996. [1]