VHDL Projects 2011

)(1
Generic Multiplexer :
. Generic Multiplexer Circuit

n sel m .
) n . ( m GENERIC n
2**n
m = 3 VHDL Quartus II
FPGA . DE2
:
-
-
-
-
n . 2
On/Off X . sel
. y
Pin Assignment !!!
)(2
Priority Encoder :
. 7-Levels Priority Encoder Circuit

0 . 000 VHDL
Quartus II FPGA . DE2
:
- On/Off .
- .
- Pin Assignment !!!
)(3
: Barrel Shifter
) . ( Barrel Shifter
inp shift
1 outp
shift . 0 VHDL Quartus II
FPGA . DE2
:
- On/Off inp . shift
- . outp
)(4
:
.
clk
count 8 . clk .
VHDL Quartus II FPGA
. DE2
:
- Push-Button )
!!! ( .
- . count
)(5
Generic Decoder :
. Generic Decoder Circuit

) sel m ( ) ena ( ) x
n ( . n 2 ) . m = log2(n ena = 0
x 1 ) ( sel
0 1 :
VHDL Quartus II
FPGA . DE2
:
- m = 2 . n = 4
- On/Off sel . ena
- . x
)(6
Generic Parity Detctor :
. Generic Parity Detector Circuit
input ) ( n+1 ) n ( GENERIC

. output output 0
input output 1
input . VHDL Quartus II
FPGA . DE2
:
- . n = 7
- On/Off . input
- . output
)(7
Generic Parity Generator :
. Generic Parity Generator Circuit

input n ) n ( GENERIC
) ( n+1 . output n ) output (
input MSB output 0
input 1
input . ) (
. VHDL Quartus II
FPGA . DE2
:
- . n = 7
- On/Off . input
- . output
)(8
n-by-m Encoder :
. n-by-m
8 x 3 ) y
) . ( 3 = log2(8 x 1
0 ) ( 1 x
. y y ) ZZZ
y . ( High Impedance VHDL
:
- On/Off . x
- . y
)(9
ALU :
8 .
8 (
: ) a 4
8 ( cin
) b 4
sel 4 ) ( .
Arithmetic Unit
sel Logic Unit
sel .
8
) y 4
( MSB ) sel
sel(3) = 0 . ( sel(3) = 1
. DE2
:
a b y 4 !!!
-
- On/Off a b cin sel
- . y
9
)(10
:
0 9 .
) clk (
0 9 . digit
4 . VHDL
:
- Push-Button )
!!! ( .
- . digit
10
)(11
Shift Register :
4 .
) d ( ) clk (
) rst ( . q
d 4 . rst )
. ( clk
. DE2
:
- On/Off . d
- 2 Push-Buttons clk . rst
- DE2 . q
11
)(12
00 99 :
00 99 .
) clk ( ) rst rst
. ( 00
2 7-Segment Displays
BCD . ( Seven Segments Display Code ) SSD
. DE2
:
- 7-Segments DE2
) digit1 ( ) digit2 ( .
12
)(13
) ( :
) ( .
d q 4 . clk
) sel ( q d
) sel = 2 q 3
d . ( q = q3 VHDL Quartus II
FPGA . DE2
:
- sel . INTEGER RANGE 0 TO 3
- On/Off . d
- Push-Button )
!!! ( .
- On/Off . sel
- . q
13
)(14
data 7 zeros 3
data ) zeros
MSB ' . '1
: " "0001010 . ( 3 VHDL
- zeros . INTEGER RANGE 0 To 7

- On/Off . data
- . zeros
14
)(15
Timer 0 min : 00 sec
. 9 min : 59 sec
Timer 0 min : 00 sec . 9 min : 59 sec

clk )
( reset / . start / stop start / stop ''1
0 min : 00 sec
. 9 min : 59 sec
. 50 MHz 3
. 7-Segments VHDL Quartus II
FPGA . DE2
:
- 2 Push-Buttons start / stop . reset
- DE2 50 MHz
. clk 50 MHz !!! 1 Hz
- 3 7-Segments DE2
) ( .
7-Segments
!!! 7-Segments
15
)(16
data 7 ones zeros 3

data ones data
. zeros VHDL Quartus II
FPGA . DE2
- ones zeros INTEGER RANGE 0

. TO 7
- On/Off . data
- DE2 ones
. zeros
16
)(17
Sequence Detctor d
clk . rst . q
" "111 d :
". "111
q ' '1 ' '1
d ' '1 q ' '0 ' '0 . d
. DE2
:
- On/Off DE2 . d
- DE2 . q
17
)(18
( FSM ) Finite States Machine :
.
inp clk
rst outp .
. DE2
:
- On/Off DE2 . inp
- DE2
. outp
18
)(19
: Barrel Shifter
.
inp 8 shift
3 inp outp
8 . inp " "11110000 shift
" ) "010 ( 2 outp " ) "11000000
( . VHDL Quartus II
FPGA . DE2
:
- 8 On/Off DE2 . inp
- 3 On/Off . shift
- 8 ) ( 8 LEDs DE2 . outp
19
)(20
4 :
/ 4 .
: clk rst ena
) u_d ' u_d = '0 '. ( u_d = '1
count 4 . VHDL
:
- On/Off ena . u_d
- 4 DE2
count .
20
)(21
4
:
/ 4 .
: clk rst
ena ) u_d ' u_d = '0
' ( u_d = '1 load
) value 4 (
. count 4 .
. DE2
:
- On/Off DE2
ena u_d load . value
- 4 DE2
count .
21
)(22
( Binary-Coded Decimal ) BCD
) 4 ( :
BCD .
x )
( BCD y )
( BCD cin .
s 4 cout
' '1 . 9
. DE2
:
- On/Off DE2
x y . cin
- 7-Segments DE2
. s
- DE2
. cout
22
)(23
4 :
4 .
A 4
B 4 .
A B ) AeqB : ( A = B AltB
) ( A < B ) AgtB . ( A > B VHDL
:
- On/Off DE2
A.B
- DE2
AeqB AltB . AgtB
23
)(24
Shift Register 4
4 : shift_load
4 .
clock
) reset ( shift_load
) ( s_input ) 4 ( . p_input
shift_load ' '0
s_input
shift_load ' '1 ) 4 (
p_input
) Q 4 ( . VHDL
:
- On/Off DE2
shift_load s_input . p_input
- 2 Push-Buttons reset . clock
- 4 DE2
. Q
24
)(25
BCD BCD0 BCD1
4 clear : enable
BCD .
) clock (
clear enable ' '1 ''0
.
BCD0 BCD1
00 99 .
. DE2
:
- Push-Button . clock
- On/Off clear . enable
- 8 DE2
BCD0 . BCD1
25
)(26
4
:
4 .
S0 S1
) A 4 (
. " S1S0 = "00
" S1S0 = "01
s_input ) ( D0 A0 = s_input
. clock " S1S0 = "10
s_input ) ( D3
A3 = s_input . clock = S1S0
" "11 ) I 4 (
A = I . clock
) reset ( ' '0
A ) ( .
VHDL Quartus II
FPGA . DE2
:
- 2 Push-Buttons clock . reset
- On/Off DE2
S0 S1 s_input . I
- 4 DE2
. A
26
)(27
4
4 .
' clear = '1
) ( load
. increment ' clear = '0 ' load = '1 ) I 4 (
) A 4 ( I
. increment ' clear = '0 = load
' '0 ' increment = '1 .
clear load increment ' '0
. VHDL Quartus II
FPGA . DE2
:
- Push-Button clock .
- On/Off DE2
clear load increment . I
- 4 DE2
. A
27

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VHDL Projects 2011

Hochgeladen von

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Verfügbare Formate

)(1

. Generic Multiplexer Circuit

. 7-Levels Priority Encoder Circuit

. Generic Decoder Circuit

. Generic Parity Detector Circuit

input ) ( n+1 ) n ( GENERIC

. Generic Parity Generator Circuit

- zeros . INTEGER RANGE 0 To 7

Timer 0 min : 00 sec . 9 min : 59 sec

data 7 ones zeros 3

- ones zeros INTEGER RANGE 0

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