MicroC2 eCH04L3dataTrInst

Chapter 4
8051 Family Microcontrollers Instruction Set
Lesson 3
Data Transfer Instructions
Move byte between accumulator (an SFR) and register at a register bank
2011
Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education
MOV Rn, A
Destination Source
Rn
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MOV A, Rn
Destination Source
Rn
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MOV A, Rn; MOV Rn, A

A Bank 3 Bank 2 Bank 1 Bank 0 R7 R6 R5 R4 R3 R2 R1 R0
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Rn
8051
2011
Rn
Rn: n = 0,1, 2, 3,4, 5, 6,or 7, n is as per 3 bits coexisting with 5-bits with opcode
Register n is at the bank defined by RS1 and RS0 at PSW - 00 means Bank 0, -01 bank 1 - 10 bank 2- 11 bank 3
2011 Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education 7
Instruction Execution STEP 1 STEP 2 Fetch opcode-bits Fetch bits for getting the operand(s)
1 clock cycle
Time
Register addressing mode
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Move byte from an SFR/Internal RAM to another direct
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MOV A, direct; MOV Rn, direct; MOV direct, A; MOV direct, Rn
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An SFR or Internal RAM between 00H-7FH

Destination Source
direct
A or Rn
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A Bank 3 Bank 2 Bank 1 Bank 0
or
Rn
8051
Direct addressed SFR 80H-FFH or Internal RAM between 00H7FH

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An SFR or Internal RAM between 00H-7FH

Destination Source
A or Rn
direct
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Instruction Execution STEP 1 STEP 2 Fetch opcode-bits Fetch direct
1 clock cycle
Time
direct addressing mode
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MOV direct, direct
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MOV direct, direct

direct direct
8051
Direct addressed SFR or Internal RAM between 00H-7FH
Direct addressed SFR or Internal RAM between 00H-7FH

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Instruction Execution STEP 1 STEP 2 STEP 3 Fetch opcode-bits Fetch direct Fetch direct
2 clock cycles
Time
both the operands using direct addressing modes
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Move indirect
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MOV A, @Ri; MOV @Ri, A; MOV direct, @Ri; MOV @Ri, direct
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An indirect addressed Internal RAM between 00H-FFH

Destination Source
A or direct
Address pointed by R0 or R1
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indirect
A or direct
8051
Indirect addressed Internal RAM between 00H-FFH
SFR direct addressed between 80H8FH or A register

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An indirect Internal RAM between 00H-FFH

Destination Source
Address pointed by R0 or R1
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A or direct
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or 4
direct R0 or R1
8051
Bank 3 Bank 2 Bank 1 Bank 0
Pointed address Internal RAM between 00HFFH

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Instruction Execution
STEP 1 STEP 2 STEP 3 Fetch opcode-bits Fetch bits for A or direct Fetch bit for i 0 or 1
1 or 2 clock cycle(s)
Time
indirect addressing mode one operand 2 cycles when direct, 1 when A other operand
Instruction Execution 1. No indirect addressing in 8051 instruction for an SFR 2. Only indirect addressing in 8052 instruction Internal RAM between 80H-FFH
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Move immediate, MOV immediate DPTR
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byte
A register
2nd Byte of instruction
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MOV A,#data Example
For moving 08H into A register MOV A, #08H
Fetch opcode and then byte for getting the operand for move
1 clock cycle Time
Sign # specifies that 08H is the immediate succeeding byte is the operand
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Codes in Memory74H, 08H

28
Rn
byte
8051
Rn (R0 or R1 or ...R6 or R7) at Bank 0 or 1or 2 or 3
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MOV Rn,#data Fetch opcode For moving and then byte 08H into Rn for getting the register operand for move MOV Rn, #08H Sign # specifies that 08H is the immediate succeeding byte is the operand
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1 clock cycle Time
Codes in Memory78H-7FH, 08H
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direct
byte
8051
direct address internal RAM 00H7FH or SFR 80HFFH
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MOV direct,#data
For moving 08H into direct Fetch opcode and then bytes for getting the operands
2 clock cycles
Time Codes in Memory75H, 00HFFH, 08H

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MOV direct, #08H Sign # specifies that 08H is the immediate succeeding byte is the operand
2011 Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education
Destination Direct Addressing STEP 2 Fetch byte(s) after the opcode
clock cycle (s) Time
Addressing mode specifies that fetch byte(s) (next to the opcode of 8 bits) specify an address, destination operand is at that address.
indirect
byte
8051
indirect address internal RAM 00HFFH pointed by R0 or R1
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MOV @Ri,#data Fetch opcode For moving and then bits 08H into for getting the indirect operands MOV @Ri, #08H Sign # specifies that 08H is the immediate succeeding byte is the operand
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1 clock cycle Time Codes in Memory76-77H, 08H

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Destination indirect Addressing STEP 2 Fetch bit 0 or 1 for R0 or R1 the opcode
1 clock cycle Time
Addressing mode specifies that fetch byte(s) specify by an address pointed by R0 or R1 at a bank
Immediate Addressing Four type of instructions
A Rn direct for Internal RAM in between

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00H to 7FH or direct for SFR 80HFFH Indirect using R0 or R1

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education 37
Immediate addressing mode for source two-bytes
Lower byte is second byte of the instruction and is for DPL Higher byte is third byte of the instruction and is for DPH
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MOV DPTR, #data16 2 clock Fetch opcode cycles For moving and then 16 08C1H into bits for getting Time DPTR the operands MOV DPTR, #08C1H
Sign # specifies that 08C1H is two immediate succeeding bytes as the operand 2nd Ed. Raj Kamal Microcontrollers-... 2011
Pearson Education
Codes in Memory90H, C1H, 08H

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MOVC and MOVX indirect
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1. Only indirect addressing in 8051 instruction for a byte in external data memory
2. Only indirect addressing in 8051 instruction for a code in internal/external program memory
Always Indirect Addressing mode

Internal/External Program Memory (max. 64kB)
External Data Memory and Ports (max 64kB)
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MOVC A, @A + PC For Fetch opcode transferring bits

addressed code byte into A
C means code memory is used
2 clock cycles Time STEPS 2-3 Code bits in Memory83H

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MOVC A, @A + PC indirectly specify, PC16-bits adds with 8-bits at A register and then new 16-bits point to the code at that address Microcontrollers-... 2nd Ed. Raj Kamal 2011
Pearson Education
MOVC A, @A + DPTR
For transferring addressed code byte into A
2 clock cycles Time STEPS 2-3 Code bits in Memory93H
Fetch opcode bits
MOVC A, @A + DPTR
indirectly specify, DPTR16-bits adds in 8-bits at A register and then 16-bits point to code at that C means code address memory is used Microcontrollers-... 2nd Ed. Raj Kamal 44 2011
Pearson Education
MOVX A, @DPTR For Fetch opcode transferring Sign @ means an external DPTR is a byte into A pointer MOVX A, @DPTR X specifies external memory, byte at DPTR points indirectly to the address for the operand
2 clock cycles
Time
STEP 2
Code bits in MemoryE0H
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MOVX @DPTR, A
For transferring A to a byte at external pointed address
Fetch opcode
Sign @ means DPTR is a pointer
2 clock cycles Time STEP 2

Code bits in MemoryF0H
MOVX @DPTR, A
X specifies external memory, byte at DPTR points indirectly to the address for the operand
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MOVX A, @Ri For Fetch opcode transferring an external byte Sign @ means Ri is a pointer into A MOVX A, @Ri X specifies external memory, byte at Ri points indirectly to an external memory address for the operand
2 clock cycles
Time
STEP 2
Code bits in Memory- E2E3H
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MOVX @Ri, A
For transferring Fetch opcode A to a byte at external pointed Sign @ means Ri is a pointer address MOVX @Ri, A X specifies external memory, byte at Ri points indirectly to the address for the operand
2 clock cycles Time
Code bits in Memory- F2F3H
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Push or Pop direct or Exchange or Swap
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Always direct Addressing mode for Push or Pop

Internal data Memory (00H-7FH) SFR (80H-FFH)
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direct
4
SP
stack
1
8051 Direct address SFR or internal 007FH RAM
Increment SP Move the byte to SP pointed address 3 SP is of 8-bits
Push direct
direct
2 8051 Direct address SFR or internal 00-7FH RAM
3 SP
stack
Move the byte to SP pointed address and decrement SP 4 SP is of 8-bits
Pop direct
Instruction Execution STEP 1 STEP 2 Fetch opcode-bits Fetch byte direct
2 clock cycles
Time direct addressing mode for source operand in push and for destination operand for pop
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Push an SFR or Internal RAM between 00H-7FH

Source Destination stack direct
Pre-increment SP
Pop an SFR or Internal RAM between 00H-7FH

Source Destination direct stack
Post-decrement SP
Exchange of A register byte with other

Internal data Memory (00H-FFH) SFR (80H-FFH)
A register
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A 1 8051 A register
Rn or internal Temp RAM or 3 SFR
XCH A, Rn, XCH A, direct, XCH A, @Ri; exchange bytes

Exchange of A register lower digit with other Internal data Memory (00H-FFH) SFR (80H-FFH)
A register
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bit3-bit0 2 8051 Indirect address internal 00FFH RAM pointed by R0 or R1
3
temp
bit3-bit0 4 1
A register lower 4 bits XCHD A, @Ri; exchange lower digits (4-bits)
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Exchange of A register lower digit with higher digit
A register lower bits
A register higher bits
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bit7-bit4 1 8051 A register higher 4 bits 6
4 temp 5
bit3-bit0
2
A register lower 4 bits
SWAP A; exchange of lower digit (4bits) with higher at A

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Summary
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We learnt 8051 family data transfer instructions move (copy) push pop exchange exchange lower 4-bits

MicroC2 eCH04L3dataTrInst

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Chapter 4

8051 Family Microcontrollers Instruction Set

Data Transfer Instructions

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

MOV A, Rn; MOV Rn, A

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

Register addressing mode

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

Move byte from an SFR/Internal RAM to another direct

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

MOV A, direct; MOV Rn, direct; MOV direct, A; MOV direct, Rn

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

An SFR or Internal RAM between 00H-7FH

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

A Bank 3 Bank 2 Bank 1 Bank 0

Direct addressed SFR 80H-FFH or Internal RAM between 00H7FH

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

An SFR or Internal RAM between 00H-7FH

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

Instruction Execution STEP 1 STEP 2 Fetch opcode-bits Fetch direct

direct addressing mode

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

MOV direct, direct

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

MOV direct, direct

Direct addressed SFR or Internal RAM between 00H-7FH

Direct addressed SFR or Internal RAM between 00H-7FH

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

both the operands using direct addressing modes

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

An indirect addressed Internal RAM between 00H-FFH

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

Indirect addressed Internal RAM between 00H-FFH

SFR direct addressed between 80H8FH or A register

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

An indirect Internal RAM between 00H-FFH

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

Bank 3 Bank 2 Bank 1 Bank 0

Pointed address Internal RAM between 00HFFH

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

Move immediate, MOV immediate DPTR

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

2nd Byte of instruction

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

MOV A,#data Example

For moving 08H into A register MOV A, #08H

1 clock cycle Time

Codes in Memory74H, 08H

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

Rn (R0 or R1 or ...R6 or R7) at Bank 0 or 1or 2 or 3

2nd Byte of instruction

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

1 clock cycle Time

Microcontrollers-... 2nd Ed. Raj Kamal Pearson Education

Codes in Memory78H-7FH, 08H

direct address internal RAM 00H7FH or SFR 80HFFH

2nd Byte of instruction