A-Si TFT LCD Single Chip Driver 240Rgbx320 Resolution and 262K Color Datasheet

ILI9328
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Datasheet
Version: V0.1 Document No.: ILI9328DS_V0.1.pdf
ILI TECHNOLOGY CORP.
4F, No. 2, Tech. 5th Rd., Hsinchu Science Park, Taiwan 300, R.O.C. Tel.886-3-5670095; Fax.886-3-5670096 http://www.ilitek.com
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Table of Contents Section
ILI9328
Page
1. Introduction.................................................................................................................................................... 7 2. Features ........................................................................................................................................................ 7 3. Block Diagram ............................................................................................................................................... 9 4. Pin Descriptions .......................................................................................................................................... 10 5. Pad Arrangement and Coordination............................................................................................................ 14 6. Block Description ........................................................................................................................................ 21 7. System Interface ......................................................................................................................................... 23 7.1. 7.2. Interface Specifications .................................................................................................................. 23 Input Interfaces .............................................................................................................................. 24 7.2.1. 7.2.2. 7.2.3. 7.2.4. 7.3. 7.4. 7.5. i80/18-bit System Interface.................................................................................................. 25 i80/16-bit System Interface.................................................................................................. 26 i80/9-bit System Interface.................................................................................................... 27 i80/8-bit System Interface.................................................................................................... 27
Serial Peripheral Interface (SPI) .................................................................................................... 28 VSYNC Interface............................................................................................................................ 33 RGB Input Interface ....................................................................................................................... 37 7.5.1. 7.5.2. 7.5.3. 7.5.4. 7.5.5. 7.5.6. RGB Interface...................................................................................................................... 38 RGB Interface Timing .......................................................................................................... 39 Moving Picture Mode........................................................................................................... 41 6-bit RGB Interface.............................................................................................................. 42 16-bit RGB Interface............................................................................................................ 43 18-bit RGB Interface............................................................................................................ 43
7.6. 8.1. 8.2.
Interface Timing.............................................................................................................................. 46 Registers Access............................................................................................................................ 47 Instruction Descriptions.................................................................................................................. 50 8.2.1. 8.2.2. 8.2.3. 8.2.4. 8.2.5. 8.2.6. 8.2.7. 8.2.8. 8.2.9. Index (IR)............................................................................................................................. 52 Driver Output Control (R01h) .............................................................................................. 52 LCD Driving Wave Control (R02h) ...................................................................................... 53 Entry Mode (R03h) .............................................................................................................. 54 Resizing Control Register (R04h)........................................................................................ 56 Display Control 1 (R07h) ..................................................................................................... 57 Display Control 2 (R08h) ..................................................................................................... 58 Display Control 3 (R09h) ..................................................................................................... 59 Display Control 4 (R0Ah)..................................................................................................... 60
8. Register Descriptions .................................................................................................................................. 47
8.2.10. RGB Display Interface Control 1 (R0Ch)............................................................................. 60 8.2.11. Frame Marker Position (R0Dh) ........................................................................................... 61 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 2 of 106 Version: 0.1
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color
ILI9328
8.2.12. RGB Display Interface Control 2 (R0Fh) ............................................................................. 62 8.2.13. Power Control 1 (R10h)....................................................................................................... 62 8.2.14. Power Control 2 (R11h) ....................................................................................................... 63 8.2.15. Power Control 3 (R12h)....................................................................................................... 64 8.2.16. Power Control 4 (R13h)....................................................................................................... 65 8.2.17. GRAM Horizontal/Vertical Address Set (R20h, R21h) ........................................................ 65 8.2.18. Write Data to GRAM (R22h)................................................................................................ 66 8.2.19. Read Data from GRAM (R22h) ........................................................................................... 66 8.2.20. Power Control 7 (R29h)....................................................................................................... 68 8.2.21. Frame Rate and Color Control (R2Bh)................................................................................ 69 8.2.22. Gamma Control (R30h ~ R3Dh).......................................................................................... 70 8.2.23. Horizontal and Vertical RAM Address Position (R50h, R51h, R52h, R53h) ....................... 70 8.2.24. Gate Scan Control (R60h, R61h, R6Ah) ............................................................................. 71 8.2.25. Partial Image 1 Display Position (R80h).............................................................................. 74 8.2.26. Partial Image 1 RAM Start/End Address (R81h, R82h)....................................................... 74 8.2.27. Partial Image 2 Display Position (R83h).............................................................................. 74 8.2.28. Partial Image 2 RAM Start/End Address (R84h, R85h)....................................................... 74 8.2.29. Panel Interface Control 1 (R90h)......................................................................................... 75 8.2.30. Panel Interface Control 2 (R92h)......................................................................................... 75 8.2.31. Panel Interface Control 4 (R95h)......................................................................................... 75 8.2.32. Panel Interface Control 5 (R97h)......................................................................................... 76 8.2.33. OTP VCM Programming Control (RA1h) ............................................................................ 76 8.2.34. OTP VCM Status and Enable (RA2h) ................................................................................. 77 8.2.35. OTP Programming ID Key (RA5h) ...................................................................................... 77 9. OTP Programming Flow.............................................................................................................................. 78 10. GRAM Address Map & Read/Write ............................................................................................................. 79 11. Window Address Function........................................................................................................................... 85 12. Gamma Correction...................................................................................................................................... 86 13. Application................................................................................................................................................... 91 13.1. Configuration of Power Supply Circuit ........................................................................................... 91 13.2. Display ON/OFF Sequence ........................................................................................................... 93 13.3. Standby and Sleep Mode ............................................................................................................... 94 13.4. Power Supply Configuration .......................................................................................................... 95 13.5. Voltage Generation ........................................................................................................................ 96 13.6. Applied Voltage to the TFT panel................................................................................................... 97 13.7. Partial Display Function ................................................................................................................. 97 13.8. Resizing Function........................................................................................................................... 98 14. Electrical Characteristics........................................................................................................................... 101 14.1. Absolute Maximum Ratings ......................................................................................................... 101 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9328
14.2. DC Characteristics ....................................................................................................................... 102 14.3. Reset Timing Characteristics ....................................................................................................... 102 14.4. AC Characteristics ....................................................................................................................... 102 14.4.1. i80-System Interface Timing Characteristics ..................................................................... 102 14.4.2. Serial Data Transfer Interface Timing Characteristics....................................................... 103 14.4.3. RGB Interface Timing Characteristics ............................................................................... 104 15. Revision History ........................................................................................................................................ 106
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Figures
ILI9328
FIGURE1 SYSTEM INTERFACE AND RGB INTERFACE CONNECTION .................................................................................... 24 FIGURE2 18-BIT SYSTEM INTERFACE DATA FORMAT ......................................................................................................... 25 FIGURE3 16-BIT SYSTEM INTERFACE DATA FORMAT ......................................................................................................... 26 FIGURE4 9-BIT SYSTEM INTERFACE DATA FORMAT ........................................................................................................... 27 FIGURE5 8-BIT SYSTEM INTERFACE DATA FORMAT ........................................................................................................... 28 FIGURE6 DATA TRANSFER SYNCHRONIZATION IN 8/9-BIT SYSTEM INTERFACE.................................................................. 28 FIGURE 7 DATA FORMAT OF SPI INTERFACE ..................................................................................................................... 30 FIGURE8 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) ............................................................... 31 FIGURE9 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI), TRI=1 AND DFM=10).................... 32 FIGURE10 DATA TRANSMISSION THROUGH VSYNC INTERFACE)....................................................................................... 33 FIGURE11 MOVING PICTURE DATA TRANSMISSION THROUGH VSYNC INTERFACE ............................................................ 33 FIGURE12 OPERATION THROUGH VSYNC INTERFACE ...................................................................................................... 34 FIGURE13 TRANSITION FLOW BETWEEN VSYNC AND INTERNAL CLOCK OPERATION MODES ............................................ 36 FIGURE14 RGB INTERFACE DATA FORMAT ...................................................................................................................... 37 FIGURE15 GRAM ACCESS AREA BY RGB INTERFACE ..................................................................................................... 38 FIGURE16 TIMING CHART OF SIGNALS IN 18-/16-BIT RGB INTERFACE MODE .................................................................. 39 FIGURE17 TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MODE ............................................................................ 40 FIGURE18 EXAMPLE OF UPDATE THE STILL AND MOVING PICTURE .................................................................................... 41 FIGURE19 INTERNAL CLOCK OPERATION/RGB INTERFACE MODE SWITCHING ................................................................... 44 FIGURE20 GRAM ACCESS BETWEEN SYSTEM INTERFACE AND RGB INTERFACE .............................................................. 45 FIGURE21 RELATIONSHIP BETWEEN RGB I/F SIGNALS AND LCD DRIVING SIGNALS FOR PANEL ..................................... 46 FIGURE22 REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI)...................................................................... 47 FIGURE23 REGISTER SETTING WITH I80 SYSTEM INTERFACE ............................................................................................ 48 FIGURE 24 REGISTER READ/WRITE TIMING OF I80 SYSTEM INTERFACE ........................................................................... 49 FIGURE25 GRAM ACCESS DIRECTION SETTING ............................................................................................................... 54 FIGURE28 16-BIT MPU SYSTEM INTERFACE DATA FORMAT............................................................................................. 55 FIGURE29 8-BIT MPU SYSTEM INTERFACE DATA FORMAT............................................................................................... 56 FIGURE 30 DATA READ FROM GRAM THROUGH READ DATA REGISTER IN 18-/16-/9-/8-BIT INTERFACE MODE .............. 67 FIGURE 31 GRAM DATA READ BACK FLOW CHART ........................................................................................................ 68 FIGURE 32 GRAM ACCESS RANGE CONFIGURATION ........................................................................................................ 71 FIGURE33 GRAM READ/WRITE TIMING OF I80-SYSTEM INTERFACE ............................................................................... 79 FIGURE34 I80-SYSTEM INTERFACE WITH 18-/16-/9-BIT DATA BUS (SS=0, BGR=0) ................................................. 81 FIGURE35 I80-SYSTEM INTERFACE WITH 8-BIT DATA BUS (SS=0, BGR=0) .............................................................. 82 FIGURE 36 I80-SYSTEM INTERFACE WITH 18-/9-BIT DATA BUS (SS=1, BGR=1) ....................................................... 84 FIGURE 37 GRAM ACCESS WINDOW MAP ....................................................................................................................... 85 FIGURE 38 GRAYSCALE VOLTAGE GENERATION ............................................................................................................... 86 FIGURE 39 GRAYSCALE VOLTAGE ADJUSTMENT .............................................................................................................. 87 FIGURE 40 GAMMA CURVE ADJUSTMENT ......................................................................................................................... 88 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9328
FIGURE 41 RELATIONSHIP BETWEEN SOURCE OUTPUT AND VCOM ................................................................................. 90 FIGURE 42 RELATIONSHIP BETWEEN GRAM DATA AND OUTPUT LEVEL.......................................................................... 90 FIGURE 43 POWER SUPPLY CIRCUIT BLOCK ...................................................................................................................... 91 FIGURE 44 DISPLAY ON/OFF REGISTER SETTING SEQUENCE ............................................................................................ 93 FIGURE 45 STANDBY/SLEEP MODE REGISTER SETTING SEQUENCE................................................................................... 94 FIGURE 46 POWER SUPPLY ON/OFF SEQUENCE ............................................................................................................... 95 FIGURE 47 VOLTAGE CONFIGURATION DIAGRAM ............................................................................................................. 96 FIGURE 48 VOLTAGE OUTPUT TO TFT LCD PANEL .......................................................................................................... 97 FIGURE 49 PARTIAL DISPLAY EXAMPLE ............................................................................................................................ 98 FIGURE 50 DATA TRANSFER IN RESIZING ........................................................................................................................... 99 FIGURE 51 RESIZING EXAMPLE ......................................................................................................................................... 99 FIGURE 52 I80-SYSTEM BUS TIMING ............................................................................................................................... 103 FIGURE 53 SPI SYSTEM BUS TIMING ............................................................................................................................... 104 FIGURE54 RGB INTERFACE TIMING ................................................................................................................................ 105
ILI9328
1. Introduction
ILI9328 is a 262,144-color one-chip SoC driver for a-TFT liquid crystal display with resolution of 240RGBx320 dots, comprising a 720-channel source driver, a 320-channel gate driver, 172,800 bytes RAM for graphic data of 240RGBx320 dots, and power supply circuit. ILI9328 has four kinds of system interfaces which are i80-system MPU interface (8-/9-/16-/18-bit bus width), VSYNC interface (system interface + VSYNC, internal clock, DB[17:0]), serial data transfer interface (SPI) and RGB 6-/16-/18-bit interface (DOTCLK, VSYNC, HSYNC, ENABLE, DB[17:0]). In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption. ILI9328 can operate with 1.65V I/O interface voltage, and an incorporated voltage follower circuit to generate voltage levels for driving an LCD. The ILI9328 also supports a function to display in 8 colors and a sleep mode, allowing for precise power control by software and these features make the ILI9328 an ideal LCD driver for medium or small size portable products such as digital cellular phones, smart phone, PDA and PMP where long battery life is a major concern.
2. Features
Single chip solution for a liquid crystal QVGA TFT LCD display 240RGBx320-dot resolution capable with real 262,144 display color Support MVA (Multi-domain Vertical Alignment) wide view display Incorporate 720-channel source driver and 320-channel gate driver Internal 172,800 bytes graphic RAM High-speed RAM burst write function System interfaces i80 system interface with 8-/ 9-/16-/18-bit bus width Serial Peripheral Interface (SPI) RGB interface with 6-/16-/18-bit bus width (VSYNC, HSYNC, DOTCLK, ENABLE, DB[17:0]) VSYNC interface (System interface + VSYNC) Internal oscillator and hardware reset Resizing function (1/2, 1/4) Reversible source/gate driver shift direction Window address function to specify a rectangular area for internal GRAM access Abundant functions for color display control -correction function enabling display in 262,144 colors Line-unit vertical scrolling function The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9328
Partial drive function, enabling partially driving an LCD panel at positions specified by user Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) Power saving functions 8-color mode standby mode sleep mode Low -power consumption architecture Low operating power supplies: IOVcc = 1.65V ~ 3.3 V (interface I/O) Vci = 2.5V ~ 3.3 V (analog) LCD Voltage drive: Source/VCOM power supply voltage DDVDH - GND = 4.5V ~ 6.0 VCL GND = -2.0V ~ -3.0V VCI VCL 6.0V Gate driver output voltage VGH - GND = 10V ~ 20V VGL GND = -5V ~ -15V VGH VGL 32V VCOM driver output voltage VCOMH = 3.0V ~ (DDVDH-0.2)V VCOML = (VCL+0.5)V ~ 0V VCOMH-VCOML 6.0V a-TFT LCD storage capacitor: Cst only
ILI9328
3. Block Diagram
IOVCC IM[3:0] nRESET nCS nWR/SCL nRD RS SDI SDO DB[17:0] HSYNC VSYNC DOTCLK ENABLE TEST1 TEST2 TEST3 TS[8:0]
Index Register (IR) MPU I/F 18-bit 16-bit 9-bit 8-bit SPI I/F RGB I/F 18-bit 16-bit 6-bit VSYNC I/F
18 8 18
Control Register (CR)
Address Counter (AC)
LCD Source Driver
S[720:1]
Graphics Operation
18
V63 ~ 0 18
Read Latch
72
Write Latch
72
Grayscale Reference Voltage
VREG1OUT
VGS
VCC VDDD GND DUMMY1~15
Regulator
Graphics RAM (GRAM)
DUMMY20~27
RC-OSC.
Timing Controller
LCD Gate Driver
G[320:1]
VCI VCI1 GND
Charge-pump Power Circuit
VCOM Generator
VCOM
C21-
C21+
DDVDH
C22+
C11-
C22-
VCOMH
C11+
VCL
VCOML
C12-
C13-
C12+
C13+
VGH VGL
ILI9328
4. Pin Descriptions
Pin Name I/O Type Descriptions Input Interface Select the MPU system interface mode
IM3 0 0 0 0 IM2 0 0 0 0 1 1 0 0 0 0 1 IM1 0 0 1 1 0 1 0 0 1 1 * IM0 0 1 0 1 ID * 0 1 0 1 * MPU-Interface Mode Setting invalid Setting invalid i80-system 16-bit interface i80-system 8-bit interface Serial Peripheral Interface (SPI) Setting invalid Setting invalid Setting invalid i80-system 18-bit interface i80-system 9-bit interface Setting invalid DB[17:0] DB[17:9] DB[17:10], DB[8:1] DB[17:10] SDI, SDO DB Pin in use
IM3, IM2, IM1, IM0/ID
IOVcc
0 1 1 1 1 1
nCS
MPU IOVcc
RS
MPU IOVcc
nWR/SCL
MPU IOVcc
When the serial peripheral interface is selected, IM0 pin is used for the device code ID setting. A chip select signal. Low: the ILI9328 is selected and accessible High: the ILI9328 is not selected and not accessible Fix to the GND level when not in use. A register select signal. Low: select an index or status register High: select a control register Fix to either IOVcc or GND level when not in use. A write strobe signal and enables an operation to write data when the signal is low. Fix to either IOVcc or GND level when not in use. SPI Mode: Synchronizing clock signal in SPI mode. A read strobe signal and enables an operation to read out data when the signal is low. Fix to either IOVcc or GND level when not in use. A reset pin. Initializes the ILI9328 with a low input. Be sure to execute a power-on reset after supplying power. SPI interface input pin. The data is latched on the rising edge of the SCL signal. SPI interface output pin. The data is outputted on the falling edge of the SCL signal. Let SDO as floating when not used. An 18-bit parallel bi-directional data bus for MPU system interface mode 8-bit I/F: DB[17:10] is used. 9-bit I/F: DB[17:9] is used. 16-bit I/F: DB[17:10] and DB[8:1] is used. 18-bit I/F: DB[17:0] is used. 18-bit parallel bi-directional data bus for RGB interface operation 6-bit RGB I/F: DB[17:12] are used.
nRD
MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc
nRESET SDI
I I
SDO
DB[17:0]
I/O
MPU IOVcc
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Pin Name I/O Type Descriptions 16-bit RGB I/F: DB[17:13] and DB[11:1] are used. 18-bit RGB I/F: DB[17:0] are used. Unused pins must be fixed to GND level. Data ENEABLE signal for RGB interface operation. Low: Select (access enabled) High: Not select (access inhibited) The EPL bit inverts the polarity of the ENABLE signal.
ILI9328
ENABLE
MPU IOVcc
DOTCLK
MPU IOVcc
VSYNC
MPU IOVcc
HSYNC
MPU IOVcc MPU IOVcc
FMARK
S720~S1
LCD
G320~G1
LCD
VCOM VCOMH VCOML VGS
O O O I
Vci GND
I I
Vci1
DDVDH
TFT common electrode Stabilizing capacitor Stabilizing capacitor GND or Reference level for the grayscale voltage generating circuit. The VGS external level can be changed by connecting to an external resistor. resistor Charge-pump and Regulator Circuit Power A supply voltage to the analog circuit. Connect to an external power supply supply of 2.5 ~ 3.3V. Power GND for the analog side: GND = 0V. In case of COG, connect to supply GND on the FPC to prevent noise. An internal reference voltage for the step-up circuit1. The amplitude between Vci and GND is determined by the VC[2:0] Stabilizing bits. capacitor Make sure to set the Vci1 voltage so that the DDVDH, VGH and VGL voltages are set within the respective specification. Stabilizing Power supply for the source driver and Vcom drive.
Fix to either IOVcc or GND level when not in use. Dot clock signal for RGB interface operation. DPL = 0: Input data on the rising edge of DOTCLK DPL = 1: Input data on the falling edge of DOTCLK Fix to the GND level when not in use Frame synchronizing signal for RGB interface operation. VSPL = 0: Active low. VSPL = 1: Active high. Fix to the GND level when not in use. Line synchronizing signal for RGB interface operation. HSPL = 0: Active low. HSPL = 1: Active high. Fix to the GND level when not in use Output a frame head pulse signal. The FMARK signal is used when writing RAM data in synchronization with frame. Leave the pin open when not in use. LCD Driving signals Source output voltage signals applied to liquid crystal. To change the shift direction of signal outputs, use the SS bit. SS = 0, the data in the RAM address h00000 is output from S1. SS = 1, the data in the RAM address h00000 is output from S720. S1, S4, S7, display red (R), S2, S5, S8, ... display green (G), and S3, S6, S9, ... display blue (B) (SS = 0). Gate line output signals. VGH: the level selecting gate lines VGL: the level not selecting gate lines A supply voltage to the common electrode of TFT panel. VCOM is AC voltage alternating signal between the VCOMH and VCOML levels. The high level of VCOM AC voltage. Connect to a stabilizing capacitor. The low level of VCOM AC voltage. Adjust the VCOML level with the VDV bits. Connect to a stabilizing capacitor.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Pin Name VGH VGL VCL C11+, C11C12+, C12C13+, C13C21+, C21C22+, C22I/O O O O I/O I/O Type capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Step-up capacitor Step-up capacitor Descriptions Power supply for the gate driver. Power supply for the gate driver. VcomL driver power supply.
ILI9328
VCL = 0.5 ~ VCI . Place a stabilizing capacitor between GND Capacitor connection pins for the step-up circuit 1. Capacitor connection pins for the step-up circuit 2. Output voltage generated from the reference voltage.
VREG1OUT
I/O
Stabilizing capacitor
IOVcc
Power supply
VDDD GND DUMMY1~ 15 DUMMY20 ~ 27 IOGNDDUM TESTO1~16 TEST1, 2, 3 TS0~8
O I
Power Power supply GND Open IOGND OPEN
The voltage level is set with the VRH bits. VREG1OUT is (1) a source driver grayscale reference voltage, (2) VcomH level reference voltage, and (3) Vcom amplitude reference voltage. Connect to a stabilizing capacitor. VREG1OUT = 3.0 ~ (DDVDH 0.2)V. Power Pads A supply voltage to the interface pins: IM[3:0], nRESET, nCS, nWR, nRD, RS, DB[17:0], VSYNC, HSYNC, DOTCLK, ENABLE, SCL, SDI, SDO. IOVcc = 1.65 ~ 3.3V and Vcc IOVcc. In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to prevent noise. Digital circuit power pad. Connect these pins with the 1uF capacitor. GND = 0V. Test Pads Dummy pad. Leave these pins as open. GND pin. Test pins. Leave them open. Test pins (internal pull low). Connect to GND or leave these pins as open. Test pins (internal pull low). Leave them open.
O O I I
Liquid crystal power supply specifications Table 1 No. 1 2 3 4 5 Item TFT Source Driver TFT Gate Driver TFT Displays Capacitor Structure S1 ~ S720 Liquid Crystal Drive G1 ~ G320 Output VCOM IOVcc Input Voltage Vci Description 720 pins (240 x RGB) 320 pins Cst structure only (Common VCOM) V0 ~ V63 grayscales VGH - VGL VCOMH - VCOML: Amplitude = electronic volumes 1.65 ~ 3.30V 2.50 ~ 3.30V
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color DDVDH VGH VGL VCL VGH - VGL Vci - VCL DDVDH VGH VGL VCL 4.5V ~ 6.0V 10V ~ 20V -5V ~ -15V -2.0V ~ -3.0V Max. 32V Max. 6.0V Vci1 x2 Vci1 x4, x5, x6 Vci1 x-3, x-4, x-5 Vci1 x-1
ILI9328
Liquid Crystal Voltages
Drive
Internal Step-up Circuits
ILI9328
4.1. Pad Arrangement and Coordination

Chip Size: 17820um x 870um Chip thickness : 280um or 400um (typ.) Pad Location: Pad Center. Coordinate Origin: Chip center Au bump height: 15um (typ.) Au Bump Size: 1. 16um x 98um Gate: G1 ~ G320 Source: S1 ~ S720 2. 50um x 80um Input Pads Pad 1 to 243.
DUMMY1 TEST1 IO G NDDUM TESTO 1 TESTO 2 TESTO 3 IM0/ID IM1 IM2 IM3 TEST2 TESTO 4 TESTO 5 TESTO 6 TESTO 7 TESTO 8 TESTO 9 TESTO 10 nRESET nRESET VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 TESTO 11 DB 12 DB 11 DB 10 DB9 DB8 TEST3 TESTO 12 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 TESTO 13 SDO SDI nRD nWR/SCL RS nCS TESTO 14 TESTO 15 FMARK TESTO 16 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 DUMMY 2 IO VCC IO VCC IO VCC IO VCC IO VCC IO VCC VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD DUMMY3 G ND G ND G ND G ND G ND G ND GND GND VGS VGS GND GND GND GND GND GND GND GND GND GND DUMMY 4 DUMMY 5 DUMMY 6 VCOM VCOM VCOM VCO M VCO M VCO M VCO M VCO MH VCO MH VCO MH VCO MH VCO MH VCO MH VCO ML VCO ML VCO ML VCO ML VREG 1O UT VREG 1O UT VREG 1O UT DUMMY 7 DUMMY 8 DUMMY 9 VCL VCL VCL VCL VCL DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCI1 VCI1 VCI1 VCI VCI VCI VCI VCI VCI
DUM MY 27 G319 G317 G315 G313 G311 G309 G307 G305 G303
Alignment Marks
15 10 10 20 15
.
S353 S354 S355 S356 S357 S358 S359 S360 DUMM Y 24
1 1 0
2 0 3 0 4 0 5 0 6 0 7 0 8 0
G17 G15 G13 G11 G9 G7 G5 G3 G1 DUMMY 26 DUMM Y 25 S1 S2 S3 S4 S5 S6 S7 S8 S9
Face Up (Bump View)
9 0 1 0 0
15 20 15
1 1 0 1 2 0 1 3 0
y
DUMM Y 23 S361 S362 S363 S364 S365 S366 S367 S368 S369
Alignment Mark: A1
1 4 0 1 5 0
10 10 15
VCI VCI DUMMY10 DUMMY11 C12C12C12C12C12C12+ C12+ C12+ C12+ C12+ C11C11C11C11C11C11+ C11+ C11+ C11+ C11+ VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL GND GND GND VGH VGH VGH VG H VG H VG H DUMMY 12 DUMMY 13 C13C13C13C13C13+ C13+ C13+ C13+ C21C21C21C21C21C21C21C21+ C21+ C21+ C21+ C21+ C21+ C21+ C22C22C22C22C22C22C22C22+ C22+ C22+ C22+ C22+ C22+ C22+ DUMMY14 DUMMY15
.
S712 S713 S714 S715 S716 S717 S718 S719 S720 DUM MY 22 DUM MY 21 G2 G4 G6 G8 G10 G12 G14 G16 G18
15
20
15
VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI
1 6 0 1 7 0
20 15
1 8 0 1 9 0
Alignment Mark: A2
G304 G306 G308 G310 G312 G314 G316 G318 G320 DUM MY 20
2 0 0 2 1 0 2 2 0 2 3 0
Bump View
2 4 0 2 4 3
ILI9328
Y No. 241 Name C22+ X 8470 8540 8610 8659 8643 8627 8611 8595 8579 8563 8547 8531 8515 8499 8483 8467 8451 8435 8419 8403 8387 8371 8355 8339 8323 8307 8291 8275 8259 8243 8227 8211 8195 8179 8163 8147 8131 8115 8099 8083 8067 8051 8035 8019 8003 7987 7971 7955 7939 7923 7907 7891 7875 7859 7843 7827 7811 7795 7779 7763 Y -307.5 -307.5 -307.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Name DUMMY1 TEST1 IOGNDDUM TESTO1 TESTO2 TESTO3 IM0/ID IM1 IM2 IM3 TEST2 TESTO4 TESTO5 TESTO6 TESTO7 TESTO8 TESTO9 TESTO10 nRESET nRESET VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 TESTO11 DB12 DB11 DB10 DB9 DB8 TEST3 TESTO12 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 TESTO13 SDO SDI nRD nWR/SCL RS nCS TESTO14 TESTO15 FMARK TESTO16 TS8 TS7 TS6 TS5
X -8610 -8540 -8470 -8400 -8330 -8260 -8190 -8120 -8050 -7980 -7910 -7840 -7770 -7700 -7630 -7560 -7490 -7420 -7350 -7280 -7210 -7140 -7070 -7000 -6905 -6825 -6745 -6665 -6585 -6495 -6405 -6325 -6245 -6165 -6085 -5990 -5920 -5825 -5745 -5665 -5585 -5505 -5425 -5345 -5265 -5180 -5110 -5040 -4970 -4900 -4830 -4760 -4690 -4620 -4550 -4480 -4410 -4340 -4270 -4200
Y -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5
No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Name TS4 TS3 TS2 TS1 TS0 DUMMY2 IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD DUMMY3 GND GND GND GND GND GND GND GND VGS VGS GND GND GND GND GND GND GND GND GND GND DUMMY4 DUMMY5 DUMMY6 VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH
No. 121 122 123 124
Name VCOML VCOML VCOML VCOML
X 70 140 210 280 350 420 490 560 630 700 770 840 910 980 1050 1120 1190 1260 1330 1400 1470 1540 1610 1680 1750 1820 1890 1960 2030 2100 2170 2240 2310 2380 2450 2520 2590 2660 2730 2800 2870 2940 3010 3080 3150 3220 3290 3360 3430 3500 3570 3640 3710 3780 3850 3920 3990 4060 4130 4200
Y -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5
No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203
Name C11+ C11+ C11+ C11+ VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL GND GND GND VGH VGH VGH VGH VGH VGH
-4130 -307.5 -4060 -307.5 -3990 -307.5 -3920 -307.5 -3850 -307.5 -3780 -307.5 -3710 -307.5 -3640 -307.5 -3570 -307.5 -3500 -307.5 -3430 -307.5 -3360 -307.5 -3290 -307.5 -3220 -307.5 -3150 -307.5 -3080 -307.5 -3010 -307.5 -2940 -307.5 -2870 -307.5 -2800 -307.5 -2730 -307.5 -2660 -307.5 -2590 -307.5 -2520 -307.5 -2450 -307.5 -2380 -307.5 -2310 -307.5 -2240 -307.5 -2170 -307.5 -2100 -307.5 -2030 -307.5 -1960 -307.5 -1890 -307.5 -1820 -307.5 -1750 -307.5 -1680 -307.5 -1610 -307.5 -1540 -307.5 -1470 -307.5 -1400 -307.5 -1330 -307.5 -1260 -307.5 -1190 -307.5 -1120 -307.5 -1050 -307.5 -980 -910 -840 -770 -700 -630 -560 -490 -420 -350 -280 -210 -140 -70 0 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5 -307.5
4270 -307.5 4340 -307.5 4410 -307.5 4480 -307.5 4550 -307.5 4620 -307.5 4690 -307.5 4760 -307.5 4830 -307.5 4900 -307.5 4970 -307.5 5040 -307.5 5110 -307.5 5180 -307.5 5250 -307.5 5320 -307.5 5390 -307.5 5460 -307.5 5530 -307.5 5600 -307.5 5670 -307.5 5740 -307.5 5810 -307.5 5880 -307.5 5950 -307.5 6020 -307.5 6090 -307.5 6160 -307.5 6230 -307.5 6300 -307.5 6370 -307.5 6440 -307.5 6510 -307.5 6580 -307.5 6650 -307.5 6720 -307.5 6790 -307.5 6860 -307.5 6930 -307.5 7000 -307.5 7070 -307.5 7140 -307.5 7210 -307.5 7280 -307.5 7350 -307.5 7420 -307.5 7490 -307.5 7560 -307.5 7630 -307.5 7700 -307.5 7770 -307.5 7840 -307.5 7910 -307.5 7980 -307.5 8050 -307.5 8120 -307.5 8190 -307.5 8260 -307.5 8330 -307.5 8400 -307.5
242 DUMMY14 243 DUMMY15 244 DUMMY20 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 G320 G318 G316 G314 G312 G310 G308 G306 G304 G302 G300 G298 G296 G294 G292 G290 G288 G286 G284 G282 G280 G278 G276 G274 G272 G270 G268 G266 G264 G262 G260 G258 G256 G254 G252 G250 G248 G246 G244 G242 G240 G238 G236 G234 G232 G230 G228 G226 G224 G222 G220 G218 G216 G214 G212 G210
125 VREG1OUT 126 VREG1OUT 127 VREG1OUT 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 DUMMY7 DUMMY8 DUMMY9 VCL VCL VCL VCL VCL DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCI1 VCI1 VCI1 VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI
204 DUMMY12 205 DUMMY13 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 C13C13C13C13C13+ C13+ C13+ C13+ C21C21C21C21C21C21C21C21+ C21+ C21+ C21+ C21+ C21+ C21+ C22C22C22C22C22C22C22C22+ C22+ C22+ C22+ C22+ C22+
163 DUMMY10 164 DUMMY11 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 C12C12C12C12C12C12+ C12+ C12+ C12+ C12+ C11C11C11C11C11C11+
ILI9328
Y 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 No. 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 Name S586 S585 S584 S583 S582 S581 S580 S579 S578 S577 S576 S575 S574 S573 S572 S571 S570 S569 S568 S567 S566 S565 S564 S563 S562 S561 S560 S559 S558 S557 S556 S555 S554 S553 S552 S551 S550 S549 S548 S547 S546 S545 S544 S543 S542 S541 S540 S539 S538 S537 S536 S535 S534 S533 S532 S531 S530 S529 S528 S527 X 3887 3871 3855 3839 3823 3807 3791 3775 3759 3743 3727 3711 3695 3679 3663 3647 3631 3615 3599 3583 3567 3551 3535 3519 3503 3487 3471 3455 3439 3423 3407 3391 3375 3359 3343 3327 3311 3295 3279 3263 3247 3231 3215 3199 3183 3167 3151 3135 3119 3103 3087 3071 3055 3039 3023 3007 2991 2975 2959 2943 Y 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5
No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360
Name G208 G206 G204 G202 G200 G198 G196 G194 G192 G190 G188 G186 G184 G182 G180 G178 G176 G174 G172 G170 G168 G166 G164 G162 G160 G158 G156 G154 G152 G150 G148 G146 G144 G142 G140 G138 G136 G134 G132 G130 G128 G126 G124 G122 G120 G118 G116 G114 G112 G110 G108 G106 G104 G102 G100 G98 G96 G94 G92 G90
X 7747 7731 7715 7699 7683 7667 7651 7635 7619 7603 7587 7571 7555 7539 7523 7507 7491 7475 7459 7443 7427 7411 7395 7379 7363 7347 7331 7315 7299 7283 7267 7251 7235 7219 7203 7187 7171 7155 7139 7123 7107 7091 7075 7059 7043 7027 7011 6995 6979 6963 6947 6931 6915 6899 6883 6867 6851 6835 6819 6803
Y 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5
No. 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420
Name G88 G86 G84 G82 G80 G78 G76 G74 G72 G70 G68 G66 G64 G62 G60 G58 G56 G54 G52 G50 G48 G46 G44 G42 G40 G38 G36 G34 G32 G30 G28 G26 G24 G22 G20 G18 G16 G14 G12 G10 G8 G6 G4 G2 DUMMY21 DUMMY22 S720 S719 S718 S717 S716 S715 S714 S713 S712 S711 S710 S709 S708 S707
X 6787 6771 6755 6739 6723 6707 6691 6675 6659 6643 6627 6611 6595 6579 6563 6547 6531 6515 6499 6483 6467 6451 6435 6419 6403 6387 6371 6355 6339 6323 6307 6291 6275 6259 6243 6227 6211 6195 6179 6163 6147 6131 6115 6099 6083 6047 6031 6015 5999 5983 5967 5951 5935 5919 5903 5887 5871 5855 5839 5823
Y 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5
No. 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480
Name S706 S705 S704 S703 S702 S701 S700 S699 S698 S697 S696 S695 S694 S693 S692 S691 S690 S689 S688 S687 S686 S685 S684 S683 S682 S681 S680 S679 S678 S677 S676 S675 S674 S673 S672 S671 S670 S669 S668 S667 S666 S665 S664 S663 S662 S661 S660 S659 S658 S657 S656 S655 S654 S653 S652 S651 S650 S649 S648 S647
X 5807 5791 5775 5759 5743 5727 5711 5695 5679 5663 5647 5631 5615 5599 5583 5567 5551 5535 5519 5503 5487 5471 5455 5439 5423 5407 5391 5375 5359 5343 5327 5311 5295 5279 5263 5247 5231 5215 5199 5183 5167 5151 5135 5119 5103 5087 5071 5055 5039 5023 5007 4991 4975 4959 4943 4927 4911 4895 4879 4863
Y 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5
No. 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540
X 4847 4831 4815 4799 4783 4767 4751 4735 4719 4703 4687 4671 4655 4639 4623 4607 4591 4575 4559 4543 4527 4511 4495 4479 4463 4447 4431 4415 4399 4383 4367 4351 4335 4319 4303 4287 4271 4255 4239 4223 4207 4191 4175 4159 4143 4127 4111 4095 4079 4063 4047 4031 4015 3999 3983 3967 3951 3935 3919 3903
ILI9328
Y 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 No. 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 Name S288 S287 S286 S285 S284 S283 S282 S281 S280 S279 S278 S277 S276 S275 S274 S273 S272 S271 S270 S269 S268 S267 S266 S265 S264 S263 S262 S261 S260 S259 S258 S257 S256 S255 S254 S253 S252 S251 S250 S249 S248 S247 S246 S245 S244 S243 S242 S241 S240 S239 S238 S237 S236 S235 S234 S233 S232 S231 S230 S229 X -1439 -1455 -1471 -1487 -1503 -1519 -1535 -1551 -1567 -1583 -1599 -1615 -1631 -1647 -1663 -1679 -1695 -1711 -1727 -1743 -1759 -1775 -1791 -1807 -1823 -1839 -1855 -1871 -1887 -1903 -1919 -1935 -1951 -1967 -1983 -1999 -2015 -2031 -2047 -2063 -2079 -2095 -2111 -2127 -2143 -2159 -2175 -2191 -2207 -2223 -2239 -2255 -2271 -2287 -2303 -2319 -2335 -2351 -2367 -2383 Y 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5
No. 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660
X 2927 2911 2895 2879 2863 2847 2831 2815 2799 2783 2767 2751 2735 2719 2703 2687 2671 2655 2639 2623 2607 2591 2575 2559 2543 2527 2511 2495 2479 2463 2447 2431 2415 2399 2383 2367 2351 2335 2319 2303 2287 2271 2255 2239 2223 2207 2191 2175 2159 2143 2127 2111 2095 2079 2063 2047 2031 2015 1999 1983
Y 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5
No. 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720
X 1967 1951 1935 1919 1903 1887 1871 1855 1839 1823 1807 1791 1775 1759 1743 1727 1711 1695 1679 1663 1647 1631 1615 1599 1583 1567 1551 1535 1519 1503 1487 1471 1455 1439 1423 1407 1391 1375 1359 1343 1327 1311 1295 1279 1263 1247 1231 1215 1199 1183 1167 1151 1135 1119 1103 1087 1071 1055 1039 1023
Y 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5
No. 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766
Name S406 S405 S404 S403 S402 S401 S400 S399 S398 S397 S396 S395 S394 S393 S392 S391 S390 S389 S388 S387 S386 S385 S384 S383 S382 S381 S380 S379 S378 S377 S376 S375 S374 S373 S372 S371 S370 S369 S368 S367 S366 S365 S364 S363 S362 S361
X 1007 991 975 959 943 927 911 895 879 863 847 831 815 799 783 767 751 735 719 703 687 671 655 639 623 607 591 575 559 543 527 511 495 479 463 447 431 415 399 383 367 351 335 319 303 287 271 -271 -287 -303 -319 -335 -351 -367 -383 -399 -415 -431 -447 -463
Y 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5
No. 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840
X -479 -495 -511 -527 -543 -559 -575 -591 -607 -623 -639 -655 -671 -687 -703 -719 -735 -751 -767 -783 -799 -815 -831 -847 -863 -879 -895 -911 -927 -943 -959 -975 -991 -1007 -1023 -1039 -1055 -1071 -1087 -1103 -1119 -1135 -1151 -1167 -1183 -1199 -1215 -1231 -1247 -1263 -1279 -1295 -1311 -1327 -1343 -1359 -1375 -1391 -1407 -1423
767 DUMMY23 768 DUMMY24 769 770 771 772 773 774 775 776 777 778 779 780 S360 S359 S358 S357 S356 S355 S354 S353 S352 S351 S350 S349
ILI9328
Y 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 No. 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 Name G21 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 G59 G61 G63 G65 G67 G69 G71 G73 G75 G77 G79 G81 G83 G85 G87 G89 G91 G93 G95 G97 G99 G101 G103 G105 G107 G109 G111 G113 G115 G117 G119 G121 G123 G125 G127 G129 G131 G133 G135 G137 G139 X -6259 -6275 -6291 -6307 -6323 -6339 -6355 -6371 -6387 -6403 -6419 -6435 -6451 -6467 -6483 -6499 -6515 -6531 -6547 -6563 -6579 -6595 -6611 -6627 -6643 -6659 -6675 -6691 -6707 -6723 -6739 -6755 -6771 -6787 -6803 -6819 -6835 -6851 -6867 -6883 -6899 -6915 -6931 -6947 -6963 -6979 -6995 -7011 -7027 -7043 -7059 -7075 -7091 -7107 -7123 -7139 -7155 -7171 -7187 -7203 Y 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5
No. Name 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 S228 S227 S226 S225 S224 S223 S222 S221 S220 S219 S218 S217 S216 S215 S214 S213 S212 S211 S210 S209 S208 S207 S206 S205 S204 S203 S202 S201 S200 S199 S198 S197 S196 S195 S194 S193 S192 S191 S190 S189 S188 S187 S186 S185 S184 S183 S182 S181 S180 S179 S178 S177 S176 S175 S174 S173 S172 S171 S170 S169
X -2399 -2415 -2431 -2447 -2463 -2479 -2495 -2511 -2527 -2543 -2559 -2575 -2591 -2607 -2623 -2639 -2655 -2671 -2687 -2703 -2719 -2735 -2751 -2767 -2783 -2799 -2815 -2831 -2847 -2863 -2879 -2895 -2911 -2927 -2943 -2959 -2975 -2991 -3007 -3023 -3039 -3055 -3071 -3087 -3103 -3119 -3135 -3151 -3167 -3183 -3199 -3215 -3231 -3247 -3263 -3279 -3295 -3311 -3327 -3343
Y 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5
No. 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020
X -3359 -3375 -3391 -3407 -3423 -3439 -3455 -3471 -3487 -3503 -3519 -3535 -3551 -3567 -3583 -3599 -3615 -3631 -3647 -3663 -3679 -3695 -3711 -3727 -3743 -3759 -3775 -3791 -3807 -3823 -3839 -3855 -3871 -3887 -3903 -3919 -3935 -3951 -3967 -3983 -3999 -4015 -4031 -4047 -4063 -4079 -4095 -4111 -4127 -4143 -4159 -4175 -4191 -4207 -4223 -4239 -4255 -4271 -4287 -4303
Y 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5
No. 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080
X -4319 -4335 -4351 -4367 -4383 -4399 -4415 -4431 -4447 -4463 -4479 -4495 -4511 -4527 -4543 -4559 -4575 -4591 -4607 -4623 -4639 -4655 -4671 -4687 -4703 -4719 -4735 -4751 -4767 -4783 -4799 -4815 -4831 -4847 -4863 -4879 -4895 -4911 -4927 -4943 -4959 -4975 -4991 -5007 -5023 -5039 -5055 -5071 -5087 -5103 -5119 -5135 -5151 -5167 -5183 -5199 -5215 -5231 -5247 -5263
Y 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5
No. 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128
Name S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1
X -5279 -5295 -5311 -5327 -5343 -5359 -5375 -5391 -5407 -5423 -5439 -5455 -5471 -5487 -5503 -5519 -5535 -5551 -5567 -5583 -5599 -5615 -5631 -5647 -5663 -5679 -5695 -5711 -5727 -5743 -5759 -5775 -5791 -5807 -5823 -5839 -5855 -5871 -5887 -5903 -5919 -5935 -5951 -5967 -5983 -5999 -6015 -6031 -6047 -6083 -6099 -6115 -6131 -6147 -6163 -6179 -6195 -6211 -6227 -6243
1129 DUMMY25 1130 DUMMY26 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 G1 G3 G5 G7 G9 G11 G13 G15 G17 G19
ILI9328
No. 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260
Name G141 G143 G145 G147 G149 G151 G153 G155 G157 G159 G161 G163 G165 G167 G169 G171 G173 G175 G177 G179 G181 G183 G185 G187 G189 G191 G193 G195 G197 G199 G201 G203 G205 G207 G209 G211 G213 G215 G217 G219 G221 G223 G225 G227 G229 G231 G233 G235 G237 G239 G241 G243 G245 G247 G249 G251 G253 G255 G257 G259
X -7219 -7235 -7251 -7267 -7283 -7299 -7315 -7331 -7347 -7363 -7379 -7395 -7411 -7427 -7443 -7459 -7475 -7491 -7507 -7523 -7539 -7555 -7571 -7587 -7603 -7619 -7635 -7651 -7667 -7683 -7699 -7715 -7731 -7747 -7763 -7779 -7795 -7811 -7827 -7843 -7859 -7875 -7891 -7907 -7923 -7939 -7955 -7971 -7987 -8003 -8019 -8035 -8051 -8067 -8083 -8099 -8115 -8131 -8147 -8163
Y 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5
No. 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291
Name G261 G263 G265 G267 G269 G271 G273 G275 G277 G279 G281 G283 G285 G287 G289 G291 G293 G295 G297 G299 G301 G303 G305 G307 G309 G311 G313 G315 G317 G319 DUMMY27
X -8179 -8195 -8211 -8227 -8243 -8259 -8275 -8291 -8307 -8323 -8339 -8355 -8371 -8387 -8403 -8419 -8435 -8451 -8467 -8483 -8499 -8515 -8531 -8547 -8563 -8579 -8595 -8611 -8627 -8643 -8659 X -8751 8751
Y 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 319.5 202.5 Y 269 269
Alignment mark 1-a 1-b
ILI9328
16
16
16
98
S1 ~ S720 G1 ~ G320
19
DUMMY20~27 (No. 244 ~ 1291)
98 Unit: um
50
50
Pad Pump
Pad Pump y
I/O Pads (No. 1 ~ 243)
X=20, 30, 35 Y=70, 80, 85
Unit: um
80
ILI9328
5. Block Description
MPU System Interface
ILI9328 supports three system high-speed interfaces: i80-system high-speed interfaces to 8-, 9-, 16-, 18-bit parallel ports and serial peripheral interface (SPI). The interface mode is selected by setting the IM[3:0] pins. ILI9328 has a 16-bit index register (IR), an 18-bit write-data register (WDR), and an 18-bit read-data register (RDR). The IR is the register to store index information from control registers and the internal GRAM. The WDR is the register to temporarily store data to be written to control registers and the internal GRAM. The RDR is the register to temporarily store data read from the GRAM. Data from the MPU to be written to the internal GRAM are first written to the WDR and then automatically written to the internal GRAM in internal operation. Data are read via the RDR from the internal GRAM. Therefore, invalid data are read out to the data bus when the ILI9328 read the first data from the internal GRAM. Valid data are read out after the ILI9328 performs the second read operation. Registers are written consecutively as the register execution time. Registers selection by system interface (8-/9-/16-/18-bit bus width) Function Write an index to IR register Read an internal status Write to control registers or the internal GRAM by WDR register. Read from the internal GRAM by RDR register. Registers selection by the SPI system interface Function Write an index to IR register Read an internal status Write to control registers or the internal GRAM by WDR register. Read from the internal GRAM by RDR register. I80 nWR nRD 0 1 1 0 0 1 1 0
RS 0 0 1 1
R/W 0 1 0 1
RS 0 0 1 1
Parallel RGB Interface

ILI9328 supports the RGB interface and the VSYNC interface as the external interface for displaying a moving picture. When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and DOTCLK. In RGB interface mode, data (DB17-0) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data. In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal. Display data are written to the internal GRAM via the system interface. In this case, there are constraints in speed and method in writing data to the internal RAM. For details, see the External Display Interface section. The ILI9328 allows for switching between the external display interface and the system interface by instruction so that the optimum interface is selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)). The RGB The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9328
interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display.
Address Counter (AC)

The address counter (AC) gives an address to the internal GRAM. When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC. As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus 1. The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM.
Graphics RAM (GRAM)

GRAM is graphics RAM storing bit-pattern data of 172,820 (240 x 320x 18/8) bytes with 18 bits per pixel.
Grayscale Voltage Generating Circuit

The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the -correction register to display in 262,144 colors. For details, see the -Correction Register section.
Timing Controller
The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM. The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other.
Oscillator (OSC)
ILI9328 generates RC oscillation with an internal oscillation resistor. The frame rate is adjusted by the register setting.
LCD Driver Circuit

The LCD driver circuit of ILI9328 consists of a 720-output source driver (S1 ~ S720) and a 320-output gate driver (G1~G320). Display pattern data are latched when the 720th bit data are input. The latched data control the source driver and generate a drive waveform. The gate driver for scanning gate lines outputs either VGH or VGL level. The shift direction of 720 source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit. The scan mode by the gate driver is set with the SM bit. These bits allow setting an appropriate scan method for an LCD module.
LCD Driver Power Supply Circuit

The LCD drive power supply circuit generates the voltage levels VREG1OUT, VGH, VGL and Vcom for driving an LCD.
ILI9328
6. System Interface
6.1. Interface Specifications
ILI9328 has the system interface to read/write the control registers and display graphics memory (GRAM), and the RGB Input Interface for displaying a moving picture. User can select an optimum interface to display the moving or still picture with efficient data transfer. All display data are stored in the GRAM to reduce the data transfer efforts and only the updating data is necessary to be transferred. User can only update a sub-range of GRAM by using the window address function. ILI9328 also has the RGB interface and VSYNC interface to transfer the display data without flicker the moving picture on the screen. In RGB interface mode, the display data is written into the GRAM through the control signals of ENABLE, VSYNC, HSYNC, DOTCLK and data bus DB[17:0]. In VSYNC interface mode, the internal display timing is synchronized with the frame synchronization signal (VSYNC). The VSYNC interface mode enables to display the moving picture display through the system interface. In this case, there are some constraints of speed and method to write data to the internal RAM. ILI9328 operates in one of the following 4 modes. The display mode can be switched by the control register. When switching from one mode to another, refer to the sequences mentioned in the sections of RGB and VSYNC interfaces.
Operation Mode Internal operating clock only (Displaying still pictures) RGB interface (1) (Displaying moving pictures) RGB interface (2) (Rewriting still pictures while displaying moving pictures) VSYNC interface (Displaying moving pictures) RAM Access Setting (RM) System interface (RM = 0) RGB interface (RM = 1) System interface (RM = 0) System interface (RM = 0) Display Operation Mode (DM[1:0]) Internal operating clock (DM[1:0] = 00) RGB interface (DM[1:0] = 01) RGB interface (DM[1:0] = 01) VSYNC interface (DM[1:0] = 01)
Note 1) Registers are set only via the system interface. Note 2) The RGB-I/F and the VSYNC-I/F are not available simultaneously.
ILI9328
System Interface
18/16/6
nCS RS nWR nRD DB[17:0]
System
ENABLE VSYNC HSYNC DOTCLK
RGB Interface
Figure1 System Interface and RGB Interface connection
6.2. Input Interfaces

The following are the system interfaces available with the ILI9328. The interface is selected by setting the IM[3:0] pins. The system interface is used for setting registers and GRAM access.
IM3 0 0 0 0 0 0 1 1 1 1 1 IM2 0 0 0 0 1 1 0 0 0 0 1 IM1 0 0 1 1 0 1 0 0 1 1 * IM0/ID 0 1 0 1 ID * 0 1 0 1 * Interface Mode Setting invalid Setting invalid i80-system 16-bit interface i80-system 8-bit interface Serial Peripheral Interface (SPI) Setting invalid Setting invalid Setting invalid i80-system18-bit interface i80-system 9-bit interface Setting invalid DB Pin
DB[17:10], DB[8:1] DB[17:10] SDI, SDO
DB[17:0] DB[17:9]
ILI9328
6.2.1. i80/18-bit System Interface

The i80/18-bit system interface is selected by setting the IM[3:0] as 1010 levels.
System
nCS A2 nWR nRD D[31:0]
18
18-bit System Interface (262K colors) TRI=0, DFM[1:0]=00

Input Data
DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0
Write Data Register
WD 17
WD 16
WD 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
WD 0
GRAM Data & RGB Mapping
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure2 18-bit System Interface Data Format
ILI9328

The i80/16-bit system interface is selected by setting the IM[3:0] as 0010 levels. The 262K or 65K color can be display through the 16-bit MPU interface. When the 262K color is displayed, two transfers (1st transfer: 2 bits, 2nd transfer: 16 bits or 1st transfer: 16 bits, 2nd transfer: 2 bits) are necessary for the 16-bit CPU interface.
TRI
DFM
16-bit MPU System Interface Data Format system 16-bit interface (1 transfers/pixel) 65,536 colors
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
1st Transfer
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
80-system 16-bit interface (2 transfers/pixel) 262,144 colors 1 0

DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11
1st Transfer
DB 10 DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
2nd Transfer DB DB 17 16
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0

1st Transfer DB DB 2 1 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11
2nd Transfer
DB 10 DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
ILI9328

The i80/9-bit system interface is selected by setting the IM[3:0] as 1011 and the DB17~DB9 pins are used to transfer the data. When writing the 16-bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first. The display data is also divided in upper byte (9 bits) and lower byte, and the upper byte is transferred first. The unused DB[8:0] pins must be tied to GND.
System
nCS A1 nWR nRD D[8:0]
9-bit System Interface (262K colors) TRI=0, DFM[1:0]=00

1st Transfer (Upper bits) 2nd Transfer (Lower bits)
Input Data
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
Write Data Register
WD 17
WD 16
WD 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
WD 0
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0

The i80/8-bit system interface is selected by setting the IM[3:0] as 0011 and the DB17~DB10 pins are used to transfer the data. When writing the 16-bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first. The display data is also divided in upper byte (8 bits) and lower byte, and the upper byte is transferred first. The written data is expanded into 18 bits internally (see the figure below) and then written into GRAM. The unused DB[9:0] pins must be tied to GND.
TRI DFM 8-bit MPU System Interface Data Format system 8-bit interface (2 transfers/pixel) 65,536 colors 0 *
DB 17 DB 16 DB 15
ILI9328
1st Transfer
DB 14 DB 13
DB 12
DB 11
DB 10
DB 17
DB 16
DB 15
2nd Transfer
DB 14 DB 13
DB 12
DB 11
DB 10
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0

1st Transfer DB DB 11 10 DB 17 DB 16 DB 15
2nd Transfer
DB 14 DB 13
DB 12
DB 11
DB 10
DB 17
DB 16
DB 15
3rd Transfer
DB 14 DB 13
DB 12
DB 11
DB 10
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0

DB 17 DB 16
1st Transfer
DB 15 DB 14
DB 13
DB 12
DB 17
DB 16
2nd Transfer
DB 15 DB 14
DB 13
DB 12
DB 17
DB 16
3rd Transfer
DB 15 DB 14
DB 13
DB 12
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure5 8-bit System Interface Data Format Data transfer synchronization in 8/9-bit bus interface mode ILI9328 supports a data transfer synchronization function to reset upper and lower counters which count the transfers numbers of upper and lower byte in 8/9-bit interface mode. If a mismatch arises in the numbers of transfers between the upper and lower byte counters due to noise and so on, the 00h register is written 4 times consecutively to reset the upper and lower counters so that data transfer will restart with a transfer of upper byte. This synchronization function can effectively prevent display error if the upper/lower counters are periodically reset.
RS
RD
nWR Upper/ Lower
DB[17:9]
00h
00h
00h
00h
Upper
Lower
8-/9-bit transfer synchronization
Figure6 Data Transfer Synchronization in 8/9-bit System Interface
6.3. Serial Peripheral Interface (SPI)

The Serial Peripheral Interface (SPI) is selected by setting the IM[3:0] pins as 010x level. The chip select pin The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9328
(nCS), the serial transfer clock pin (SCL), the serial data input pin (SDI) and the serial data output pin (SDO) are used in SPI mode. The ID pin sets the least significant bit of the identification code. The DB[17:0] pins, which are not used, must be tied to GND. The SPI interface operation enables from the falling edge of nCS and ends of data transfer on the rising edge of nCS. The start byte is transferred to start the SPI interface and the read/write operation and RS information are also included in the start byte. When the start byte is matched, the subsequent data is received by ILI9328. The seventh bit of start byte is RS bit. When RS = 0, either index write operation or status read operation is executed. When RS = 1, either register write operation or RAM read/write operation is executed. The eighth bit of the start byte is used to select either read or write operation (R/W bit). Data is written when the R/W bit is 0 and read back when the R/W bit is 1. After receiving the start byte, ILI9328 starts to transfer or receive the data in unit of byte and the data transfer starts from the MSB bit. All the registers of the ILI9328 are 16-bit format and receive the first and the second byte datat as the upper and the lower eight bits of the 16-bit register respectively. In SPI mode, 5 bytes dummy read is necessary and the valid data starts from 6th byte of read back data. Start Byte Format Transferred bits Start byte format S Transfer start 1 0 Note: ID bit is selected by setting the IM0/ID pin. RS and R/W Bit Function RS 0 0 1 1 R/W 0 1 0 1 Function Set an index register Read a status Write a register or GRAM data Read a register or GRAM data 2 1 3 4 Device ID code 1 1 5 0 6 ID 7 RS 1/0 8 R/W 1/0
ILI9328
Serial Peripheral Interface for register access

D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
SPI Input Data
Register Data
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Serial Peripheral Interface 65K colors

Input Data
Write Data Register
WD 17
WD 16
WD 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
WD 0
GRAM Data RGB mapping
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure 7 Data Format of SPI Interface
ILI9328
End
(a) Basic data transmission through SPI

Start nCS (Input) 1 SCL (Input) SDI (Input) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
ID
RS RW D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Start Byte SDO (Output)
Index register, registers setting, and GRAM write D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Status, registers read and GRAM read
(b) Consecutive data transmission through SPI

Start nCS (Input) 1 SCL (Input) SDI (Input) Start Byte Register 1 upper eight bits Register 1 lower eight bits Register 2 upper eight bits Register 1 execution time Register 2 lower eight bits 8 9 16 17 24 25 32
Note: The first byte after the start byte is always the upper eight bits .
(c) GRAM data read transmission

Start nCS (Input)
End
SCL (Input) SDI (Input) SDO (Output) Start Byte RS=1, RW=1 Dummy read 1 Dummy read 2 Dummy read 3 Dummy read 4 Dummy read 5 RAM read upper byte RAM read lower byte
Note: Five bytes of invalid dummy data read after the start byte .
(d) Status/registers read transmission

Start nCS (Input) 1 SCL (Input) SDI (Input) SDO (Output) Start Byte Register 1 upper eight bits Register 1 lower eight bits 8 9 16 17 24
End
Note: One byte of invalid dummy data read after the start byte .
Figure8 Data transmission through serial peripheral interface (SPI)
ILI9328
End
(e) Basic data transmission through SPI

Start nCS (Input) 1 SCL (Input) SDI (Input) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ID
RS RW D23 D22 D21 D120 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 GRAM data write D23 D22 D21 D120 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 GRAM data read
D8
D7
D6
D5
D4
D3
D2
D1
D0
Start Byte SDO (Output)
D8
D7
D6
D5
D4
D3
D2
D1
D0
(f) GRAM data write transmission

Start nCS (Input)
End
SCL (Input) SDI (Input) SDO (Output) Note: Five bytes of invalid dummy data read after the start byte. Start Byte RAM data 1 1st transfer RAM data 1 2nd transfer RAM data 1 3rd transfer RAM data 2 1st transfer RAM data 2 2nd transfer RAM data 2 3rd transfer
GRAM Data (1) execution time
GRAM Data (2) execution time
(g) GRAM data read transmission

Start nCS (Input)
End
SCL (Input) SDI (Input) SDO (Output) Start Byte RS=1, RW=1 Dummy read 1 Dummy read 2 Dummy read 3 Dummy read 4 Dummy read 5 RAM read 1st byte RAM read 2nd byte RAM read 3rd byte
Note: Five bytes of invalid dummy data read after the start byte.
RAM data transfer in SPI mode when TRI=1 and DFM[1:0]=10.
Figure9 Data transmission through serial peripheral interface (SPI), TRI=1 and DFM=10)
ILI9328
6.4. VSYNC Interface

ILI9328 supports the VSYNC interface in synchronization with the frame-synchronizing signal VSYNC to display the moving picture with the i80 system interface. When the VSYNC interface is selected to display a moving picture, the minimum GRAM update speed is limited and the VSYNC interface is enabled by setting DM[1:0] = 10 and RM = 0.
VSYNC
MPU
nCS RS nWR DB[17:0]
Figure10 Data transmission through VSYNC interface) In the VSYNC mode, the display operation is synchronized with the internal clock and VSYNC input and the frame rate is determined by the pulse rate of VSYNC signal. All display data are stored in GRAM to minimize total data transfer required for moving picture display.
VSYNC Write data to RAM through system interface Display operation synchronized with internal clocks Rewriting screen data Rewriting screen data
Figure11 Moving picture data transmission through VSYNC interface
ILI9328
VSYNC
Back porch (14 lines)
RAM Write Display operation
Display (320 lines)
Front porch (2 lines) Black period
Figure12 Operation through VSYNC Interface The VSYNC interface has the minimum speed limitation of writing data to the internal GRAM via the system interface, which are calculated from the following formula. Internal clock frequency (fosc.) [Hz] = FrameFrequency x (DisplayLine (NL) + FrontPorch (FP) + BackPorch (BP)) x ClockCyclePerLines (RTN) x FrequencyFluctuation.
Minimum RAM write speed (HZ)
240 x DisplayLines (NL) [(BackPorch(BP)+DisplayLines(NL) - margins] x 16 (clocks) x 1/fosc
Note: When the RAM write operation does not start from the falling edge of VSYNC, the time from the falling edge of VSYNC until the start of RAM write operation must also be taken into account. An example of minimum GRAM writing speed and internal clock frequency in VSYNC interface mode is as below. [Example] Display size: 240 RGB 320 lines Lines: 320 lines (NL = 100111) Back porch: 14 lines (BP = 1110) Front porch: 2 lines (FP = 0010) Frame frequency: 60 Hz Frequency fluctuation: 10% The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9328
Internal oscillator clock (fosc.) [Hz] = 60 x [320+ 2 + 14] x 16 clocks x (1.1/0.9) 394KHz
When calculate the internal clock frequency, the oscillator variation is needed to be taken into consideration. In the above example, the calculated internal clock frequency with 10% margin variation is considered and ensures to complete the display operation within one VSYNC cycle. The causes of frequency variation come from fabrication process of LSI, room temperature, external resistors and VCI voltage variation. Minimum speed for RAM writing [Hz] > 240 x 320 x 394K / [ (14 + 320 2)lines x 16clocks] 5.7 MHz
The above theoretical value is calculated based on the premise that the ILI9328 starts to write data into the internal GRAM on the falling edge of VSYNC. There must at least be a margin of 2 lines between the physical display line and the GRAM line address where data writing operation is performed. The GRAM write speed of 5.7MHz or more will guarantee the completion of GRAM write operation before the ILI9328 starts to display the GRAM data on the screen and enable to rewrite the entire screen without flicker.
Notes in using the VSYNC interface 1. The minimum GRAM write speed must be satisfied and the frequency variation must be taken into consideration. 2. The display frame rate is determined by the VSYNC signal and the period of VSYNC must be longer than the scan period of an entire display. 3. When switching from the internal clock operation mode (DM[1:0] = 00) to the VSYNC interface mode or inversely, the switching starts from the next VSYNC cycle, i.e. after completing the display of the frame. 4. The partial display, vertical scroll, and interlaced scan functions are not available in VSYNC interface mode and set the AM bit to 0 to transfer display data.
ILI9328
System Interface Mode to VSYNC interface mode
VSYNC interface mode to System Interface Mode Opeartion through VSYNC interface
Set DM [1:0]=00, RM=0 for system interface mode
System Interface
Set
AM=0
Set GRAM Address
Display operation in synchronization with internal clocks
Display operation in synchronization with VSYNC DM [1:0], RM become enable after completion of displaying 1 frame Display operation in synchronization with internal clocks
Set DM1:0]=10, RM=0 [ for VSYNC interface mode
Wait more than1 frame
Set index register to R 22h
DM [1:0], RM become enable after completion of displaying 1 frame
System Interface
Wait more than1 frame
Note: input VSYNC for more than 1 frame period after setting the DM , RM register . Display operation in synchronization with VSYNC
Write data to GRAM through VSYNC interface
Opeartion through VSYNC interface
Figure13 Transition flow between VSYNC and internal clock operation modes
ILI9328
6.5. RGB Input Interface

The RGB Interface mode is available for ILI9328 and the interface is selected by setting the RIM[1:0] bits as following table. RIM1 0 0 1 1 RIM0 0 1 0 1 RGB Interface 18-bit RGB Interface 16-bit RGB Interface 6-bit RGB Interface Setting prohibited DB pins DB[17:0] DB[17:13], DB[11:1] DB[17:12]
18-bit RGB Interface (262K colors)

Input Data
Write Data Register
WD 17
WD 16
WD 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
WD 0
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0

Input Data
DB 17 DB 16 DB 15 DB 14 DB 13 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1
Write Data Register
WD 17
WD 16
WD 15
WD 14
WD 13
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0

1st Transfer 2nd Transfer 3rd Transfer
Input Data
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
Write Data Register
WD 17
WD 16
WD 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
WD 0
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure14 RGB Interface Data Format The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9328
6.5.1. RGB Interface

The display operation via the RGB interface is synchronized with the VSYNC, HSYNC, and DOTCLK signals. The RGB interface transfers the updated data to GRAM with the high-speed write function and the update area is defined by the window address function. The back porch and front porch are used to set the RGB interface timing.
VSYNC RAM data display area Moving picture display area HSYNC DOTCLK ENABLE DB[17:0]
Back porch period (BP[3:0])
Display period (NL[4:0]
Front porch period (FP[3:0]) Note 1: Front porch period continues until the next input of VSYNC. Note 2: Input DOTCLK throughout the operation. Note 3: Supply the VSYNC, HSYNC and DOTCLK with frequency that can meet the resolution requirement of panel.
Figure15 GRAM Access Area by RGB Interface
ILI9328
6.5.2. RGB Interface Timing

The timing chart of 18-/16-bit RGB interface mode is shown as follows.
1 frame Back porch VLW >= 1H Front porch
VSYNC
HSYNC
DOTCLK
ENABLE
DB[17:0]
HLW >= 3 DOTCLK HSYNC
// 1H
// DOTCLK DTST >= HLW ENABLE //
DB[17:0] Valid data VLW: VSYNC low period HLW: HSYNC low period DTST: data transfer startup time .
Figure16 Timing Chart of Signals in 18-/16-bit RGB Interface Mode
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color The timing chart of 6-bit RGB interface mode is shown as follows.
1 frame Back porch VLW >= 1H Front porch
ILI9328
VSYNC
HSYNC
DOTCLK
ENABLE
DB[17:12]
HLW >= 3 DOTCLK HSYNC
// 1H
// DOTCLK DTST >= HLW ENABLE // R G B R G B DB[17:12] Valid data VLW: VSYNC low period HLW: HSYNC low period DTST: data transfer startup time . Note 1) In 6-bit RGB interface mode, each dot of one pixel (R, G and B) is transferred in synchronization with DOTCLKs.
Note 2) In 6-bit RGB interface mode, set the cycles of VSYNC, HSYNC and ENABLE to 3 multiples of DOTCLKs.
//
B R G B
Figure17 Timing chart of signals in 6-bit RGB interface mode
ILI9328
6.5.3. Moving Picture Mode

ILI9328 has the RGB interface to display moving picture and incorporates GRAM to store display data, which has following merits in displaying a moving picture. The window address function defined the update area of GRAM. Only the moving picture area of GRAM is updated. When display the moving picture in RGB interface mode, the DB[17:0] can be switched as system interface to update still picture area and registers, such as icons. RAM access via a system interface in RGB-I/F mode ILI9328 allows GRAM access via the system interface in RGB interface mode. In RGB interface mode, data are written to the internal GRAM in synchronization with DOTCLK and ENABLE signals. When write data to the internal GRAM by the system interface, set ENABLE to terminate the RGB interface and switch to the system interface to update the registers (RM = 0) and the still picture of GRAM. When restart RAM access in RGB interface mode, wait one read/write cycle and then set RM = 1 and the index register to R22h to start accessing RAM via the RGB interface. If RAM accesses via two interfaces conflicts, there is no guarantee that data are written to the internal GRAM. The following figure illustrates the operation of the ILI9328 when displaying a moving picture via the RGB interface and rewriting the still picture RAM area via the system interface.
Still Picture Area Moving Picture Area Update a frame
Update a frame
VSYNC
ENABLE
DOTCLK
DB[17:0] Update moving picture area Update moving picture area
Set IR to R22h
Set RM=0
Set AD[15:0]
Set IR to R22h
Update display data in other than the moving picture area
Set AD[15:0]
Set RM=1
Set IR to R22h
Figure18 Example of update the still and moving picture
ILI9328
6.5.4. 6-bit RGB Interface

The 6-bit RGB interface is selected by setting the RIM[1:0] bits to 10. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal GRAM in synchronization with the display operation via 6-bit RGB data bus (DB[17:12]) according to the data enable signal (ENABLE). Unused pins (DB[11:0]) must be fixed at GND level. Registers can be set by the system interface (i80/SPI).
RGB interface with 6-bit data bus
1st Transfer Input Data
DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16
2nd Transfer
DB 15 DB 14 DB 13 DB 12 DB 17 DB 16
3rd Transfer
DB 15 DB 14 DB 13 DB 12
RGB Assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Data transfer synchronization in 6-bit RGB interface mode ILI9328 has data transfer counters to count the first, second, third data transfers in 6-bit RGB interface mode. The transfer counter is always reset to the state of first data transfer on the falling edge of VSYNC. If a mismatch arises in the number of each data transfer, the counter is reset to the state of first data transfer at the start of the frame (i.e. on the falling edge of VSYNC) to restart data transfer in the correct order from the next frame. This function is expedient for moving picture display, which requires consecutive data transfer in light of minimizing effects from failed data transfer and enabling the system to return to a normal state. Note that internal display operation is performed in units of pixels (RGB: taking 3 inputs of DOTCLK). Accordingly, the number of DOTCLK inputs in one frame period must be a multiple of 3 to complete data transfer correctly. Otherwise it will affect the display of that frame as well as the next frame.
HSYNC
ENABLE
DOTCLK DB[17:12]
st nd rd 1st 2nd 3rd 1st 2nd 3rd 1 2 3 1st 2nd 3rd
Transfer synchronization
ILI9328

The 16-bit RGB interface is selected by setting the RIM[1:0] bits to 01. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal RAM in synchronization with the display operation via 16-bit RGB data bus (DB17-13, DB11-1) according to the data enable signal (ENABLE). Registers are set only via the system interface.

Input Data
Write Data Register
WD 17
WD 16
WD 15
WD 14
WD 13
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0

The 18-bit RGB interface is selected by setting the RIM[1:0] bits to 00. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal RAM in synchronization with the display operation via 18-bit RGB data bus (DB[17:0]) according to the data enable signal (ENABLE). Registers are set only via the system interface.
RGB interface with 18-bit data bus

Input Data
RGB Assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Notes in using the RGB Input Interface 1. The following are the functions not available in RGB Input Interface mode. Function Partial display Scroll function Interlaced scan RGB interface Not available Not available Not available I80 system interface Available Available Available
2. VSYNC, HSYNC, and DOTCLK signals must be supplied throughout a display operation period. 3. The periods set with the NO[1:0] bits (gate output non-overlap period), STD[1:0] bits (source output delay period) and EQ[1:0] bits (equalization period) are not based on the internal clock but based on DOTCLK in The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color RGB interface mode.
ILI9328
4. In 6-bit RGB interface mode, each of RGB dots is transferred in synchronization with a DOTCLK input. In other words, it takes 3 DOTCLK inputs to transfer one pixel. Be sure to complete data transfer in units of 3 DOTCLK inputs in 6-bit RGB interface mode. 5. In 6-bit RGB interface mode, data of one pixel, which consists of RGB dots, are transferred in units of 3 DOTCLK. Accordingly, set the cycle of each signal in 6-bit interface mode (VSYNC, HSYNC, ENABLE, DB[17:0]) to contain DOTCLK inputs of a multiple of 3 to complete data transfer in units of pixels. 6. When switching from the internal operation mode to the RGB Input Interface mode, or the other way around, follow the sequence below. 7. In RGB interface mode, the front porch period continues until the next VSYNC input is detected after drawing one frame. 8. In RGB interface mode, a RAM address (AD[15:0]) is set in the address counter every frame on the falling edge of VSYNC.
Internal clock operation to RGB I/F Internal clock operation AM=0 Internal clock operation * SPI interface can be used to set the registers and data * DM[1:0] and RM become enable after completion of display 1 frame
RGB I/F to Internal clock operation RGB Interface Operation Set Internal Clock Operation mode DM[1:0]=00 and RM=0 RGB Interface (Display operation in synchronization with VSYNC, HSYNC, DOTCLK) * DM[1:0] and RM become enable after completion of display 1 frame
Set AD[15:0]
Wait for more than 1 frame
Set RGB Interface mode DM[1:0]=01 and RM=1
Note
Internal clock operation
Set IR to R22h (GRAM data write)
Display operation in synchronization with internal clock
Wait for more than 1 frame RGB Interface (Display operation in synchronization with VSYNC, HSYNC, DOTCLK)
Write through RGB I/F
RGB Interface Operation

Note: Input RGB Interface signals (VSYNC, HSYNC, DOTCLK) before setting DM[1;0] and RM to the RGB interface mode
Figure19 Internal clock operation/RGB interface mode switching The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9328
Write data through RGB interface to write data through system interface RGB Interface operation Set DM=1, RM=0 with RGB interface mode Set AD[15;0]
Write data through system interface to write data through RGB interface System Interface operation Write data to GRAM through system interface
Set AD[15;0] Set DM=1, RM=1 with RGB interface mode Set IR to R22h (GRAM data write) RGB Interface operation
Set IR to R22h (GRAM data write)
Write data to GRAM through system interface System Interface operation
Figure20 GRAM access between system interface and RGB interface
ILI9328
6.6. Interface Timing

The following are diagrams of interfacing timing with LCD panel control signals in internal operation and RGB interface modes.
// VSYNC //
HSYNC
DOTCLK
//
ENABLE // // DB[17:0] 1 2 3 4 5 318 319 320 1 2 3 4
FLM
G1 G2
G320 // 1 2 3 4 5 318 319 320
S[720:1]
VCOM
..
Figure21 Relationship between RGB I/F signals and LCD Driving Signals for Panel
ILI9328
7. Register Descriptions
7.1. Registers Access
ILI9328 adopts 18-bit bus interface architecture for high-performance microprocessor. All the functional blocks of ILI9328 starts to work after receiving the correct instruction from the external microprocessor by the 18-, 16-, 9-, 8-bit interface. The index register (IR) stores the register address to which the instructions and display data will be written. The register selection signal (RS), the read/write signals (nRD/nWR) and data bus D17-0 are used to read/write the instructions and data of ILI9328. The registers of the ILI9328 are categorized into the following groups. 1. Specify the index of register (IR) 2. Read a status 3. Display control 4. Power management Control 5. Graphics data processing 6. Set internal GRAM address (AC) 7. Transfer data to/from the internal GRAM (R22) 8. Internal grayscale -correction (R30 ~ R39) Normally, the display data (GRAM) is most often updated, and in order since the ILI9328 can update internal GRAM address automatically as it writes data to the internal GRAM and minimize data transfer by using the window address function, there are fewer loads on the program in the microprocessor. As the following figure shows, the way of assigning data to the 16 register bits (D[15:0]) varies for each interface. Send registers in accordance with the following data transfer format.
Serial Peripheral Interface for register access

SPI Input Data
Register Data
D 15
D 14
D 13
D 12
D 11
D 10
D 9
D 8
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
Figure22 Register Setting with Serial Peripheral Interface (SPI)
ILI9328
i80/M68 system 18-bit data bus interface

Data Bus (DB[17:0])
Register Bit (D[15:0])
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

Data Bus (DB[17:10]), (DB[8:1]) Register Bit (D[15:0])
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

Data Bus (DB[17:9])
DB 17 DB 16 DB 15 1st Transfer DB DB DB 14 13 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 2nd Transfer DB DB DB 14 13 12 DB 11 DB 10 DB 9
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
i80/M68 system 8-bit data bus interface/Serial peripheral interface (2/3 transmission)
Data Bus (DB[17:10])
DB 17 DB 16 DB 15 1st Transfer DB DB 14 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 2nd Transfer DB DB 14 13 DB 12 DB 11 DB 10
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure23 Register setting with i80 System Interface
ILI9328
i80 18-/16-bit System Bus Interface Timing
(a) Write to register

nCS RS nRD nWR DB[17:0]
Write register index Write register data
(b) Read from register

Write register index Read register data
(a) Write to register

00h Write register index Write register high byte data Write register low byte data
(b) Read from register

00h Write register index Read register high byte data Read register low byte data
Figure 24 Register Read/Write Timing of i80 System Interface The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9328
D10 0 SM 0 0 0 0 FP2 PTS2 0 0 0 0 BT2 DC12 0 VDV2 0 0 D9 1 0 BC0 0 RCV1 0 FP1 PTS1 0 0 0 0 BT1 DC11 0 VDV1 0 0 D8 1 SS EOR 0 RCV0 BASEE FP0 PTS0 0 RM FMP8 0 BT0 DC10 0 VDV0 0 AD16 D7 ID7 0 0 0 ORG 0 0 0 0 0 0 FMP7 0 APE 0 VCIRE 0 AD7 AD15 D6 ID6 0 0 0 0 0 0 0 0 0 0 FMP6 0 AP2 DC02 0 0 AD6 AD14 D5 ID5 1 0 0 I/D1 RCH1 GON 0 PTG1 0 DM1 FMP5 0 AP1 DC01 0 0 AD5 AD13 D4 ID4 0 0 0 I/D0 RCH0 DTE 0 PTG0 0 DM0 FMP4 VSPL AP0 DC00 PON 0 AD4 AD12 D3 ID3 0 0 0 AM 0 CL BP3 ISC3 FMARKOE 0 FMP3 HSPL 0 0 VRH3 0 AD3 AD11 D2 ID2 1 0 0 0 0 0 BP2 ISC2 FMI2 0 FMP2 0 0 VC2 VRH2 0 AD2 AD10 D1 ID1 0 0 0 0 RSZ1 D1 BP1 ISC1 FMI1 RIM1 FMP1 DPL SLP VC1 VRH1 0 AD1 AD9 D0 ID0 1 0 0 0 RSZ0 D0 BP0 ISC0 FMI0 RIM0 FMP0 EPL STB VC0 VRH0 0 AD0 AD8
7.2. Instruction Descriptions

No. IR Registers Name Index Register R/W RS W RO W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D15 1 0 0 TRI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D14 0 0 0 DFM 0 0 0 0 0 ENC2 0 0 0 0 0 0 0 0 D13 0 0 0 0 0 PTDE1 0 0 0 ENC1 0 0 0 0 0 0 0 0 D12 1 0 0 BGR 0 PTDE0 0 0 0 ENC0 0 0 SAP 0 0 VDV4 0 0 D11 0 0 0 0 0 0 FP3 0 0 0 0 0 0 0 0 VDV3 0 0 00h Driver Code Read 01h Driver Output Control 1 02h LCD Driving Control 03h Entry Mode 04h Resize Control 07h Display Control 1 08h Display Control 2 09h Display Control 3 0Ah Display Control 4 0Ch RGB Display Interface Control 1 0Dh Frame Maker Position 0Fh RGB Display Interface Control 2 10h Power Control 1 11h Power Control 2 12h Power Control 3 13h Power Control 4 20h Horizontal GRAM Address Set 21h Vertical GRAM Address Set 22h Write Data to GRAM 29h Power Control 7 2Bh Frame Rate and Color Control 30h Gamma Control 1 31h Gamma Control 2 32h Gamma Control 3 35h Gamma Control 4 36h Gamma Control 5 37h Gamma Control 6 38h Gamma Control 7 39h Gamma Control 8 3Ch Gamma Control 9 3Dh Gamma Control 10 50h Horizontal Address Start
RAM write data (WD17-0) / read data (RD17-0) bits are transferred via different data bus lines according to the selected interfaces. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VRP1[4] 0 0 0 0 VRN1[4] 0 0 0 0 0 0 0 VRP1[3] 0 0 0 0 VRN1[3] 0 0 0 KP1[2] KP3[2] KP5[2] RP1[2] KN1[2] KN3[2] KN5[2] RN1[2] 0 0 0 KP1[1] KP3[1] KP5[1] RP1[1] KN1[1] KN3[1] KN5[1] RN1[1] 0 0 0 KP1[0] KP3[0] KP5[0] RP1[0] KN1[0] KN3[0] KN5[0] RN1[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 HSA7 0 0 0 0 0 0 0 0 0 0 0 0 HSA6 VCM5 0 0 0 0 0 0 0 0 0 0 0 HSA5 VCM4 0 0 0 0 0 0 0 0 0 0 0 HSA4 VCM3 FRS[3] 0 0 0 0 VRP0[3] 0 0 0 0 VRN0[3] HSA3 VCM2 FRS[2] KP0[2] KP2[2] KP4[2] RP0[2] KN0[2] KN2[2] KN4[2] RN0[2] HSA2 VCM1 FRS[1] KP0[1] KP2[1] KP4[1] RP0[1] KN0[1] KN2[1] KN4[1] RN0[1] HSA1 VCM0 FRS[0] KP0[0] KP2[0] KP4[0] RP0[0] KN0[0] KN2[0] KN4[0] RN0[0] HSA0
VRP1[2] VRP1[1] VRP1[0]
VRP0[2] VRP0[1] VRP0[0]
VRN1[2] VRN1[1] VRN1[0]
VRN0[2] VRN0[1] VRN0[0]
No. Registers Name Position 51h Horizontal Address End Position 52h Vertical Address Start Position 53h Vertical Address End Position 60h Driver Output Control 2 61h Base Image Display Control 6Ah Vertical Scroll Control 80h Partial Image 1 Display Position 81h Partial Image 1 Area (Start Line) 82h Partial Image 1 Area (End Line) 83h Partial Image 2 Display Position 84h Partial Image 2 Area (Start Line) 85h Partial Image 2 Area (End Line) 90h Panel Interface Control 1 92h Panel Interface Control 2 95h Panel Interface Control 4 A1h OTP VCM Programming Control A2h OTP VCM Status and Enable A5h OTP Programming ID Key W W W W W W W W W W W W W W W W W W 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 GS 0 0 0 0 0 0 0 0 0 0 0 0 PGM_ CNT1 KEY 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGM_ CNT0 KEY 14 0 0 0 NL5 0 0 0 0 0 0 0 0 0 0 0 0 VCM_ D5 KEY 13 0 0 0 NL4 0 0 0 0 0 0 0 0 0 0 0 0 VCM_ D4 KEY 12 0 0 0 NL3 0 0 0 0 0 0 0 0 0 0 0 OTP_ PGM_EN VCM_ D3 KEY 11 0 0 0 NL2 0 0 0 0 0 0 0 0 0 NOWI2 0 0 VCM_ D2 KEY 10 R/W RS D15 D14 D13 D12 D11 D10
ILI9328
D9 0 0 0 NL1 0 0 0 0 0 0 0 0 DIVI1 NOWI1 DIVE1 0 VCM_ D1 KEY 9 D8 0 VSA8 VEA8 NL0 0 VL8 D7 HEA7 VSA7 VEA7 0 0 VL7 D6 HEA6 VSA6 VEA6 0 0 VL6 D5 HEA5 VSA5 VEA5 SCN5 0 VL5 D4 HEA4 VSA4 VEA4 SCN4 0 VL4 PTDP04 PTSA04 PTEA04 PTDP14 PTSA14 PTEA14 0 0 RTNE4 VCM_ OTP4 0 KEY 4 D3 HEA3 VSA3 VEA3 SCN3 0 VL3 PTDP03 PTSA03 PTEA03 PTDP13 PTSA13 PTEA13 RTNI3 0 RTNE3 VCM_ OTP3 0 KEY 3 D2 HEA2 VSA2 VEA2 SCN2 NDL VL2 D1 HEA1 VSA1 VEA1 SCN1 VLE VL1 D0 HEA0 VSA0 VEA0 SCN0 REV VL0
PTDP08 PTDP07 PTDP06 PTDP05 PTSA08 PTSA07 PTSA06 PTSA05 PTEA08 PTEA07 PTEA06 PTEA05 PTDP18 PTDP17 PTDP16 PTDP15 PTSA18 PTSA17 PTSA16 PTSA15 PTEA18 PTEA17 PTEA16 PTEA15 DIVI00 NOWI0 DIVE0 0 VCM_ D0 KEY 8 0 0 0 0 0 KEY 7 0 0 0 0 0 KEY 6 0 0 RTNE5 VCM_ OTP5 0 KEY 5
PTDP02 PTDP01 PTDP00 PTSA02 PTSA01 PTSA00 PTEA02 PTEA01 PTEA00 PTDP12 PTDP11 PTDP10 PTSA12 PTSA11 PTSA10 PTEA12 PTEA11 PTEA10 RTNI2 0 RTNE2 VCM_ OTP2 0 KEY 2 RTNI1 0 RTNE1 VCM_ OTP1 0 KEY 1 RTNI0 0 RTNE0 VCM_ OTP0 VCM_ EN KEY 0
ILI9328
D4 ID4 D3 ID3 D2 ID2 D1 ID1 D0 ID0
7.2.1. Index (IR)

R/W W RS 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 ID7 D6 ID6 D5 ID5
The index register specifies the address of register (R00h ~ RFFh) or RAM which will be accessed.
7.2.2. ID code (R00h)

R/W RO RS 1 D15 1 D14 0 D13 0 D12 1 D11 0 D10 0 D9 1 D8 1 D7 0 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 1
The device code 9325h is read out when read this register.
7.2.3. Driver Output Control (R01h)

R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 SM D9 0 D8 SS D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
SS: Select the shift direction of outputs from the source driver. When SS = 0, the shift direction of outputs is from S1 to S720 When SS = 1, the shift direction of outputs is from S720 to S1. In addition to the shift direction, the settings for both SS and BGR bits are required to change the assignment of R, G, B dots to the source driver pins. To assign R, G, B dots to the source driver pins from S1 to S720, set SS = 0. To assign R, G, B dots to the source driver pins from S720 to S1, set SS = 1. When changing SS or BGR bits, RAM data must be rewritten. SM: Sets the gate driver pin arrangement in combination with the GS bit (R60h) to select the optimal scan mode for the module.
ILI9328
SM
GS
Scan Direction
G320 G318 Even-number TFT Panel G319 G317 Odd-number
Gate Output Sequence
G1, G2, G3, G4, ,G316

G2 to G320 Even-number G1 to G319 G4 G2 ILI9328 G320 G318 TFT Panel G319 G317 Odd-number G3 G1
G317, G318, G319, G320
G320, G319, G318, ,

G2 to G320 Even-number G2 to G320 G1 to G319 G4 G2 ILI9328 G320 TFT Panel G2 G3 G1
G6, G5, G4, G3, G2, G1
G1, G3, G5, G7, ,G311 G313, G315, G317, G319

G319 Odd-number
G2, G4, G6, G8, ,G312 G314, G316, G318, G320
G1 to G319
G1 ILI9328
Even-number
G320
G320, G318, G316, ,

TFT Panel G2
G10, G8, G6, G4, G2

G319 Odd-number
G2 to G320
G319, G317, G315, ,

G1 to G319 G1 ILI9328
G9, G78, G5, G3, G1
7.2.4. LCD Driving Wave Control (R02h)

R/W
W
RS
1
D15
0
D14
0
D13
0
D12
0
D11
0
D10
1
D9
B/C
D8
EOR
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
.B/C 0 : Frame/Field inversion 1 : Line inversion
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color EOR: EOR = 1 and B/C=1 to set the line inversion.
ILI9328
7.2.5. Entry Mode (R03h)

R/W
W
RS
1
D15
TRI
D14
DFM
D13
0
D12
BGR
D11
0
D10
0
D9
0
D8
0
D7
ORG
D6
0
D5
I/D1
D4
I/D0
D3
AM
D2
0
D1
0
D0
0
AM Control the GRAM update direction. When AM = 0, the address is updated in horizontal writing direction. When AM = 1, the address is updated in vertical writing direction. When a window area is set by registers R50h ~R53h, only the addressed GRAM area is updated based on I/D[1:0] and AM bits setting. I/D[1:0] Control the address counter (AC) to automatically increase or decrease by 1 when update one pixel display data. Refer to the following figure for the details.
I/D[1:0] = 00 Horizontal : decrement Vertical : decrement

E
I/D[1:0] = 01 Horizontal : increment Vertical : decrement

E
I/D[1:0] = 10 Horizontal : decrement Vertical : increment

B
I/D[1:0] = 11 Horizontal : increment Vertical : increment

B
AM = 0 Horizontal
AM = 1 Vertical
Figure25 GRAM Access Direction Setting ORG Moves the origin address according to the ID setting when a window address area is made. This function is enabled when writing data with the window address area using high-speed RAM write. ORG = 0: The origin address is not moved. In this case, specify the address to start write operation according to the GRAM address map within the window address area. ORG = 1: The original address 00000h moves according to the I/D[1:0] setting. Notes: 1. When ORG=1, only the origin address address00000h can be set in the RAM address set registers R20h, and R21h. 2. In RAM read operation, make sure to set ORG=0. BGR Swap the R and B order of written data. BGR=0: Follow the RGB order to write the pixel data. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color BGR=1: Swap the RGB data to BGR in writing into GRAM.
ILI9328
TRI When TRI = 1, data are transferred to the internal RAM in 8-bit x 3 transfers mode via the 8-bit interface. It is also possible to send data via the 16-bit interface or SPI in the transfer mode that realizes display in 262k colors in combination with DFM bits. When not using these interface modes, be sure to set TRI = 0. DFM Set the mode of transferring data to the internal RAM when TRI = 1. See the following figures for details.
TRI DFM 16-bit MPU System Interface Data Format
system 16-bit interface (1 transfers/pixel) 65,536 colors
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
1st Transfer
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
80-system 16-bit interface (2 transfers/pixel) 262,144 colors
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
1st Transfer
DB 10 DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
2nd Transfer DB DB 17 16
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1st Transfer DB DB 2 1
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
2nd Transfer
DB 10 DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure26 16-bit MPU System Interface Data Format
TRI DFM 8-bit MPU System Interface Data Format
system 8-bit interface (2 transfers/pixel) 65,536 colors
ILI9328
DB 17
DB 16
DB 15
1st Transfer
DB 14 DB 13
DB 12
DB 11
DB 10
DB 17
DB 16
DB 15
2nd Transfer
DB 14 DB 13
DB 12
DB 11
DB 10
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1st Transfer DB DB 11 10
DB 17
DB 16
DB 15
2nd Transfer
DB 14 DB 13
DB 12
DB 11
DB 10
DB 17
DB 16
DB 15
3rd Transfer
DB 14 DB 13
DB 12
DB 11
DB 10
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
DB 17
DB 16
1st Transfer
DB 15 DB 14
DB 13
DB 12
DB 17
DB 16
2nd Transfer
DB 15 DB 14
DB 13
DB 12
DB 17
DB 16
3rd Transfer
DB 15 DB 14
DB 13
DB 12
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Figure27 8-bit MPU System Interface Data Format
7.2.6. Resizing Control Register (R04h)

R/W
W
RS
1
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
RCV1
D8
RCV0
D7
0
D6
0
D5
RCH1
D4
RCH0
D3
0
D2
0
D1
RSZ1
D0
RSZ0
RSZ[1:0] Sets the resizing factor. When the RSZ bits are set for resizing, the ILI9328 writes the data according to the resizing factor so that the original image is displayed in horizontal and vertical dimensions, which are contracted according to the factor respectively. See Resizing function. RCH[1:0] Sets the number of remainder pixels in horizontal direction when resizing a picture. By specifying the number of remainder pixels by RCH bits, the data can be transferred without taking the reminder pixels into consideration. Make sure that RCH = 2h0 when not using the resizing function (RSZ = 2h0) or there are no remainder pixels. RCV[1:0] Sets the number of remainder pixels in vertical direction when resizing a picture. By specifying the number of remainder pixels by RCV bits, the data can be transferred without taking the reminder pixels into consideration. Make sure that RCV = 2h0 when not using the resizing function (RSZ = 2h0) or there are no remainder pixels. RSZ[1:0] 00 01 10 11 RCH[1:0] 00 Resizing factor No resizing (x1) x 1/2 Setting prohibited x 1/4
Number of remainder Pixels in Horizontal Direction 0 pixel*
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 01 10 11 RCV[1:0] 00 01 10 11 *1 pixel = 1RGB 1 pixel 2 pixel 3 pixel Number of remainder Pixels in Vertical Direction 0 pixel* 1 pixel 2 pixel 3 pixel
ILI9328
7.2.7. Display Control 1 (R07h)

R/W
W
RS
1
D15
0
D14
0
D13
PTDE1
D12
PTDE0
D11
0
D10
0
D9
0
D8
BASEE
D7
0
D6
0
D5
GON
D4
DTE
D3
CL
D2
0
D1
D1
D0
D0
D[1:0] Set D[1:0]=11 to turn on the display panel, and D[1:0]=00 to turn off the display panel. A graphics display is turned on the panel when writing D1 = 1, and is turned off when writing D1 = 0. When writing D1 = 0, the graphics display data is retained in the internal GRAM and the ILI9328 displays the data when writing D1 = 1. When D1 = 0, i.e. while no display is shown on the panel, all source outputs becomes the GND level to reduce charging/discharging current, which is generated within the LCD while driving liquid crystal with AC voltage. When the display is turned off by setting D[1:0] = 01, the ILI9328 continues internal display operation. When the display is turned off by setting D[1:0] = 00, the ILI9328 internal display operation is halted completely. In combination with the GON, DTE setting, the D[1:0] setting controls display ON/OFF. D1 0 0 1 1 1 D0 0 1 0 1 1 BASEE 0 1 0 0 1 Source, VCOM Output GND GND Non-lit display Non-lit display Base image display ILI9328 internal operation Halt Operate Operate Operate Operate
Note: 1. data write operation from the microcontroller is performed irrespective of the setting of D[1:0] bits. 2. The D[1:0] setting is valid on both 1st and 2nd displays. 3. The non-lit display level from the source output pins is determined by instruction (PTS). CL When CL = 1, the 8-color display mode is selected. CL 0 1 Colors 262,144 8
GON and DTE Set the output level of gate driver G1 ~ G320 as follows GON 0 0 DTE 0 1 G1 ~G320 Gate Output VGH VGH
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 1 1 BASEE 0 1 VGL Normal Display
ILI9328
Base image display enable bit. When BASEE = 0, no base image is displayed. The ILI9328 drives liquid crystal at non-lit display level or displays only partial images. When BASEE = 1, the base image is displayed. The D[1:0] setting has higher priority over the BASEE setting. PTDE[1:0] Partial image 2 and Partial image 1 enable bits PTDE1/0 = 0: turns off partial image. Only base image is displayed. PTDE1/0 = 1: turns on partial image. Set the base image display enable bit to 0 (BASEE = 0).

R/W
W
RS
1
D15
0
D14
0
D13
0
D12
0
D11
FP3
D10
FP2
D9
FP1
D8
FP0
D7
0
D6
0
D5
0
D4
0
D3
BP3
D2
BP2
D1
BP1
D0
BP0
FP[3:0]/BP[3:0] The FP[3:0] and BP[3:0] bits specify the line number of front and back porch periods respectively. When setting the FP[3:0] and BP[3:0] value, the following conditions shall be met: BP + FP 16 lines FP 2 lines BP 2 lines
Set the BP[3:0] and FP[3:0] bits as below for each operation modes
Operation Mode I80 System Interface Operation Mode RGB interface Operation VSYNC interface Operation BP BP 2 lines BP 2 lines BP 2 lines FP FP 2 lines FP 2 lines FP 2 lines BP+FP FP +BP 16 lines FP +BP 16 lines FP +BP = 16 lines
FP[3:0] Number of lines for Front Porch BP[3:0] Number of lines for Back Porch 0000 Setting Prohibited Back Porch 0001 Setting Prohibited 0010 2 lines 0011 3 lines Display 0100 4 lines Area 0101 5 lines 0110 6 lines 0111 7 lines Front Porch 1000 8 lines 1001 9 lines 1010 10 lines 1011 11 lines 1100 12 lines Note: The output timing to the LCD is delayed by 2 1101 13 lines lines period from the input of synchronizing signal. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 58 of 106
VSYNC
Version: 0.1
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 1110 1111 14 lines Setting Prohibited
ILI9328

R/W
W
RS
1
D15
0
D14
0
D13
0
D12
0
D11
0
D10
PTS2
D9
PTS1
D8
PTS0
D7
0
D6
0
D5
PTG1
D4
PTG0
D3
ISC3
D2
ISC2
D1
ISC1
D0
ISC0
ISC[3:0]: Specify the scan cycle interval of gate driver in non-display area when PTG[1:0]=10 to select interval scan. Then scan cycle is set as odd number from 0~29 frame periods. The polarity is inverted every scan cycle. ISC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ISC3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ISC3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ISC3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Scan Cycle 0 frame 1 frame 3 frame 5 frame 7 frame 9 frame 11 frame 13 frame 15 frame 17 frame 19 frame 21 frame 23 frame 25 frame 27 frame 29 frame fFLM=60 Hz 17ms 50ms 84ms 117ms 150ms 184ms 217ms 251ms 284ms 317ms 351ms 384ms 418ms 451ms 484ms
PTG[1:0] Set the scan mode in non-display area. PTG1 0 0 1 1 PTS[2:0] Set the source output level in non-display area drive period (front/back porch period and blank area between partial displays). When PTS[2] = 1, the operation of amplifiers which generates the grayscales other than V0 and V63 are halted and the step-up clock frequency becomes half the normal frequency in non-display drive period in order to reduce power consumption.
Source output level Positive polarity Negative polarity V63 V0 Setting Prohibited Setting Prohibited Grayscale amplifier in operation V63 to V0 -
PTG0 0 1 0 1
Gate outputs in non-display area Normal scan

Setting Prohibited
Source outputs in non-display area Set with the PTS[2:0] bits Set with the PTS[2:0] bits -
Vcom output VcomH/VcomL VcomH/VcomL -
Interval scan
Setting Prohibited
PTS[2:0] 000 001
Step-up clock frequency Register Setting (DC1, DC0) -
010 011 100 101 110 111 GND Hi-Z V63 Setting Prohibited GND Hi-Z GND Hi-Z V0 Setting Prohibited GND Hi-Z V63 to V0 V63 to V0 V63 and V0 V63 and V0 V63 and V0
ILI9328
Register Setting (DC1, DC0) Register Setting (DC1, DC0) frequency setting by DC1, DC0 frequency setting by DC1, DC0 frequency setting by DC1, DC0
Notes: 1. The power efficiency can be improved by halting grayscale amplifiers and slowing down the step-up clock frequency only in non-display drive period. 2. The gate output level in non-lit display area drive period is determined by PTG[1:0].
7.2.10. Display Control 4 (R0Ah)

R/W
W
RS
1
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
FMARKOE
D2
FMI2
D1
FMI1
D0
FMI0
FMI[2:0] Set the output interval of FMARK signal according to the display data rewrite cycle and data transfer rate. FMARKOE When FMARKOE=1, ILI9328 starts to output FMARK signal in the output interval set by FMI[2:0] bits. FMI[2:0] 000 001 011 101 Others Output Interval 1 frame 2 frame 4 frame 6 frame Setting disabled
7.2.11. RGB Display Interface Control 1 (R0Ch)

R/W
W
RS
1
D15
0
D14
ENC2
D13
ENC1
D12
ENC0
D11
0
D10
0
D9
0
D8
RM
D7
0
D6
0
D5
DM1
D4
DM0
D3
0
D2
0
D1
RIM1
D0
RIM0
RIM[1:0] Select the RGB interface data width.

RIM1 0 0 1 1 RIM0 0 1 0 1 RGB Interface Mode 18-bit RGB interface (1 transfer/pixel), DB[17:0] 16-bit RGB interface (1 transfer/pixel), DB[17:13] and DB[11:1] 6-bit RGB interface (3 transfers/pixel), DB[17:12] Setting disabled
Note1: Registers are set only by the system interface. Note2: Be sure that one pixel (3 dots) data transfer finished when interface switch.
DM[1:0] Select the display operation mode.

DM1 0 0 1 1 DM0 0 1 0 1 Display Interface Internal system clock RGB interface VSYNC interface Setting disabled
The DM[1:0] setting allows switching between internal clock operation mode and external display interface operation mode. However, switching between the RGB interface operation mode and the The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color VSYNC interface operation mode is prohibited. RM Select the interface to access the GRAM. Set RM to 1 when writing display data by the RGB interface.
RM 0 1 Interface for RAM Access System interface/VSYNC interface RGB interface
ILI9328
Display State Still pictures Moving pictures
Operation Mode Internal clock operation RGB interface (1)
RAM Access (RM) System interface (RM = 0) RGB interface (RM = 1) System interface (RM = 0) System interface (RM = 0)
Display Operation Mode (DM[1:0] Internal clock operation (DM[1:0] = 00) RGB interface (DM[1:0] = 01) RGB interface (DM[1:0] = 01) VSYNC interface (DM[1:0] = 10)
Rewrite still picture area while RGB interface Displaying moving pictures. Moving pictures VSYNC interface
Note 1: Registers are set only via the system interface or SPI interface. Note 2: Refer to the flowcharts of RGB Input Interface section for the mode switch.
ENC[2:0] Set the GRAM write cycle through the RGB interface
ENC[2:0] 000 001 010 011 100 101 110 111 GRAM Write Cycle (Frame periods) 1 Frame 2 Frames 3 Frames 4 Frames 5 Frames 6 Frames 7 Frames 8 Frames
7.2.12. Frame Marker Position (R0Dh)

R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 FMP8 FMP7 FMP6 FMP5 FMP4 FMP3 FMP2 FMP1 FMP0
FMP[8:0] Sets the output position of frame cycle (frame marker). When FMP[8:0]=0, a high-active pulse FMARK is output at the start of back porch period for one display line period (1H). Make sure the 9h000 FMP BP+NL+FP FMP[8:0] FMARK Output Position 9h000 0th line 9h001 1st line 9h002 2nd line 9h003 3rd line . . . . . . 9h175 373rd line The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 9h176 9h177 374th line 375th line
ILI9328
7.2.13. RGB Display Interface Control 2 (R0Fh)

R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 VSPL D3 HSPL D2 0 D1 EPL D0 DPL
DPL: Sets the signal polarity of the DOTCLK pin. DPL = 0 The data is input on the rising edge of DOTCLK DPL = 1 The data is input on the falling edge of DOTCLK EPL: Sets the signal polarity of the ENABLE pin. EPL = 0 The data DB17-0 is written when ENABLE = 0. Disable data write operation when ENABLE = 1. EPL = 1 The data DB17-0 is written when ENABLE = 1. Disable data write operation when ENABLE = 0. HSPL: Sets the signal polarity of the HSYNC pin. HSPL = 0 Low active HSPL = 1 High active VSPL: Sets the signal polarity of the VSYNC pin. VSPL = 0 Low active VSPL = 1 High active
7.2.14. Power Control 1 (R10h)

R/W W RS 1 D15 0 D14 0 D13 0 D12 SAP D11 0 D10 BT2 D9 BT1 D8 BT0 D7 APE D6 AP2 D5 AP1 D4 AP0 D3 0 D2 0 D1 SLP D0 STB
SLP: When SLP = 1, ILI9328 enters the sleep mode and the display operation stops except the RC oscillator to reduce the power consumption. In the sleep mode, the GRAM data and instructions cannot be updated except the following two instructions. a. Exit sleep mode (SLP = 0) b. Start oscillation STB: When STB = 1, ILI9328 enters the standby mode and the display operation stops except the GRAM power supply to reduce the power consumption. In the STB mode, the GRAM data and instructions cannot be updated except the following two instructions. a. Exit standby mode (STB = 0) b. Start oscillation AP[2:0]: Adjusts the constant current in the operational amplifier circuit in the LCD power supply circuit. The larger constant current enhances the drivability of the LCD, but it also increases the current consumption. Adjust the constant current taking the trade-off into account between the display quality The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9328
and the current consumption. In no-display period, set AP[2:0] = 000 to halt the operational amplifier circuits and the step-up circuits to reduce current consumption.
AP[2:0] 000 001 010 011 100 101 110 111 Gamma driver amplifiers Halt 1.00 1.00 1.00 0.75 0.75 0.75 0.50 Source driver amplifiers Halt 1.00 0.75 0.50 1.00 0.75 0.50 0.50
SAP: Source Driver output control SAP=0, Source driver is disabled. SAP=1, Source driver is enabled. When starting the charge-pump of LCD in the Power ON stage, make sure that SAP=0, and set the SAP=1, after starting up the LCD power supply circuit. APE: Power supply enable bit. Set APE = 1 to start the generation of power supply according to the power supply startup sequence. BT[3:0]: Sets the factor used in the step-up circuits. Select the optimal step-up factor for the operating voltage. To reduce power consumption, set a smaller factor.
BT[2:0] 3h0 3h1 3h2 3h3 3h4 3h5 3h6 3h7 Vci1 x 2 - Vci1 Vci1 x 4 Vci1 x 2 - Vci1 Vci1 x 5 DDVDH Vci1 x 2 Vci1 x 2 VCL - Vci1 - Vci1 Vci1 x 6 VGH VGL - Vci1 x 5 - Vci1 x 4 - Vci1 x 3 - Vci1 x 5 - Vci1 x 4 - Vci1 x 3 - Vci1 x 4 - Vci1 x 3
Notes: 1. Connect capacitors to the capacitor connection pins when generating DDVDH, VGH, VGL and VCL levels. 2. Make sure DDVDH = 6.0V (max.), VGH = 15.0V (max.), VGL = 12.5V (max) and VCL= -3.0V (max.)

R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 DC12 D9 DC11 D8 DC10 D7 0 D6 DC02 D5 DC01 D4 DC00 D3 0 D2 VC2 D1 VC1 D0 VC0
VC[2:0] Sets the ratio factor of Vci to generate the reference voltages Vci1.
VC2 0 0 VC1 0 0 VC0 0 1 Vci1 voltage 0.95 x Vci 0.90 x Vci
0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0.85 x Vci 0.80 x Vci 0.75 x Vci 0.70 x Vci Disabled 1.0 x Vci
ILI9328
DC0[2:0]: Selects the operating frequency of the step-up circuit 1. The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption. Adjust the frequency taking the trade-off between the display quality and the current consumption into account. DC1[2:0]: Selects the operating frequency of the step-up circuit 2. The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption. Adjust the frequency taking the trade-off between the display quality and the current consumption into account.
DC02 0 0 0 0 1 1 1 1 DC01 0 0 1 1 0 0 1 1 DC00 0 1 0 1 0 1 0 1 Step-up circuit1 step-up frequency (fDCDC1) Fosc Fosc / 2 Fosc / 4 Fosc / 8 Fosc / 16 Fosc / 32 Fosc / 64 Halt step-up circuit 1 DC12 0 0 0 0 1 1 1 1 DC11 0 0 1 1 0 0 1 1 DC10 0 1 0 1 0 1 0 1 Step-up circuit2 step-up frequency (fDCDC2) Fosc / 4 Fosc / 8 Fosc / 16 Fosc / 32 Fosc / 64 Fosc / 128 Fosc / 256 Halt step-up circuit 2
Note: Be sure fDCDC1fDCDC2 when setting DC0[2:0] and DC1[2:0].

R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 VCIRE D6 0 D5 0 D4 PON D3 VRH3 D2 VRH2 D1 VRH1 D0 VRH0
VRH[3:0] Set the amplifying rate (1.6 ~ 1.9) of Vci applied to output the VREG1OUT level, which is a reference level for the VCOM level and the grayscale voltage level. VCIRE: Select the external reference voltage Vci or internal reference voltage VCIR. VCIRE=0 VCIRE =1
VCIRE =0 VRH3 0 0 0 0 0 0 0 VRH2 0 0 0 0 1 1 1 VRH1 0 0 1 1 0 0 1 VRH0 0 1 0 1 0 1 0 VREG1OUT Halt Vci x 2.00 Vci x 2.05 Vci x 2.10 Vci x 2.20 Vci x 2.30 Vci x 2.40 VRH3 0 0 0 0 0 0 0 VRH2 0 0 0 0 1 1 1 0 0 1 1 0 0 1
External reference voltage Vci (default) Internal reference voltage 2.5V

VCIRE =1 VRH1 VRH0 0 1 0 1 0 1 0 VREG1OUT Halt 2.5V x 2.00 = 5.000V 2.5V x 2.05 = 5.125V 2.5V x 2.10 = 5.250V 2.5V x 2.20 = 5.500V 2.5V x 2.30 = 5.750V 2.5V x 2.40 = 6.000V
0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 Vci x 2.40 Vci x 1.60 Vci x 1.65 Vci x 1.70 Vci x 1.75 Vci x 1.80 Vci x 1.85 Vci x 1.90 Vci x 1.95 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1
ILI9328
2.5V x 2.40 = 6.000V 2.5V x 1.60 = 4.000V 2.5V x 1.65 = 4.125V 2.5V x 1.70 = 4.250V 2.5V x 1.75 = 4.375V 2.5V x 1.80 = 4.500V 2.5V x 1.85 = 4.625V 2.5V x 1.90 = 4.750V 2.5V x 1.95 = 4.875V
When VCI<2.5V, Internal reference voltage will be same as VCI. Make sure that VC and VRH setting restriction: VREG1OUT (DDVDH - 0.2)V.
PON: Control ON/OFF of circuit3 (VGL) output. PON=0 PON=1 VGL output is disable VGL output is enable

R/W W RS 1 D15 0 D14 0 D13 0 D12 D11 D10 VDV2 D9 VDV1 D8 VDV0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 VDV4 VDV3
VDV[4:0] Select the factor of VREG1OUT to set the amplitude of Vcom alternating voltage from 0.70 to 1.24 x VREG1OUT .
VDV4 VDV3 VDV2 VDV1 VDV0 VCOM amplitude 0 0 0 0 0 VREG1OUT x 0.70 0 0 0 0 1 VREG1OUT x 0.72 0 0 0 1 0 VREG1OUT x 0.74 0 0 0 1 1 VREG1OUT x 0.76 0 0 1 0 0 VREG1OUT x 0.78 0 0 1 0 1 VREG1OUT x 0.80 0 0 1 1 0 VREG1OUT x 0.82 0 0 1 1 1 VREG1OUT x 0.84 0 1 0 0 0 VREG1OUT x 0.86 0 1 0 0 1 VREG1OUT x 0.88 0 1 0 1 0 VREG1OUT x 0.90 0 1 0 1 1 VREG1OUT x 0.92 0 1 1 0 0 VREG1OUT x 0.94 0 1 1 0 1 VREG1OUT x 0.96 0 1 1 1 0 VREG1OUT x 0.98 0 1 1 1 1 VREG1OUT x 1.00 VDV4 VDV3 VDV2 VDV1 VDV0 VCOM amplitude 1 0 0 0 0 VREG1OUT x 0.94 1 0 0 0 1 VREG1OUT x 0.96 1 0 0 1 0 VREG1OUT x 0.98 1 0 0 1 1 VREG1OUT x 1.00 1 0 1 0 0 VREG1OUT x 1.02 1 0 1 0 1 VREG1OUT x 1.04 1 0 1 1 0 VREG1OUT x 1.06 1 0 1 1 1 VREG1OUT x 1.08 1 1 0 0 0 VREG1OUT x 1.10 1 1 0 0 1 VREG1OUT x 1.12 1 1 0 1 0 VREG1OUT x 1.14 1 1 0 1 1 VREG1OUT x 1.16 1 1 1 0 0 VREG1OUT x 1.18 1 1 1 0 1 VREG1OUT x 1.20 1 1 1 1 0 VREG1OUT x 1.22 1 1 1 1 1 VREG1OUT x 1.24
Set VDV[4:0] to let Vcom amplitude less than 6V.
7.2.18. GRAM Horizontal/Vertical Address Set (R20h, R21h)

R/W W W RS 1 1 D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 0 0 D9 0 0 D8 0 AD16 D7 AD7 AD15 D6 AD6 AD14 D5 AD5 AD13 D4 AD4 AD12 D3 AD3 AD11 D2 AD2 AD10 D1 AD1 AD9 D0 AD0 AD8
AD[16:0] Set the initial value of address counter (AC). The address counter (AC) is automatically updated in accordance to the setting of the AM, I/D bits as data is written to the internal GRAM. The address counter is not automatically updated when read data from the internal GRAM. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9328
AD[16:0] 17h00000 ~ 17h000EF 17h00100 ~ 17h001EF 17h00200 ~ 17h002EF 17h00300 ~ 17h003EF 17h13D00 ~ 17 h13DEF 17h13E00 ~ 17 h13EEF 17h13F00 ~ 17h13FEF every frame on the falling edge of VSYNC.
GRAM Data Map 1st line GRAM Data 2nd line GRAM Data 3rd line GRAM Data 4th line GRAM Data 318th line GRAM Data 319th line GRAM Data 320th line GRAM Data
Note1: When the RGB interface is selected (RM = 1), the address AD[16:0] is set to the address counter Note2: When the internal clock operation or the VSYNC interface mode is selected (RM = 0), the address AD[16:0] is set to address counter when update register R21.
7.2.19. Write Data to GRAM (R22h)

R/W W RS 1 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RAM write data (WD[17:0], the DB[17:0] pin assignment differs for each interface.
This register is the GRAM access port. When update the display data through this register, the address counter (AC) is increased/decreased automatically.
7.2.20. Read Data from GRAM (R22h)

R/W R RS 1 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RAM Read Data (RD[17:0], the DB[17:0] pin assignment differs for each interface.
RD[17:0] Read 18-bit data from GRAM through the read data register (RDR).
ILI9328
18-bit System Interface

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Write Data Register
RD 17
RD 16
RD 15
RD 14
RD 13
RD 12
RD 11
RD 10
RD 9
RD 8
RD 7
RD 6
RD 5
RD 4
RD 3
RD 2
RD 1
RD 0
Output Data
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0

Write Data Register
RD 17
RD 16
RD 15
RD 14
RD 13
RD 12
RD 11
RD 10
RD 9
RD 8
RD 7
RD 6
RD 5
RD 4
RD 3
RD 2
RD 1
RD 0
Output Data
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1

Write Data Register
RD 17
RD 16
RD 15
RD 14
RD 13
RD 12
RD 11
RD 10
RD 9
RD 8
RD 7
RD 6
RD 5
RD 4
RD 3
RD 2
RD 1
RD 0
Output Data
DB 17
DB 16
DB 15
DB 14
DB 13
1st Transfer
DB 12
DB 11
DB 10
DB 9
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
2nd Transfer
8-bit System Interface / Serial Data Transfer Interface

Write Data Register
RD 17
RD 16
RD 15
RD 14
RD 13
RD 12
RD 11
RD 10
RD 9
RD 8
RD 7
RD 6
RD 5
RD 4
RD 3
RD 2
RD 1
RD 0
Output Data
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
1st Transfer
2nd Transfer
Figure 28 Data Read from GRAM through Read Data Register in 18-/16-/9-/8-bit Interface Mode
ILI9328
Set I/D AM, HAS/HEA, VSA/VEA
Set address M
Dummy read (invalid data) GRAM -> Read data latch
Read Output (data of address M) Read datalatch -> DB[17:0]
Read Output (data of address M+1) Read datalatch -> DB[17:0]
Set address N
Dummy read (invalid data) GRAM -> Read data latch
Read Output (data of address N) Read datalatch -> DB[17:0]
Figure 29 GRAM Data Read Back Flow Chart

R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 D4 D3 D2 D1 D0 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0
VCM[5:0] Set the internal VcomH voltage.

VCM5 VCM4 VCM3 VCM2 VCM1 VCM0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 VCOMH VREG1OUT 0.685 VREG1OUT 0.690 VREG1OUT 0.695 VREG1OUT 0.700 VREG1OUT VCM5 VCM4 VCM3 VCM2 VCM1 VCM0 x x x x x 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 VCOMH VREG1OUT 0.845 VREG1OUT 0.850 VREG1OUT 0.855 VREG1OUT 0.860 VREG1OUT
x x x x x
0.705 VREG1OUT 0.710 VREG1OUT 0.715 VREG1OUT 0.720 VREG1OUT 0.725 VREG1OUT 0.730 VREG1OUT 0.735 VREG1OUT 0.740 VREG1OUT 0.745 VREG1OUT 0.750 VREG1OUT 0.755 VREG1OUT 0.760 VREG1OUT 0.765 VREG1OUT 0.770 VREG1OUT 0.775 VREG1OUT 0.780 VREG1OUT 0.785 VREG1OUT 0.790 VREG1OUT 0.795 VREG1OUT 0.800 VREG1OUT 0.805 VREG1OUT 0.810 VREG1OUT 0.815 VREG1OUT 0.820 VREG1OUT 0.825 VREG1OUT 0.830 VREG1OUT 0.835 VREG1OUT 0.840 x x x x x x x x x x x x x x x x x x x x x x x x x x x
ILI9328
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.865 VREG1OUT 0.870 VREG1OUT 0.875 VREG1OUT 0.880 VREG1OUT 0.885 VREG1OUT 0.890 VREG1OUT 0.895 VREG1OUT 0.900 VREG1OUT 0.905 VREG1OUT 0.910 VREG1OUT 0.915 VREG1OUT 0.920 VREG1OUT 0.925 VREG1OUT 0.930 VREG1OUT 0.935 VREG1OUT 0.940 VREG1OUT 0.945 VREG1OUT 0.950 VREG1OUT 0.955 VREG1OUT 0.960 VREG1OUT 0.965 VREG1OUT 0.970 VREG1OUT 0.975 VREG1OUT 0.980 VREG1OUT 0.985 VREG1OUT 0.990 VREG1OUT 0.995 VREG1OUT 1.000 x x x x x x x x x x x x x x x x x x x x x x x x x x x
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
7.2.22. Frame Rate and Color Control (R2Bh)

R/W W RS 1 D15 0 D14 0 D13 0 D12 D11 0 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 FRS3 FRS2 FRS1 FRS0
FRS[4:0] Set the frame rate when the internal resistor is used for oscillator circuit. FRS[3:0] 0000 FRS[3:0] 4h0 Frame Rate 30
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4h1 4h2 4h3 4h4 4h5 4h6 4h7 4h8 4h9 4hA 4hB 4hC 4hD 4hE 4hF 31 33 35 38 40 43 47 51 56 62 70 80 93 112 Setting Prohibited
ILI9328
7.2.23. Gamma Control (R30h ~ R3Dh)

R/W R30h R31h R32h R35h R36h R37h R38h R39h R3Ch R3Dh W W W W W W W W W W RS 1 1 1 1 1 1 1 1 1 1 D15 D14 D13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D12 0 0 0 0 D11 0 0 0 0 D10 KP1[2] KP3[2] KP5[2] RP1[2] D9 KP1[1] KP3[1] KP5[1] RP1[1] D8 KP1[0] KP3[0] KP5[0] RP1[0] D7 D6 D5 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3 0 0 0 0 D2 KP0[2] KP2[2] KP4[2] RP0[2] D1 KP0[1] KP2[1] KP4[1] RP0[1] D0 KP0[0] KP2[0] KP4[0] RP0[0]
VRP1[4] VRP1[3] VRP1[2] VRP1[1] VRP1[0] 0 0 0 0 0 0 0 0 0 KN1[2] KN3[2] KN5[2] RN1[2] KN1[1] KN3[1] KN5[1] RN1[1] KN1[0] KN3[0] KN5[0] RN1[0] 0 0 0 0
VRP0[3] VRP0[2] VRP0[1] VRP0[0] 0 0 0 0 KN0[2] KN2[2] KN4[2] RN0[2] KN0[1] KN2[1] KN4[1] RN0[1] KN0[0] KN2[0] KN4[0] RN0[0]
VRN1[4] VRN1[3] VRN1[2] VRN1[1] VRN1[0] 0
VRN0[3] VRN0[2] VRN0[1] VRN0[0]
KP5-0[2:0] : fine adjustment register for positive polarity RP1-0[2:0] : gradient adjustment register for positive polarity VRP1-0[4:0] : amplitude adjustment register for positive polarity KN5-0[2:0] : fine adjustment register for negative polarity RN1-0[2:0] : gradient adjustment register for negative polarity VRN1-0[4:0] : amplitude adjustment register for negative polarity For details -Correction Function section.
7.2.24. Horizontal and Vertical RAM Address Position (R50h, R51h, R52h, R53h)
R/W R50h R51h R52h R53h W W W W RS 1 1 1 1 D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D8 0 0 D7 D6 D5 D4 D3 D2 D1 D0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0
0 VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 0 VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0
ILI9328
HSA[7:0]/HEA[7:0] HSA[7:0] and HEA[7:0] represent the respective addresses at the start and end of the window address area in horizontal direction. By setting HSA and HEA bits, it is possible to limit the area on the GRAM horizontally for writing data. The HSA and HEA bits must be set before starting RAM write operation. In setting these bits, be sure 00h HSA[7:0]< HEA[7:0] EFh. and 04hHEA-HAS.
VSA[8:0]/VEA[8:0] VSA[8:0] and VEA[8:0] represent the respective addresses at the start and end of the window address area in vertical direction. By setting VSA and VEA bits, it is possible to limit the area on the GRAM vertically for writing data. The VSA and VEA bits must be set before starting RAM write operation. In setting, be sure 000h VSA[8:0]< VEA[8:0] 13Fh.
HSA
0000h
HEA
VSA Window Address Area VEA GRAM Address Area

13FEFh
Figure 30 GRAM Access Range Configuration
00h HAS[7:0] HEA[7:0] EFh 00h VSA[7:0] VEA[7:0] 13Fh

Note1. The window address range must be within the GRAM address space. Note2. Data are written to GRAM in four-words when operating in high speed mode, the dummy write operations should be inserted depending on the window address area. For details, see the High-Speed RAM Write Function section.
7.2.25. Gate Scan Control (R60h, R61h, R6Ah)

R/W R60h R61h R6Ah W W W RS 1 1 1 D15 GS 0 0 D14 0 0 0 D13 NL5 0 0 D12 NL4 0 0 D11 NL3 0 0 D10 NL2 0 0 D9 NL1 0 0 D8 NL0 0 VL8 D7 0 0 VL7 D6 0 0 VL6 D5 D4 D3 D2 D1 D0 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0 0 VL5 0 VL4 0 VL3 NDL VL2 VLE VL1 REV VL0
ILI9328
SCN[5:0] The ILI9328 allows to specify the gate line from which the gate driver starts to scan by setting the SCN[5:0] bits.
Scanning Start Position
SCN[5:0] 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h ~ 3Fh
SM=0 GS=0 G1 G9 G17 G25 G33 G41 G49 G57 G65 G73 G81 G89 G97 G105 G113 G121 G129 G137 G145 G153 G161 G169 G177 G185 G193 G201 G209 G217 G225 G233 G241 G249 G257 G265 G273 G281 G289 G297 G305 G313 Setting disabled GS=1 G320 G312 G304 G296 G288 G280 G272 G264 G256 G248 G240 G232 G224 G216 G208 G200 G192 G184 G176 G168 G160 G152 G144 G136 G128 G120 G112 G104 G96 G88 G80 G72 G64 G56 G48 G40 G32 G24 G16 G8 Setting disabled
SM=1 GS=0 GS=1 G1 G320 G17 G304 G33 G288 G49 G272 G65 G256 G81 G240 G97 G224 G113 G208 G129 G192 G145 G176 G161 G160 G177 G144 G193 G128 G209 G112 G2 G96 G18 G80 G34 G64 G50 G48 G66 G32 G82 G16 G98 G319 G114 G303 G130 G287 G146 G271 G162 G255 G178 G239 G194 G223 G114 G207 G130 G191 G146 G175 G162 G159 G178 G143 G194 G127 G210 G111 G226 G95 G242 G79 G258 G63 G274 G47 G290 G31 G306 G15 Setting disabled Setting disabled
NL[5:0]: Sets the number of lines to drive the LCD at an interval of 8 lines. The GRAM address mapping is not affected by the number of lines set by NL[5:0]. The number of lines must be the same or more than the number of lines necessary for the size of the liquid crystal panel.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color NL[5:0] 6h00 6h01 6h02 6h1D 6h1E 6h1F 6h20 6h21 6h22 6h23 6h24 6h25 6h26 6h27 Others LCD Drive Line 8 lines 16 lines 24lines 240 lines 248 lines 256 lines 264 lines 272 lines 280 lines 288 lines 296 lines 304 lines 312 line 320 line Setting inhibited
ILI9328
NDL: Sets the source driver output level in the non-display area. NDL 0 1 Non-Display Area Positive Polarity Negative Polarity V63 V0 V0 V63
GS: Sets the direction of scan by the gate driver in the range determined by SCN[4:0] and NL[4:0]. The scan direction determined by GS = 0 can be reversed by setting GS = 1. When GS = 0, the scan direction is from G1 to G320. When GS = 1, the scan direction is from G320 to G1 REV: Enables the grayscale inversion of the image by setting REV=1. Source Output in Display Area Positive polarity negative polarity V63 V0 . . . . . . V0 V63 V0 V63 . . . . . . V63 V0
REV
GRAM Data 18h00000 . . . 18h3FFFF 18h00000 . . . 18h3FFFF
VLE: Vertical scroll display enable bit. When VLE = 1, the ILI9328 starts displaying the base image from the line (of the physical display) determined by VL[8:0] bits. VL[8:0] sets the amount of scrolling, which is the number of lines to shift the start line of the display from the first line of the physical display. Note that the partial image display position is not affected by the base image scrolling. The vertical scrolling is not available in external display interface operation. In this case, make sure to The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color set VLE = 0. VLE 0 1 Base Image Display Fixed Enable Scrolling
ILI9328
VL[8:0]: Sets the scrolling amount of base image. The base image is scrolled in vertical direction and displayed from the line determined by VL[8:0]. Make sure that VL[8:0] 320.
7.2.26. Partial Image 1 Display Position (R80h)

R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 P0[8] P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] D8 PTD D7 PTD D6 PTD D5 PTD D4 PTD D3 PTD D2 PTD D1 PTD D0 PTD
PTDP0[8:0]: Sets the display start position of partial image 1. The display areas of the partial images 1 and 2 must not overlap each another.
7.2.27. Partial Image 1 RAM Start/End Address (R81h, R82h)

R/W W W RS 1 1 D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 0 0 D9 0 A0[8] 0 PTE A0[8] A0[7] PTE A0[7] A0[6] PTE A0[6] A0[5] PTE A0[5] A0[4] PTE A0[4] A0[3] PTE A0[3] A0[2] PTE A0[2] A0[1] PTE A0[1] A0[0] PTE A0[0] D8 PTS D7 PTS D6 PTS D5 PTS D4 PTS D3 PTS D2 PTS D1 PTS D0 PTS
PTSA0[8:0] PTEA0[8:0]: Sets the start line address and the end line address of the RAM area storing the data of partial image 1. Make sure PTSA0[8:0] PTEA0[8:0].
7.2.28. Partial Image 2 Display Position (R83h)

R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 P1[8] P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0] D8 D7 D6 PTD D5 PTD D4 PTD D3 PTD D2 PTD D1 PTD D0 PTD PTD PTD
PTDP1[8:0]: Sets the display start position of partial image 2 The display areas of the partial images 1 and 2 must not overlap each another.
7.2.29. Partial Image 2 RAM Start/End Address (R84h, R85h)

R/W W W RS 1 1 D15 0 0 D14 0 0 D13 0 0 D12 0 0 D11 0 0 D10 0 0 D9 0 A1[8] A1[7] 0 PTE PTE A1[8] A1[7] A1[6] PTE A1[6] A1[5] PTE A1[5] A1[4] PTE A1[4] A1[3] PTE A1[3] A1[2] PTE A1[2] A1[1] PTE A1[1] A1[0] PTE A1[0] D8 D7 D6 PTS D5 PTS D4 PTS D3 PTS D2 PTS D1 PTS D0 PTS PTS PTS
PTSA1[8:0] PTEA1[8:0]: Sets the start line address and the end line address of the RAM area storing the data of partial image 2 Make sure PTSA1[8:0] PTEA1[8:0]. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9328
7.2.30. Panel Interface Control 1 (R90h)

R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 DIVI1 D8 DIVI0 D7 0 D6 0 D5 0 D4 RTNI4 D3 RTNI3 D2 RTNI2 D1 RTNI1 D0 RTNI0
RTNI[4:0]: Sets 1H (line) clock number of internal clock operating mode. In this mode, ILI9328 display operation is synchronized with internal clock signal. RTNI[4:0] 00000~01111 10000 10001 10010 10011 10100 10101 10110 10111 Clocks/Line Setting Disabled 16 clocks 17 clocks 18 clocks 19 clocks 20 clocks 21 clocks 22 clocks 23 clocks RTNI[4:0] 11000 11001 11010 11011 11100 11101 11110 11111 Clocks/Line 24 clocks 25 clocks 26 clocks 27 clocks 28 clocks 29 clocks 30 clocks 31 clocks
DIVI[1:0]: Sets the division ratio of internal clock frequency. DIVI1 0 0 1 1 DIVI0 0 1 0 1 Division Ratio 1 2 4 8 Internal Operation Clock Frequency fosc / 1 fosc / 2 fosc / 4 fosc / 8

R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 D9 D8 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 NOWI[2] NOWI[1] NOWI[0]
NOWI[2:0]: Sets the gate output non-overlap period when ILI9328 display operation is synchronized with internal clock signal. NOWI[2:0] 000 001 010 011 100 101 110 111 Gate Non-overlap Period 0 clocks 1 clocks 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks
Note: The gate output non-overlap period is defined by the number of frequency-divided internal clocks, the frequency of which is determined by instruction (DIVI), from the reference point.

R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 D8 D7 0 D6 0 D5 D4 D3 D2 D1 D0 DIVE1 DIVE0 RTNE5 RTNE4 RTNE3 RTNE2 RTNE1 RTNE0
RTNE[5:0]: Sets 1H (line) clock number of RGB interface mode. In this mode, ILI9328 display operation is The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color synchronized with RGB interface signals. DIVE (division ratio) x RTNE (DOTCLKs) DOTCLKs in 1H period.
ILI9328
RTNE[5:0]
Clocks per line period (1H)
RTNE[5:0]
RTNE[5:0]
RTNE[5:0]
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh
Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited Setting Prohibited
16 clocks 17 clocks 18 clocks 19 clocks 20 clocks 21 clocks 22 clocks 23 clocks 24 clocks 25 clocks 26 clocks 27 clocks 28 clocks 29 clocks 30 clocks 31 clocks
DIVE[1:0]: Sets the division ratio of DOTCLK when ILI9328 display operation is synchronized with RGB interface signals.
DIVE[1:0] 00 01 10 11 Division Ratio Setting Prohibited 1/4 1/8 1/16 18/16-bit RGB Interface Setting Prohibited 4 8 16 DOTCLKS DOTCLKS DOTCLKS DOTCLK=5MHz 0.8 s 1.6 s 3.2 s 6-bit x 3 Transfers RGB Interface Setting Prohibited 12 24 48 DOTCLKS DOTCLKS DOTCLKS DOTCLK=5MHz 0.8 s 1.6 s 3.2 s

R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 D10 D9 D8 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 NOWE3 NOWE2 NOWE1 NOWE0
NOWE[2:0]: Sets the gate output non-overlap period when the ILI9320 display operation is synchronized with RGB interface signals. NOWE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 Gate Non-overlap Period 0 clocks 1 clocks 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks NOWE[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 Gate Non-overlap Period 8 clocks 9 clocks 10 clocks 11 clocks 12 clocks 13 clocks 14 clocks 15 clocks
Note: 1 clock = (number of data transfer/pixel) x DIVE (division ratio) [DOTCLK]
7.2.34. OTP VCM Programming Control (RA1h)

R/W W RS 1 D15 0 D14 0 D13 0 D12 0 D11 OTP_ PGM_EN D10 0 D9 0 D8 0 D7 0 D6 0 D5 VCM_ OTP5 D4 VCM_ OTP4 D3 VCM_ OTP3 D2 VCM_ OTP2 D1 VCM_ OTP1 D0 VCM_ OTP0
OTP_PGM_EN: OTP programming enable. When program OTP, must set this bit. OTP data can be The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color programmed 3 times.
ILI9328
VCM_OTP[5:0]: OTP programming data for VCOMH voltage, the voltage refer to VCM[5:0] value.
7.2.35. OTP VCM Status and Enable (RA2h)

R/W W RS 1 D15 PGM_ CNT1 D14 PGM_ CNT0 D13 VCM_ D5 D12 VCM_ D4 D11 VCM_ D3 D10 VCM_ D2 D9 VCM_ D1 D8 VCM_ D0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 VCM_ EN
PGM_CNT[1:0]: OTP programmed record. These bits are read only.
OTP_PGM_CNT[1:0] 00 01 10 11
Description OTP clean OTP programmed 1 time OTP programmed 2 times OTP programmed 3 times
VCM_D[5:0]: OTP VCM data read value. These bits are read only. VCM_EN: OTP VCM data enable. 1: Set this bit to enable OTP VCM data to replace R29h VCM value. 0: Default value, use R29h VCM value.
7.2.36. OTP Programming ID Key (RA5h)

R/W W RS 1 D15 KEY 15 D14 KEY 14 D13 KEY 13 D12 KEY 12 D11 KEY 11 D10 KEY 10 D9 KEY 9 D8 KEY 8 D7 KEY 7 D6 KEY 6 D5 KEY 5 D4 KEY 4 D3 KEY 3 D2 KEY 2 D1 KEY 1 D0 KEY 0
KEY[15:0]: OTP Programming ID key protection. Before writing OTP programming data RA1h, it must write RA5h with 0xAA55 value first to make OTP programming successfully. If RA5h is not written with 0xAA55, OTP programming will be fail. See OTP Programming flow.
ILI9328
8. OTP Programming Flow

Start
Power On
Check OTP_PGM_CNT=11?
N Supply External 7.0V to DDVDH
Wait 10ms
Set ID Key RA5h=0xAA55
Program OTP VCM Data RA1h=0x08xx (xx=6 bit VCM value)
Wait 10ms
Cut Off External 7.0V Power
Reset
End
ILI9328
9. GRAM Address Map & Read/Write

ILI9328 has an internal graphics RAM (GRAM) of 87,120 bytes to store the display data and one pixel is constructed of 18 bits. The GRAM can be accessed through the i80 system, SPI and RGB interfaces.
(a) Write to GRAM

Write 0022h to index register Write GRAM data Nth pixel Write GRAM data (N+1)th pixel Write GRAM data (N+2)th pixel Write GRAM data (N+3)th pixel
(b) Read from GRAM

Write 0022h to index register Dummy Read 1st Read data Nth pixel 2nd Read data (N+1)th pixel 3rd Read data (N+2)th pixel
(a) Write to GRAM

00h 22h 1st write high byte 1st write low byte 2nd write high byte 2nd write low byte 3rd write high byte 3rd write low byte
Nth pixel
(N+1)th pixel
(N+2)th pixel
(b) Read from GRAM

00h 22h Dummy Read 1 Dummy Read 2 1st read high byte 1st read low byte 2nd read high byte 2nd read low byte
Nth pixel
(N+1)th pixel
Figure31 GRAM Read/Write Timing of i80-System Interface The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9328
GRAM address map table of SS=0, BGR=0

SS=0, BGR=0 GS=0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 . . . G311 G312 G313 G314 G315 G316 G317 G318 G319 G320 GS=1 G320 G319 G318 G317 G316 G315 G314 G313 G312 G311 . . . G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 S1S3 DB170 00000h 00100h 00200h 00300h 00400h 00500h 00600h 00700h 00800h 00900h . . . 13600h 13700h 13800h 13900h 13A00h 13B00h 13C00h 13D00h 13E00h 13F00h S4S6 DB170 00001h 00101h 00201h 00301h 00401h 00501h 00601h 00701h 00801h 00901h . . . 13601h 13701h 13801h 13901h 13A01h 13B01h 13C01h 13D01h 13E01h 13F01h S7S9 DB170 00002h 00102h 00202h 00302h 00402h 00502h 00602h 00702h 00802h 00902h . . . 13602h 13702h 13802h 13902h 13A02h 13B02h 13C02h 13D02h 13E02h 13F02h S10S12 DB170 00003h 00103h 00203h 00303h 00403h 00503h 00603h 00703h 00803h 00903h . . . 13603h 13703h 13803h 13903h 13A03h 13B03h 13C03h 13D03h 13E03h 13F03h S517S519 DB170 000ECh 001ECh 002ECh 003ECh 004ECh 005ECh 006ECh 007ECh 008ECh 009ECh . . . 136ECh 137ECh 138ECh 139ECh 13AECh 13BECh 13CECh 13DECh 13EECh 13FECh S520S522 DB170 000EDh 001EDh 002EDh 003EDh 004EDh 005EDh 006EDh 007EDh 008EDh 009EDh . . . 136EDh 137EDh 138EDh 139EDh 13AEDh 13BEDh 13CEDh 13DEDh 13EEDh 13FEDh S523S525 DB170 000EEh 001EEh 002EEh 003EEh 004EEh 005EEh 006EEh 007EEh 008EEh 009EEh . . . 136EEh 137EEh 138EEh 139EEh 13AEEh 13BEEh 13CEEh 13DEEh 13EEEh 13FEEh S526S720 DB170 000EFh 001EFh 002EFh 003EFh 004EFh 005EFh 006EFh 007EFh 008EFh 009EFh . . . 136EFh 137EFh 138EFh 139EFh 13AEFh 13BEFh 13CEFh 13DEFh 13EEFh 13FEFh
ILI9328

GRAM Data
RGB Assignment Source Output Pin
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n+1)
S (3n+2)
S (3n+3)
N=0 to 175

GRAM Data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n+1)
S (3n+2)
S (3n+3)
N=0 to 175

1st Transfer GRAM Data
DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15
2nd Transfer
DB 14 DB 13 DB 12 DB 11 DB 10 DB 9
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n+1)
S (3n+2)
S (3n+3)
N=0 to 175
GRAM Data and display data of 18-/16-/9-bit system interface (SS=0", BGR=0")
Figure32 i80-System Interface with 18-/16-/9-bit Data Bus (SS=0, BGR=0)
ILI9328
i80/M68 system 8-bit interface / SPI Interface (2 transfers/pixel)

1st transfer 2nd transfer DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10
GRAM Data
DB 17
DB 16
DB 15
DB 14
DB 13
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n+1)
S (3n+2)
S (3n+3)
N=0 to 175
i80/M68 system 8-bit interface (3 transfers/pixel, TRI=1", DFM[1:0]=00")

1st Transfer
2nd Transfer
DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15
3rd Transfer
DB 14 DB 13 DB 12 DB 11 DB 10
GRAM Data
DB 11
DB 10
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n+1)
S (3n+2)
S (3n+3)
N=0 to 175
i80/M68 system 8-bit interface (3 transfers/pixel, TRI=1", DFM[1:0]=10)

DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 17 DB 16
2nd Transfer
DB 15 DB 14 DB 13 DB 12 DB 17 DB 16
3rd Transfer
DB 15 DB 14 DB 13 DB 12
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n+1)
S (3n+2)
S (3n+3)
N=0 to 175
i80/M68 system 8-bit interface (SS=0", BGR=0")
Figure33 i80-System Interface with 8-bit Data Bus (SS=0, BGR=0)
ILI9328
GRAM address map table of SS=1, BGR=1

SS=1, BGR=1 GS=0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 . . . G311 G312 G313 G314 G315 G316 G317 G318 G319 G320 GS=1 G320 G319 G318 G317 G316 G315 G314 G313 G312 G311 . . . G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 S720S718 DB170 00000h 00100h 00200h 00300h 00400h 00500h 00600h 00700h 00800h 00900h . . . 13600h 13700h 13800h 13900h 13A00h 13B00h 13C00h 13D00h 13E00h 13F00h S717S715 DB170 00001h 00101h 00201h 00301h 00401h 00501h 00601h 00701h 00801h 00901h . . . 13601h 13701h 13801h 13901h 13A01h 13B01h 13C01h 13D01h 13E01h 13F01h S714S712 DB170 00002h 00102h 00202h 00302h 00402h 00502h 00602h 00702h 00802h 00902h . . . 13602h 13702h 13802h 13902h 13A02h 13B02h 13C02h 13D02h 13E02h 13F02h S711S709 DB170 00003h 00103h 00203h 00303h 00403h 00503h 00603h 00703h 00803h 00903h . . . 13603h 13703h 13803h 13903h 13A03h 13B03h 13C03h 13D03h 13E03h 13F03h S12S10 DB170 000ECh 001ECh 002ECh 003ECh 004ECh 005ECh 006ECh 007ECh 008ECh 009ECh . . . 136ECh 137ECh 138ECh 139ECh 13AECh 13BECh 13CECh 13DECh 13EECh 13FECh S9S7 DB170 000EDh 001EDh 002EDh 003EDh 004EDh 005EDh 006EDh 007EDh 008EDh 009EDh . . . 136EDh 137EDh 138EDh 139EDh 13AEDh 13BEDh 13CEDh 13DEDh 13EEDh 13FEDh S6S4 DB170 000EEh 001EEh 002EEh 003EEh 004EEh 005EEh 006EEh 007EEh 008EEh 009EEh . . . 136EEh 137EEh 138EEh 139EEh 13AEEh 13BEEh 13CEEh 13DEEh 13EEEh 13FEEh S3S1 DB170 000EFh 001EFh 002EFh 003EFh 004EFh 005EFh 006EFh 007EFh 008EFh 009EFh . . . 136EFh 137EFh 138EFh 139EFh 13AEFh 13BEFh 13CEFh 13DEFh 13EEFh 13FEFh
ILI9328

GRAM Data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (528-3n)
S (527-3n)
S (526-3n)
N=0 to 175

DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15
2nd Transfer
DB 14 DB 13 DB 12 DB 11 DB 10 DB 9
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (528-3n)
S (527-3n)
S (526-3n)
N=0 to 175
GRAM Data and display data of 18-/9-bit system interface (SS=1", BGR=1")
Figure 34 i80-System Interface with 18-/9-bit Data Bus (SS=1, BGR=1)
ILI9328
10. Window Address Function

The window address function enables writing display data consecutively in a rectangular area (a window address area) made on the internal RAM. The window address area is made by setting the horizontal address register (start: HSA[7:0], end: HEA[7:0] bits) and the vertical address register (start: VSA[8:0], end: VEA[8:0] bits). The AM bit sets the transition direction of RAM address (either increment or decrement). These bits enable the ILI9328 to write data including image data consecutively not taking data wrap positions into account. The window address area must be made within the GRAM address map area. Also, the GRAM address bits (RAM address set register) must be an address within the window address area. [Window address setting area] (Horizontal direction) 00H HSA[7:0] HEA[7:0] EFH (Vertical direction) 00H VSA[8:0] VEA[8:0] 13FH [RAM address, AD (an address within a window address area)]] (RAM address) HSA[7:0] AD[7:0] HEA[7:0] VSA[8:0] AD[15:8] VEA[8:0]
GRAM Address Map

00000h 000EFh
Window Address Area

2010h 2110h 203Fh 213Fh
4F10h
4F3Fh
13F00h
13FEFh
Window address setting area HSA[7:0] = 10h, HSA[7:0] = 3Fh, VSA[8:0] = 20h, VSA[8:0] = 4Fh, I/D = 1 (increment) AM = 0 (horizontal writing)
Figure 35 GRAM Access Window Map The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
ILI9328
11. Gamma Correction

ILI9328 incorporates the -correction function to display 262,144 colors for the LCD panel. The -correction is performed with 3 groups of registers determining eight reference grayscale levels, which are gradient adjustment, amplitude adjustment and fine-adjustment registers for positive and negative polarities, to make ILI9328 available with liquid crystal panels of various characteristics.
Gradient Adjustment Register

VREG1OUT
PRP/N0 PRP/N1
Fine Adjustment Registers (6 x 3 bits)

PKP/N5 PKP/N4 PKP/N3 PKP/N2 PKP/N1 PKP/N0
Amplitude Adjustment Register

VRP/N0 VRP/N1
VgP0/VgN0
V0
8 to 1 selection
VgP1/VgN1
V1 V2 ...
8 to 1 selection
VgP8/VgN8 ...
V7 V8
8 to 1 selection
VgP20/VgN20
V20 ... V43 ... V55 V56 ... V61 V62 V63
8 to 1 selection
VgP43/VgN43
8 to 1 selection
VgP55/VgN55
8 to 1 selection
VgP62/VgN62
VgP63/VgN63
VGS
Figure 36 Grayscale Voltage Generation
VREG1OUT
VROP0 0 ~ 30R 5R
RP0 RP1 RP2 RP3 RP4 RP5 RP6 RP7
ILI9328
VRN0[4:0] VgN0
1uF/10V
VRP0[4:0]
VgP0
VRON0 0 ~ 30R 5R
RN0 RN1 RN2 RN3 RN4 RN5 RN6 RN7
4R
VP1 VP2 VP3 VP4 VP5 VP6 VP7 VP8 PRP0[2:0]
PKP0[2:0]
VgP1
4R
VN1 VN2 VN3 VN4 VN5 VN6 VN7 VN8 PRN0[2:0]
PKN0[2:0]
8 to 1 Selection
8 to 1 Selection
VgN1
VRCP0 0 ~ 28R
1R
1R
1R
1R
{ { { { {
5R 8R
RP8 RP9 RP10 RP11 RP12 RP13 RP14 RP15 RP16 RP17 RP18 RP19 RP20 RP21 RP22 RP23 RP24 RP25 RP26 RP27 RP28 RP29 RP30 RP31 RP32 RP33 RP34 RP35 RP36 RP37 RP38
VP9 VP10 VP11 VP12 VP13 VP14 VP15 VP16 VP17 VP18 VP19 VP20 VP21 VP22 VP23 VP24 VP25 VP26 VP27 VP28 VP29 VP30 VP31 VP32 VP33 VP34 VP35 VP36 VP37 VP38 VP39 VP40 PRP1[2:0]
PKP1[2:0]
VRCP0 0 ~ 28R
VgP8
1R
PKP2[2:0]
VgP20
1R
PKP3[2:0]
VgP43
1R
PKP4[2:0]
VgP55
1R
{ { { { {
5R 8R
RN8 RN9 RN10 RN11 RN12 RN13 RN14 RN15 RN16 RN17 RN18 RN19 RN20 RN21 RN22 RN23 RN24 RN25 RN26 RN27 RN28 RN29 RN30 RN31 RN32 RN33 RN34 RN35 RN36 RN37 RN38
VN9 VN10 VN11 VN12 VN13 VN14 VN15 VN16 VN17 VN18 VN19 VN20 VN21 VN22 VN23 VN24 VN25 VN26 VN27 VN28 VN29 VN30 VN31 VN32 VN33 VN34 VN35 VN36 VN37 VN38 VN39 VN40
PKN1[2:0]
8 to 1 Selection
8 to 1 Selection
VgN8
PKN2[2:0]
8 to 1 Selection
8 to 1 Selection
VgN20
PKN3[2:0]
8 to 1 Selection
8 to 1 Selection
VgN43
PKN4[2:0]
8 to 1 Selection
8 to 1 Selection
VgN55
VRCP1 0 ~ 28R
RP39 RP40 RP41 RP42 RP43 RP44 RP45 RP46
4R
VP41 VP42 VP43 VP44 VP45 VP46 VP47 VP48

VP49
PKP5[2:0]
VRCN1 0 ~ 28R
RN39 RN40 RN41 RN42 RN43 RN44 RN45 RN46
PRN1[2:0] VN41 VN42 VN43 VN44 VN45 VN46 VN47 VN48

VN49
PKN5[2:0]
8 to 1 Selection
VgP62
4R
8 to 1 Selection
VgN62
VgP63
VgN63
VROP1 0 ~ 31R
RP47
VRP1[4:0]
VRON1 0 ~ 31R
RN47
VRN1[4:0]
VGS
Figure 37 Grayscale Voltage Adjustment
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 1. Gradient adjustment registers
ILI9328
The gradient adjustment registers are used to adjust the gradient of the curve representing the relationship between the grayscale and the grayscale reference voltage level. To adjust the gradient, the resistance values of variable resistors in the middle of the ladder resistor are adjusted by registers PRP0[2:0]/PRN0[2:0], PRP1[2:0]/PRN1[2:0]. The registers consist of positive and negative polarity registers, allowing asymmetric drive. 2. Amplitude adjustment registers The amplitude adjustment registers, VRP0[3:0]/VRN0[3:0], VRP1[4:0]/VRN1[4:0], are used to adjust the amplitude of grayscale voltages. To adjust the amplitude, the resistance values of variable resistors at the top and bottom of the ladder resistor are adjusted. Same as the gradient registers, the amplitude adjustment registers consist of positive and negative polarity registers. 3. Fine adjustment registers The fine adjustment registers are used to fine-adjust grayscale voltage levels. To fine-adjust grayscale voltage levels, fine adjustment registers adjust the reference voltage levels, 8 levels for each register generated from the ladder resistor, in respective 8-to-1 selectors. Same with other registers, the fine adjustment registers consist of positive and negative polarity registers.
Grayscale voltage
Grayscale voltage
Gradient adjustment
Amplitude adjustment
Grayscale voltage
Fine adjustment
Figure 38 Gamma Curve Adjustment
Register Groups Gradient adjustment Amplitude adjustment
Positive Polarity PRP0 [2:0] PRP1 [2:0] VRP0 [3:0] VRP1 [4:0] KP0 [2:0] KP1 [2:0] KP2 [2:0] KP3 [2:0] KP4 [2:0] KP5 [2:0]
Negative Polarity PRN0 [2:0] PRN1 [2:0] VRN0 [3:0] VRN1 [4:0] KN0 [2:0] KN1 [2:0] KN2 [2:0] KN3 [2:0] KN4 [2:0] KN5 [2:0]
Description Variable resistor VRCP0, VRCN0 Variable resistor VRCP1, VRCN1 Variable resistor VROP0, VRON0 Variable resistor VROP1, VRON1 8-to-1 selector (voltage level of grayscale 1) 8-to-1 selector (voltage level of grayscale 8) 8-to-1 selector (voltage level of grayscale 20) 8-to-1 selector (voltage level of grayscale 43) 8-to-1 selector (voltage level of grayscale 55) 8-to-1 selector (voltage level of grayscale 62)
Fine adjustment
ILI9328
Ladder resistors and 8-to-1 selector Block configuration The reference voltage generating block consists of two ladder resistor units including variable resistors and 8-to-1 selectors. Each 8-to-1 selector selects one of the 8 voltage levels generated from the ladder resistor unit to output as a grayscale reference voltage. Both variable resistors and 8-to-1 selectors are controlled according to the -correction registers. This unit has pins to connect a volume resistor externally to compensate differences in various characteristics of panels. Variable resistors ILI9328 uses variable resistors of the following three purposes: gradient adjustment (VRCP(N)0/VRCP(N)1); amplitude adjustment (1) (VROP(N)0); and the amplitude adjustment (2) (VROP(N)1). The resistance values of these variable resistors are set by gradient adjustment registers and amplitude adjustment registers as follows.
Gradient adjustment PRP(N)0/1[2:0] VRCP(N)0 Register Resistance 000 0R 001 4R 010 8R 011 12R 100 16R 101 20R 110 24R 111 28R Amplitude adjustment (1) VRP(N)0[3:0] VROP(N)0 Register Resistance 0000 0R 0001 2R 0010 4R : : : : 1101 26R 1111 28R 1111 30R Amplitude adjustment (2) VRP(N)1[4:0] VROP(N)1 Register Resistance 00000 0R 00001 1R 00010 2R : : : : 11101 29R 11110 30R 11111 31R
8-to-1 selectors The 8-to-1 selector selects one of eight voltage levels generated from the ladder resistor unit according to the fine adjustment register and output the selected voltage level as a reference grayscale voltage (VgP(N)1~6). The table below shows the setting in the fine adjustment register and the selected voltage levels for respective reference grayscale voltages.
Fine adjustment registers and selected voltage Register Selected Voltage KP(N)[2:0] VgP(N)1 VgP(N)8 VgP(N)20 VgP(N)43 000 VP(N)1 VP(N)9 VP(N)17 VP(N)25 001 VP(N)2 VP(N)10 VP(N)18 VP(N)26 010 VP(N)3 VP(N)11 VP(N)19 VP(N)27 011 VP(N)4 VP(N)12 VP(N)20 VP(N)28 100 VP(N)5 VP(N)13 VP(N)21 VP(N)29 101 VP(N)6 VP(N)14 VP(N)22 VP(N)30 110 VP(N)7 VP(N)15 VP(N)23 VP(N)31 111 VP(N)8 VP(N)16 VP(N)24 VP(N)32
VgP(N)55 VP(N)33 VP(N)34 VP(N)35 VP(N)36 VP(N)37 VP(N)38 VP(N)39 VP(N)40
VgP(N)62 VP(N)41 VP(N)42 VP(N)43 VP(N)44 VP(N)45 VP(N)46 VP(N)47 VP(N)48
ILI9328
Source Driver Output (S[384:1])
VCOM
Negative polarity
Postive polarity
Figure 39 Relationship between Source Output and VCOM
V0
Negative Polarity Source Output Levels
Positive Polarity
V63 000000 GRAM Data 111111
Figure 40 Relationship between GRAM Data and Output Level
ILI9328
12. Application
12.1. Configuration of Power Supply Circuit
To Panel
DUMMY1 TEST1 IOGNDDUM TESTO1 TESTO2 TESTO3 IM0/ID IM1 IM2 IM3 TEST2 TESTO4 TESTO5 TESTO6 TESTO7 TESTO8 TESTO9 TESTO10 nRESET nRESET VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 TESTO11 DB12 DB11 DB10 DB9 DB8 TEST3 TESTO12 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 TESTO13 SDO SDI nRD nWR/SCL RS nCS TESTO14 TESTO15 FMARK TESTO16 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 DUMMY2 IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD DUMMY3 GND GND GND GND GND GND GND GND VGS VGS GND GND GND GND GND GND GND GND GND GND DUMMY4 DUMMY5 DUMMY6 VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VREG1OUT VREG1OUT VREG1OUT DUMMY7 DUMMY8 DUMMY9 VCL VCL VCL VCL VCL DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH VCI1 VCI1 VCI1 VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI DUMMY10 DUMMY11 C12C12C12C12C12C12+ C12+ C12+ C12+ C12+ C11C11C11C11C11C11+ C11+ C11+ C11+ C11+ VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL GND GND GND VGH VGH VGH VGH VGH VGH DUMMY12 DUMMY13 C13C13C13C13C13+ C13+ C13+ C13+ C21C21C21C21C21C21C21C21+ C21+ C21+ C21+ C21+ C21+ C21+ C22C22C22C22C22C22C22C22+ C22+ C22+ C22+ C22+ C22+ C22+ DUMMY14 DUMMY15
IM1 IM3
IM0 IM2
< 100 ohm < 100 ohm < 100 ohm < 100 ohm
DUMMY27 G319 G317 G315 G313 G311 G309 G307 G305 G303
1 1 0
nRESET HSYNC ENABLE DB16 DB14 DB12 DB10 DB8 DB6 DB4 DB2 DB0 SDI nWR nCS Fmark VSYNC DOTCLK DB17 DB15 DB13 DB11 DB9 DB7 DB5 DB3 DB1 SDO nRD RS
< 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm < 100 ohm
IOVCC
< 15 ohm
1uF/6.3V
< 10 ohm
< 5 ohm
< 50 ohm
< 5 ohm
.
S353 S354 S355 S356 S357 S358 S359 S360 DUMMY24 DUMMY23 S361 S362 S363 S364 S365 S366 S367 S368 S369
2 0 3 0 4 0 5 0 6 0 7 0 8 0
G17 G15 G13 G11 G9 G7 G5 G3 G1 DUMMY26 DUMMY25 S1 S2 S3 S4 S5 S6 S7 S8 S9
Face Up (Bump View)
9 0 1 0 0 1 1 0
< 10 ohm
1uF/6.3V 1uF/6.3V 1uF/6.3V
< 20 ohm
1 2 0
< 20 ohm < 20 ohm
1 3 0
1uF/6.3V 1uF/10V
VCL
< 20 ohm
DDVDH
< 15 ohm < 15 ohm
1 4 0
1uF/6.3V
VCI
< 5 ohm
1uF/6.3V
< 10 ohm
< 10 ohm
1uF/6.3V
< 10 ohm
< 10 ohm
VCL 1uF/25V
< 15 ohm
.
S712 S713 S714 S715 S716 S717 S718 S719 S720 DUMMY22 DUMMY21 G2 G4 G6 G8 G10 G12 G14 G16 G18
1 5 0
X
1 6 0 1 7 0 1 8 0 1 9 0
< 40 ohm
1uF/25V
2 0 0
< 15 ohm
1uF/6.3V
< 15 ohm < 15 ohm
2 1 0
1uF/10V
< 15 ohm
< 15 ohm
1uF/10V
< 15 ohm
G304 G306 G308 G310 G312 G314 G316 G318 G320 DUMMY20
2 2 0 2 3 0
< 15 ohm
Figure 41 Power Supply Circuit Block
2 4 0 2 4 3
To Panel
ILI9328
The following table shows specifications of external elements connected to the ILI9328s power supply circuit.
Items Recommended Specification 6.3V 10V 25V Schottky diode VF<0.4V/20mA at 25C, VR 30V (Recommended diode: HSC226) VREG1OUT, Pin connection VCI1, VDDD, VCL, VCOMH,
Capacity 1 F (B characteristics)
VCOML, C11+/-, C12+/-, C13+/-, DDVDH, C21+/-, C22+/-
VGH, VGL
(VCL VGL), (DDVDH VGH), (Vci DDVDH)
ILI9328
12.2. Display ON/OFF Sequence
Figure 42 Display On/Off Register Setting Sequence
ILI9328
12.3. Standby and Sleep Mode
Standby
Display Off Sequence
Sleep
Display Off Sequence
Set Standby (STB = 1)
Set Sleep (SLP = 1)
Release from Standby (STB = 0)
Release from standby
Release from Sleep (SLP = 0)
Release from Sleep
R10 0190h
80ms or more Stabilizing time 80ms or more Stabilizing time
R10 0190h
Display On Sequence
Display On Sequence
Figure 43 Standby/Sleep Mode Register Setting Sequence
ILI9328
12.4. Power Supply Configuration

When supplying and cutting off power, follow the sequence below. The setting time for step-up circuits and operational amplifiers depends on external resistance and capacitance.
Power Supply ON (VCC, VCI, IOVCC) VCI IOVCC GND VCI IOVCC or VCI, IOVCC Simultaneously Display OFF Setting Power On Reset and Display OFF
DTE = 0 D[1:0] = 00 GON = 0 PON = 0
Display ON Setting
Normal Display
DTE=1 D[1:0]=11 GON=1
Display OFF Sequence
Display OFF
LCD Power Supply ON Sequence 50ms or more Stabilizing time
Registers setting before power supply startup
Power supply initial setting

Set VC[2:0], VRH[3:0], VCM[5;0], VDV[5:0], PON=0,BT[2:0] = 000
Power Supply Halt Setting
SAP=0 AP[2:0] = 000 PON = 0
Power Supply OFF (VCC, VCI, IOVCC) IOVCC Registers setting for power supply startup Power supply operation setting
Set BT[2:0],PON = 1, Set AP[2:0],APE=1, Set DC1[2:0], DC0[2:0]
VCI GND VCI
IOVCC
80ms or more Step-up circuit stabilizing time
Or IOVCC, VCI Simultaneously
Operational Amplifier stabilizing time
Set the other registers
Display ON Sequence
Set SAP=1
Display ON
DTE=1 D[1:0]=11 GON=1
Figure 44 Power Supply ON/OFF Sequence
ILI9328
12.5. Voltage Generation

The pattern diagram for setting the voltages and the waveforms of the voltages of the ILI9328 are as follows.
VGH (+9 ~ 16.5V)
VLCD (4.5 ~ 5.5V) VREG1OUT (3.0 ~ (VLCD-0.2)V ) VCOMH (3.0 ~ (VLCD-0.2)V ) Vci
(2.5 ~ 3.3V)
VCOML (VCL+0.5) ~ -1V ) VCL (0 ~ -3.3V) VGL (-4.0 ~ -16.5V)
Figure 45 Voltage Configuration Diagram Note: The DDVDH, VGH, VGL, and VCL output voltage levels are lower than their theoretical levels (ideal voltage levels) due to current consumption at respective outputs. The voltage levels in the following relationships (DDVDH VREG1OUT ) > 0.2V and (VCOML VCL) > 0.5V are the actual voltage levels. When the alternating cycles of VCOM are set high (e.g. the polarity inverts every line cycle), current consumption is large. In this case, check the voltage before use.
ILI9328
12.6. Applied Voltage to the TFT panel
VGH Gate Output VCOM Source output
VGL
Figure 46 Voltage Output to TFT LCD Panel
12.7. Partial Display Function

The ILI9328 allows selectively driving two partial images on the screen at arbitrary positions set in the screen drive position registers. The following example shows the setting for partial display function:
Base Image Display Setting BASEE NL[5:0] 0 6h27 Partial Image 1 Display Setting PTDE0 PTSA0[8:0] PTEA0[8:0] PTDP0[8:0] 1 9h000 9h00F 9h080 Partial Image 2 Display Setting PTDE1 PTSA1[8:0] PTEA1[8:0] PTDP1[8:0] 1 9h020 9h02F 9h0C0
ILI9328
PTSA0=9'h000
GRAM MAP
Partial Image 1 GRAM Area
LCD Panel
0 (1st line) 1 (2nd line) 2 (3rd line)
PTEA0=9'h00F PTSA1=9'h020 Partial Image 2 GRAM Area PTEA1=9'h02F Partial Image 1 Display Area
PTDP0=9'h080
PTDP1=9'h0C0 Partial Image 1 Display Area
319 (320th line)
Figure 47 Partial Display Example
12.8. Resizing Function

ILI9328 supports resizing function (x1/2, x1/4), which is performed when writing image data to GRAM. The resizing function is enabled by setting a window address area and the RSZ bit which represents the resizing factor (x1/2, x1/4) of image. The resizing function allows the system to transfer the original-size image data into the GRAM with resized image data.
ILI9328
GRAM Data
Original Image Data 0 0 1 2 3 4 5 6

(0,0) (1,0) (2,0) (3,0) (4,0) (5,0) (6,0)
1
(0,1) (1,1) (2,1) (3,1) (4,1) (5,1) (6,1)
2
(0,2) (1,2) (2,2) (3,2) (4,2) (5,2) (6,2)
3
(0,3) (1,3) (2,3) (3,3) (4,3) (5,3) (6,3)
4
(0,4) (1,4) (2,4) (3,4) (4,4) (5,4) (6,4)
5
(0,5) (1,5) (2,5) (3,5) (4,5) (5,5) (6,5)
6
(0,6) (1,6) (2,6) (3,6) (4,6) (5,6) (6,6) (0,0) (0,2) (2,2) (4,2) (6,2) (0,4) (2,4) (4,4) (6,4) (0,6) (2,6) (4,6) (6,6) (2,0) (4,0) (6,0)
? resizing
Figure 48 Data transfer in resizing
Original Data 240
Panel Display
120 RSZ=2'h1 320 160

Write to GRAM
Figure 49 Resizing Example Resized Image Resolution 1/2 (RSZ=2h1) 1/4 (RSZ=2h3) 320 240 160 120 176 144 88 72 160 120 80 60 88 72 44 36 60 80 30 40 66 66 33 33
Original Image Size (X Y) 640 480 352 288 320 240 176 144 120 160 132 132
The RSZ bit sets the resizing factor of an image. When setting a window address area in the internal GRAM, the GRAM window address area must fit the size of resized image. The following example show the resizing setting. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
X
ILI9328
dx= (X-H)/N, H=X mod N dy= (Y-V)/N, V=Y mod N
GRAM Address
(X0, Y0)
dx
Original Image Size
dy
(X0+dx-1, Y0+dy-1)
Original image data number in horizontal direction Original image data number in Vertical direction Resizing Ration Resizing Setting Remainder pixels in horizontal direction Remainder pixels in vertical direction GRAM writing start address RSZ RCH RCV AD HSA GRAM window setting HEA VSA VEA
X Y 1/N N-1 H V (x0, y0) x0 x0+dx-1 y0 y0+dy-1
ILI9328
13. Electrical Characteristics

13.1. Absolute Maximum Ratings
The absolute maximum rating is listed on following table. When ILI9328 is used out of the absolute maximum ratings, the ILI9328 may be permanently damaged. To use the ILI9328 within the following electrical characteristics limit is strongly recommended for normal operation. If these electrical characteristic conditions are exceeded during normal operation, the ILI9328 will malfunction and cause poor reliability. Item Symbol Unit Power supply voltage (1) IOVCC V Power supply voltage (1) VCI - GND V Power supply voltage (1) DDVDH - GND V Power supply voltage (1) GND -VCL V Power supply voltage (1) DDVDH - VCL V Power supply voltage (1) VGH - GND V Power supply voltage (1) GND - VGL V Input voltage Vt V Operating temperature Topr C Storage temperature Tstg C Notes: 1. GND must be maintained 2. (High) (VCC = VCC) GND (Low), (High) IOVCC GND (Low). 3. Make sure (High) VCI GND (Low). 4. Make sure (High) DDVDH GND (Low). 5. Make sure (High) DDVDH VCL (Low). 6. Make sure (High) VGH GND (Low). 7. Make sure (High) GND VGL (Low). 8. For die and wafer products, specified up to 85C. 9. This temperature specifications apply to the TCP package Value -0.3 ~ + 4.6 -0.3 ~ + 4.6 -0.3 ~ + 6.0 -0.3 ~ + 4.6 -0.3 ~ + 9.0 -0.3 ~ + 18.5 -0.3 ~ + 18.5 -0.3 ~ VCC+ 0.3 -40 ~ + 85 -55 ~ + 110 Note 1, 2 1, 4 1, 4 1 1, 5 1, 5 1, 6 1 8, 9 8, 9
ILI9328
Typ.
100 (VCC)
13.2. DC Characteristics
(VCC = VCI=2.40 ~ 3.0V, IOVCC = 1.65 ~ 3.30V, Ta= -40 ~ 85 C) Item Symbol Unit Test Condition
Input high voltage Input low voltage Output high voltage(1) ( DB0-17 Pins) Output low voltage ( DB0-17 Pins) I/O leakage current Current consumption during normal operation (VCC GND ) Current consumption during standby mode (VCC GND ) VCI=2.8V , VREG1OUT =4.8V LCD Drive Power Supply Current ( DDVDH-GND ) LCD Driving Voltage ( DDVDH-GND ) Output deviation voltage Output offset voltage ILCD mA DDVDH=5.2V , Frame Rate: 70Hz, line-inversion, Ta=25 C, GRAM data = 0000h, DDVDH VDEV VOFFSET V mV mV Note1 4.5 6 20 35 5.5 IST A VCI=2.8V , Ta=25 C 30 50 IOP A VIH VIL VOH1 VOL1 ILI V V V V A IOVCC= 1.8 ~ 3.3V IOVCC= 1.8 ~ 3.3V IOH = -0.1 mA IOVCC=1.65~3.3V Vin = 0 ~ VCC VCC=2.8V , Ta=25C , fOSC = 512KHz ( Line) GRAM data = 0000h
Min.
0.8*IOV CC -0.3 0.8*IOV CC -0.1 -
Max.
IOVCC 0.2*IOVCC 0.2*IOVCC 0.1 -
Note
-
Note1: The Max. value is between with measure point and Gamma setting value.
13.3. Reset Timing Characteristics

Reset Timing Characteristics (IOVCC = 1.65 ~ 3.3 V) Item Symbol Unit Min. Typ.
Reset low-level width Reset rise time Reset high-level width tRES_L trRES tRES_H ms s ms 1 50 -
Max.
10 -
13.4. AC Characteristics
13.4.1. i80-System Interface Timing Characteristics
Normal Write Mode (IOVCC = 1.65~3.3V)
Item Bus cycle time Write Symbol tCYCW Unit ns Min. 100 Typ. Max. Test Condition -
Read Write low-level pulse width Write high-level pulse width Read low-level pulse width Read high-level pulse width Write / Read rise / fall time Write ( RS to nCS, E/nWR ) Setup time Read ( RS to nCS, RW/nRD ) Address hold time Write data set up time Write data hold time Read data delay time Read data hold time tCYCR PWLW PWHW PWLR PWHR tWRr/tWRf tAS tAH tDSW tH tDDR tDHR ns ns ns ns ns ns ns ns ns ns ns ns 300 50 50 150 150 10 5 5 10 15 5 25 100 -
ILI9328
-
RS
VIH VIL tAS tAH
VIH VIL
nCS PWLW, PWLR nWR, nRD tWRf VIH VIL VIH VIL PWHW, PWHR VIH tWRr tH Valid Data tDHR VOH VOL Valid Data VOH VOL VIH VIL tCYCW, tCYCR
tDSW Write Data DB[17:0] tDDR Read Data DB[17:0] VIH VIL
Figure 50 i80-System Bus Timing
13.4.2. Serial Data Transfer Interface Timing Characteristics

(IOVCC= 1.65 ~ 3.3V)
Item Serial clock cycle time Serial clock high level pulse width Serial clock low level pulse width Serial clock rise / fall time Write ( received ) Read ( transmitted ) Write ( received ) Read ( transmitted ) Write ( received ) Read ( transmitted ) Symbol tSCYC tSCYC tSCH tSCH tSCL tSCL tSCr, tSCf Unit ns ns ns ns ns ns ns Min. 100 200 40 100 40 100 Typ. Max. 5 Test Condition
Item Chip select set up time Chip select hold time Serial input data set up time Serial input data hold time Serial output data set up time Serial output data hold time Symbol tCSU tCH tSISU tSIH tSOD tSOH Unit ns ns ns ns ns ns Min. 10 50 20 20 5 Typ. Max. 100 -
ILI9328
Test Condition
nCS
VIL tCSU tSCr VIL tSISU tSCYC tSCf tSCL VIH VIL VIL VIH tCH
VIH
tSCH VIH
SCL
VIH VIL
tSIH Input Data VIH VIL Input Data
SDI tSOD SDO
VIH VIL
VOH VOL
Output Data
VOH VOL
Output Data
VOH VOL
Figure 51 SPI System Bus Timing
13.4.3. RGB Interface Timing Characteristics

18/16-bit Bus RGB Interface Mode (IOVCC = 1.65 ~ 3.3V)
Item
VSYNC/HSYNC setup time ENABLE setup time ENABLE hold time PD Data setup time PD Data hold time DOTCLK high-level pulse width DOTCLK low-level pulse width DOTCLK cycle time DOTCLK, VSYNC, HSYNC, rise/fall time
Symbol tSYNCS tENS tENH tPDS tPDH PWDH PWDL tCYCD trghr, trghf
Unit ns ns ns ns ns ns ns ns ns
Min. 0 10 10 10 40 40 40 100 -
Typ. -
Max. 25
Test Condition -
6-bit Bus RGB Interface Mode (IOVCC = 1.65 ~ 3.3V)

Item
VSYNC/HSYNC setup time ENABLE setup time ENABLE hold time PD Data setup time PD Data hold time DOTCLK high-level pulse width DOTCLK low-level pulse width DOTCLK cycle time
Symbol tSYNCS tENS tENH tPDS tPDH PWDH PWDL tCYCD
Unit ns ns ns ns ns ns ns ns
Min. 0 10 10 10 30 30 30 80
Typ. -
Max. -
Test Condition -
a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color DOTCLK, VSYNC, HSYNC, rise/fall time
trghr, trghf ns 25
ILI9328
-
trgbf trgbr VIH VIL tASE
tSYNCS
tENS VIH VIL trgbf VIH VIL tPDS VIH VIL PWDL trgbr VIH
tENH VIH VIL PWDH VIH
VIL
tCYCD tPDH Write Data VIH VIL
Figure52 RGB Interface Timing
ILI9328
14. Revision History

Version No. V0.1 Date 2008/10/28 Page New created. Description

A-Si TFT LCD Single Chip Driver 240Rgbx320 Resolution and 262K Color Datasheet

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A-Si TFT LCD Single Chip Driver 240Rgbx320 Resolution and 262K Color Datasheet

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ILI9328

Version: V0.1 Document No.: ILI9328DS_V0.1.pdf

ILI TECHNOLOGY CORP.

7.6. 8.1. 8.2.

8. Register Descriptions .................................................................................................................................. 47

Control Register (CR)

Address Counter (AC)

LCD Source Driver

Grayscale Reference Voltage

VCC VDDD GND DUMMY1~15

Graphics RAM (GRAM)

LCD Gate Driver

VCI VCI1 GND

Charge-pump Power Circuit

IM3, IM2, IM1, IM0/ID

MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc

MPU IOVcc MPU IOVcc

VCOM VCOMH VCOML VGS

VDDD GND DUMMY1~ 15 DUMMY20 ~ 27 IOGNDDUM TESTO1~16 TEST1, 2, 3 TS0~8

Power Power supply GND Open IOGND OPEN

Liquid Crystal Voltages

Internal Step-up Circuits

4.1. Pad Arrangement and Coordination

G17 G15 G13 G11 G9 G7 G5 G3 G1 DUMMY 26 DUMM Y 25 S1 S2 S3 S4 S5 S6 S7 S8 S9

Face Up (Bump View)

No. 121 122 123 124

Name VCOML VCOML VCOML VCOML

Alignment mark 1-a 1-b

DUMMY20~27 (No. 244 ~ 1291)

I/O Pads (No. 1 ~ 243)

X=20, 30, 35 Y=70, 80, 85

Parallel RGB Interface

Address Counter (AC)

Graphics RAM (GRAM)

Grayscale Voltage Generating Circuit

LCD Driver Circuit

LCD Driver Power Supply Circuit

nCS RS nWR nRD DB[17:0]

Figure1 System Interface and RGB Interface connection

6.2. Input Interfaces

DB[17:10], DB[8:1] DB[17:10] SDI, SDO

6.2.1. i80/18-bit System Interface

nCS A2 nWR nRD D[31:0]

nCS RS nWR nRD DB[17:0]

18-bit System Interface (262K colors) TRI=0, DFM[1:0]=00

Write Data Register

GRAM Data & RGB Mapping

Figure2 18-bit System Interface Data Format

6.2.2. i80/16-bit System Interface

80-system 16-bit interface (2 transfers/pixel) 262,144 colors 1 0

80-system 16-bit interface (2 transfers/pixel) 262,144 colors 1 1

Figure3 16-bit System Interface Data Format

6.2.3. i80/9-bit System Interface

nCS A1 nWR nRD D[8:0]

nCS RS nWR nRD DB[17:9]

9-bit System Interface (262K colors) TRI=0, DFM[1:0]=00

Write Data Register

GRAM Data & RGB Mapping

Figure4 9-bit System Interface Data Format

6.2.4. i80/8-bit System Interface

80-system 8-bit interface (3 transfers/pixel) 262,144 colors 1 0

80-system 8-bit interface (3 transfers/pixel) 262,144 colors 1 1

nWR Upper/ Lower