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8085
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8-bit microprocessor Up to 8 MHz 64 KB RAM Single voltage On-chip peripherals 256 I/O ports 8080 object-code compatible

40-pin DIP 44-pin PLCC

8086
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16-bit microprocessor 16-bit data bus Up to 10 MHz 1 MB RAM 64K I/O ports

40-pin DIP 56-pin QFP 44-pin PLCC

The third x86 generation of x86 microprocessors, Intel 80386 (i386) was a 32-bit microprocessor backwards compatible with previous generations of 80x86 CPUs. Major new feature in the i386 CPU was 80386 protected mode - this mode fixed many shortcomings that existed in the 80286 processor and in the 80286 protected mode:
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The 80386 mode included complete set of 32-bit registers and 32-bit instructions. Although in this mode the CPU still used memory segment architecture similar to the one present in earlier x86 microprocessors, the size of memory segments was increased to 4 GB. This simplified development of 32-bit software, and in most cases applications could run without worrying about switching memory segments. It became possible to switch from protected mode back to real-mode without simulating processor reset.

Another new mode in the 80386 CPU was 8086 virtual mode. In this mode the CPU could run old 8086 applications while providing necessary protection of memory and other resources. Introduction of this mode and 80386 protected mode was very significant step. All current 32-

bit x86-based operating systems use these modes to run legacy 16-bit and more modern 32-bit applications. There were a few different versions of the 80386 CPUs:
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80386DX - this CPU could work with 16-bit and 32-bit external buses. 80386SX - low cost version of the 80386. This processor had 16 bit external data bus and 24-bit external address bus. 80386SL - low-power microprocessor with power management features, with 16-bit external data bus and 24-bit external address bus. The processor included ISA bus controller, memory controller and cache controller. Embedded 80376 and 80386EX processors.

The Intel 80386 was produced at speeds up to 33 MHz, AMD produced even faster 40 MHz version.

Accumulator Accumulator is nothing but a register which can hold 8-bit data. Accumulator aids in storing two quantities. The data to be processed by arithmetic and logic unit is stored in accumulator. It also stores the result of the operation carried out by the Arithmetic and Logic unit. The accumulator is also called an 8-bit register. The accumulator is connected to Internal Data bus and ALU (arithmetic and logic unit). The accumulator can be used to send or receive data from the Internal Data bus. Arithmetic and Logic Unit There is always a need to perform arithmetic operations like +, -, *, / and to perform logical operations like AND, OR, NOT etc. So there is a necessity for creating a separate unit which can perform such types of operations. These operations are performed by the Arithmetic and Logic Unit (ALU). ALU performs these operations on 8-bit data. But these operations cannot be performed unless we have an input (or) data on which the desired operation is to be performed. So from where do these inputs reach the ALU? For this purpose accumulator is used. ALU gets its Input from accumulator and temporary register. After processing the necessary operations, the result is stored back in accumulator. General Purpose Registers Apart from accumulator 8085 consists of six special types of registers called General Purpose Registers. What do these general purpose registers do?

These general purpose registers are used to hold data like any other registers. The general purpose registers in 8085 processors are B, C, D, E, H and L. Each register can hold 8-bit data. Apart from the above function these registers can also be used to work in pairs to hold 16-bit data. They can work in pairs such as B-C, D-E and H-L to store 16-bit data. The H-L pair works as a memory pointer. A memory pointer holds the address of a particular memory location. They can store 16-bit address as they work in pair.

Program Counter and Stack Pointer Program counter is a special purpose register. Consider that an instruction is being executed by processor. As soon as the ALU finished executing the instruction, the processor looks for the next instruction to be executed. So, there is a necessity for holding the address of the next instruction to be executed in order to save time. This is taken care by the program counter. A program counter stores the address of the next instruction to be executed. In other words the program counter keeps track of the memory address of the instructions that are being executed by the microprocessor and the memory address of the next instruction that is going to be executed. Microprocessor increments the program whenever an instruction is being executed, so that the program counter points to the memory address of the next instruction that is going to be executed. Program counter is a 16-bit register. Stack pointer is also a 16-bit register which is used as a memory pointer. A stack is nothing but the portion of RAM (Random access memory). So does that mean the stack pointer points to portion of RAM? Yes. Stack pointer maintains the address of the last byte that is entered into stack. Each time when the data is loaded into stack, Stack pointer gets decremented. Conversely it is incremented when data is retrieved from stack. Temporary Register:

As the name suggests this register acts as a temporary memory during the arithmetic and logical operations. Unlike other registers, this temporary register can only be accessed by the microprocessor and it is completely inaccessible to programmers. Temporary register is an 8bit register. In the next article let us discuss about the
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FLAGS TIMING AND CONTROL UNIT INTERRUPT CONTROL

In the previous articles we learnt about what are microprocessors in general and the about the 8085 microprocessor in particular. We saw the various registers used in 8085 microprocessor and how they act along with Arithmetic and Logic unit to process a data. But Registers and ALU alone cannot successfully process a data and provide the result to the programmer. There are various other units which help in data transfer and addressing, Carry operation while adding or subtracting, and sometimes also to interrupt a process when necessary. Let us discuss about those units in detail.

Architecture Diagram

Flags
Flags are nothing but a group of individual Flip-flops. The flags are mainly associated with arithmetic and logic operations. The flags will show either a logical (0 or 1) (i.e.) a set or reset depending on the data conditions in accumulator or various other registers. A flag is actually a latch which can hold some bits of information. It alerts the processor that some event has taken place.
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But why are they called flags? The possible solution is from the small flags which are found on the mail boxes in America. The small flag indicates that there is a mail in the mail box. Similarly this denotes that an event has occurred in the processor. Intel processors have a set of 5 flags.
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Carry flag Parity flag Auxiliary carry flag Zero flag Sign flag

Consider two binary numbers. For example: 1100 0000 1000 0000 When we add the above two numbers, a carry is generated in the most significant bit. The number in the extreme right is least significant bit, while the number in extreme left is most significant bit. So a ninth bit is generated due to the carry. So how to accommodate 9th bit in an 8 bit register? For this purpose the Carry flag is used. The carry flag is set whenever a carry is generated and reset whenever there is no carry.

But there is an auxiliary carry flag? What is the difference between the carry flag and auxiliary carry flag? Lets discuss with an example. Consider the two numbers given below 0000 0100, 0000 0101 When we add both the numbers a carry is generated in the third bit from the least significant bit. This sets the auxiliary carry flag. When there is no carry, the auxiliary carry flag is reset. So whenever there is a carry in the most significant bit Carry flag is set. While an auxiliary carry flag is set only when a carry is generated in bits other than the most significant bit.

Parity checks whether its even or add parity. This flag returns a 0 if it is odd parity and returns a 1 if it is an even parity. Sometimes they are also called as parity bit which is used to check errors while data transmission is carried out. Zero flag shows whether the output of the operation is 0 or not. If the value of Zero flag is 0 then the result of operation is not zero. If it is zero the flag returns value 1. Sign flag shows whether the output of operation has positive sign or negative sign. A value 0 is returned for positive sign and 1 is returned for negative sign.

Instruction Register and Decoder

Instruction register is 8-bit register just like every other register of microprocessor. Consider an instruction. The instruction may be anything like adding two data's, moving a data, copying a data etc. When such an instruction is fetched from memory, it is directed to Instruction register. So the instruction registers are specifically to store the instructions that are fetched from memory. There is an Instruction decoder which decodes the informations present in the Instruction register for further processing.

Timing and Control Unit

Timing and control unit is a very important unit as it synchronizes the registers and flow of data through various registers and other units. This unit consists of an oscillator and controller sequencer which sends control signals needed for internal and external control of data and other units. The oscillator generates two-phase clock signals which aids in synchronizing all the registers of 8085 microprocessor. Signals that are associated with Timing and control unit are: Control Signals: READY, RD, WR, ALE Status Signals: S0, S1, IO/M DMA Signals: HOLD, HLDA RESET Signals: RESET IN, RESET OUT

Interrupt Control
As the name suggests this control interrupts a process. Consider that a microprocessor is executing the main program. Now whenever the interrupt signal is enabled or requested the microprocessor shifts the control from main program to process the incoming request and after the completion of request, the control goes back to the main program. For example an Input/output device may send an interrupt signal to notify that the data is ready for input. The microprocessor temporarily stops the execution of main program and transfers control to I/O device. After collecting the input data the control is transferred back to main program. Interrupt signals present in 8085 are: INTR RST 7.5 RST 6.5 RST 5.5 TRAP Of the above four interrupts TRAP is a NON-MASKABLE interrupt control and other three are maskable interrupts. A non-maskable interrupt is an interrupt which is given the highest priority in the order of interrupts. Suppose you want an instruction to be processed immediately, then you can give the instruction as a non-maskable interrupt. Further the non-maskable interrupt cannot be disabled by programmer at any point of time. Whereas the maskable interrupts can be disabled and enabled using EI and DI instructions. Among the maskable interrupts RST 7.5 is given the highest priority above RST 6.5 and least priority is given to INTR.

Serial I/O control

The input and output of serial data can be carried out using 2 instructions in 8085. SID-Serial Input Data SOD-Serial Output Data Two more instructions are used to perform serial-parallel conversion needed for serial I/O devices. SIM RIM

Address buffer and Address-Data buffer

The contents of the stack pointer and program counter are loaded into the address buffer and address-data buffer. These buffers are then used to drive the external address bus and addressdata bus. As the memory and I/O chips are connected to these buses, the CPU can exchange desired data to the memory and I/O chips. The address-data buffer is not only connected to the external data bus but also to the internal data bus which consists of 8-bits. The address data buffer can both send and receive data from internal data bus. Address bus and Data bus: We know that 8085 is an 8-bit microprocessor. So the data bus present in the microprocessor is also 8-bits wide. So 8-bits of data can be transmitted from or to the microprocessor. But 8085 processor requires 16 bit address bus as the memory addresses are 16-bit wide. The 8 most significant bits of the address are transmitted with the help of address bus and the 8 least significant bits are transmitted with the help of multiplexed address/data bus. The eight bit data bus is multiplexed with the eight least significant bits of address bus. The address/data bus is time multiplexed. This means for few microseconds, the 8 least significant bits of address are generated, while for next few seconds the same pin generates the data. This is called Time multiplexing. But there are situations where there is a need to transmit both data and address simultaneously. For this purpose a signal called ALE (address latch enable) is used. ALE signal holds the obtained address in its latch for a long time until the data is obtained and so when the microprocessor sends the data next time the address is also available at the output latch. This technique is called Address/Data demultiplexing.

Thus the architecture of 8085 and its various units are explained in detail. Next Article

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How To Interface The 8085 Microprocessor?

Written by: shankar Edited by: KennethSleight Published Oct 28, 2009 Related Guides: Intel | Microprocessors

A microprocessor has to be interfaced with various peripherals to perform various functions. Let's discuss about the Interfacing techniques in detail.

Introduction
We know that a microprocessor is the CPU of a computer. A microprocessor can perform some operation on a data and give the output. But to perform the operation we need an input to enter the data and an output to display the results of the operation. So we are using a keyboard and monitor as Input and output along with the processor. Microprocessors engineering involves a lot of other concepts and we also interface memory elements like ROM, EPROM to access the memory.

Interfacing Types
There are two types of interfacing in context of the 8085 processor. Memory Interfacing. I/O Interfacing. Memory Interfacing: While executing an instruction, there is a necessity for the microprocessor to access memory frequently for reading various instruction codes and data stored in the memory. The interfacing circuit aids in accessing the memory. Memory requires some signals to read from and write to registers. Similarly the microprocessor transmits some signals for reading or writing a data.
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But what is the purpose of interfacing circuit here? The interfacing process involves matching the memory requirements with the microprocessor signals. The interfacing circuit therefore should be designed in such a way that it matches the memory signal requirements with the signals of the microprocessor. For example for carrying

out a READ process, the microprocessor should initiate a read signal which the memory requires to read a data. In simple words, the primary function of a memory interfacing circuit is to aid the microprocessor in reading and writing a data to the given register of a memory chip. I/O Interfacing: We know that keyboard and Displays are used as communication channel with outside world. So it is necessary that we interface keyboard and displays with the microprocessor. This is called I/O interfacing. In this type of interfacing we use latches and buffers for interfacing the keyboards and displays with the microprocessor. But the main disadvantage with this interfacing is that the microprocessor can perform only one function. It functions as an input device if it is connected to buffer and as an output device if it is connected to latch. Thus the capability is very limited in this type of interfacing.

Programmable Peripheral Devices

Programmable peripheral devices were introduced by Intel to increase the overall performance of the system. These devices along with I/O functions, they perform various other functions such as time delays, counters and interrupt handling. These devices are nothing but a combination of many devices on a single chip. A programmable device can be set up to perform specific function by writing a code in the internal register. As this code controls the function of the device its called control word and internal register in which it is stored is called Control Register. INTEL developed some peripheral devices for processors like 8085/8086/8088. The peripheral devices includes 8255 Parallel Communication Interface (PPI) 8251 Serial communication Interface (USART- Universal Synchronous/Asynchronous Receiver/Transmitter) 8257 DMA Controller 8279 Keyboard/Display Controller 8259 Programmable Interrupt controller 8254 Programmable Timer

Types of Communication Interface

There are two ways in which a microprocessor can connect with outside world or other memory systems. Serial Communication Interface Parallel Communication interface Serial Communication Interface: In serial communication interface, the interface gets a single byte of data from the microprocessor and sends it bit by bit to other system serially (or) the interface receives data bit by bit serially from the external systems and converts the data into a single byte and transfers it to the microprocessor. Parallel Communication Interface: This interface gets a byte of data from microprocessor and sends it bit by bit to the other systems in simultaneous (or) parallel fashion. The interface also receives data bit by bit simultaneously from the external system and converts the data into a single byte and transfers it to microprocessor. Consider that we have a microprocessor interfaced to both I/O device and also a memory chip. Now how to select between the two devices according to the requirement? For this purpose an address decoding circuit is used. An address decoding circuit aids in selecting the required I/O device or a memory chip. Let us discuss the concept of Memory interfacing and I/O interfacing in the next article.

8085: Addressing Modes

Written by: shankar Edited by: KennethSleight Published Oct 11, 2009 Related Guides: Microprocessors

Learn about the addressing modes of 8085 microprocessor, what are the different types of addressing modes available for 8085 microprocessor and the significance of the addressing modes explained with examples.

Introduction
We have been doing a series of microprocessor education articles and till date we have discussed about the evolution of microprocessors, architecture, pin diagram and signal diagrams of 8085 microprocessor. We also discussed about how the signals helps in processing data, storing them and executing them. But we cannot carry out a process with a microprocessor with only signals and instructions. We need a data to operate. Every instruction has to operate on a data.

There is a method in which the instructions address the data to be operated. The method of specifying the data to be operated by the instruction is known as addressing. Now we know what is addressing. But what are addressing modes? The way by which the microprocessor identifies the operands for a particular instruction is known as Addressing mode.

Types of Addressing Modes

The process of identifying the operands for a particular instruction can be carried out in several ways. The various types of addressing modes are as shown below.
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Immediate addressing mode Direct addressing mode Register addressing mode Register indirect addressing mode Implicit addressing mode

Immediate Addressing Mode: In this type of addressing mode the operand is specified within the instruction itself. Let us discuss with an example. Consider this instruction: ADI 34H This instruction adds the immediate data, 34H to the accumulator. 34H is the data here. H represents Hexadecimal value and the immediate value is added to the accumulator. In this case 34H is added to the accumulator. Suppose if accumulator has a value 8H and when this instruction is executed, 34H is added to the 8H and the result is stored in accumulator. In the above instruction the operand is specified within instruction itself. Direct Addressing Mode: In this mode of addressing, the address of the data (operand) is specified within the instruction.

There is a subtle difference between the direct addressing modes and immediate addressing modes. In immediate addressing mode the data itself is specified within instruction, but in direct addressing mode the address of the data is specified in the instruction. Example: OUT 10H LDA 4100H STA 2000H Consider the instruction STA 2000H When this instruction is executed, the contents of the accumulator are stored in the memory location specified. In the above example the contents of accumulator are stored in memory location 2000H.

Register Addressing Mode: In this type of addressing mode the instruction specifies the name of the register in which the data is available and Opcode specifies the name (or) address of the register on which the operation would be performed. Example: MOV A, B Here the Opcode is MOV. If the above instruction is executed, the contents of Register B are moved to the Register A, which is nothing but the accumulator.

Other examples:

ANA B On executing the above instruction the contents of Register B or logically ANDed with contents of register A (accumulator). SUB H If we execute the above instruction the contents of Register H will be subtracted from the contents of the accumulator. Register Indirect Addressing Mode: This is indirect way of addressing. In this mode the instruction specifies the name of the register in which the address of the data is available. Example: MOV A, M SUB M DCR M Consider MOV A, M. This instruction will move the contents of memory location, whose address is in H-L register pair to the accumulator. M represents the address present in the H-L register pair. So when MOV A, M is executed, the contents of the address specified in H-L register pair are moved to accumulator.

Implicit Addressing Mode: There are certain instructions in 8085 which does not require the address of the operand to perform the operation. They operate only upon the contents of accumulator. Example: CMA RAL RAR

CMA complements the contents of accumulator. If RAL is executed the contents of accumulator is rotated left one bit through carry. If RAR is executed the contents of accumulator is rotated right one bit through carry.

Thus the various addressing modes of 8085 microprocessor are discussed in detail. Image Courtesy: Manoharan, P.S. (2009) Microprocessors and its Applications. Chennai: Charulatha Publications

DATA TRANSFER INSTRUCTIONS

Opcode Operand Explanation of Instruction Description This instruction copies the contents of the source register into the destination register; the contents of the source register are not altered. If one of the operands is a memory location, its location is specified by the contents of the HL registers. Example: MOV B, C or MOV B, M Rd, data MVI M, data The 8-bit data is stored in the destination register or Move immediate 8memory. If the operand is a memory location, its bit location is specified by the contents of the HL

Rd, Rs MOV M, Rs Rd, M Copy from source(Rs) to destination(Rd)

registers. Example: MVI B, 57H or MVI M, 57H 16-bit address The contents of a memory location, specified by a 16bit address in the operand, are copied to the accumulator. The contents of the source are not altered. Example: LDA 2034H The contents of the designated register pair point to a memory location. This instruction copies the contents of that memory location into the accumulator. The contents of either the register pair or the memory location are not altered. Example: LDAX B LXI Reg. pair, 16-bit data Load register pair immediate The instruction loads 16-bit data in the register pair designated in the operand. Example: LXI H, 2034H or LXI H, XYZ The instruction copies the contents of the memory location pointed out by the 16-bit address into register L and copies the contents of the next memory location into register H. The contents of source memory locations are not altered. Example: LHLD 2040H The contents of the accumulator are copied into the memory location specified by the operand. This is a 3byte instruction, the second byte specifies the loworder address and the third byte specifies the highorder address. Example: STA 4350H The contents of the accumulator are copied into the memory location specified by the contents of the Store accumulator operand (register pair). The contents of the indirect accumulator are not altered. Example: STAX B The contents of register L are stored into the memory location specified by the 16-bit address in the operand and the contents of H register are stored into the next memory location by incrementing the operand. The contents of registers HL are not altered. This is a 3byte instruction, the second byte specifies the loworder address and the third byte specifies the highorder address.

LDA

Load accumulator

LDAX

B/D Reg. pair

Load accumulator indirect

LHLD

16-bit address

Load H and L registers direct

STA

16-bit address

16-bit address

STAX

Reg. pair

SHLD

16-bit address

Store H and L registers direct

Example: SHLD 2470H The contents of register H are exchanged with the contents of register D, and the contents of register L Exchange H and L are exchanged with the contents of register E. with D and E Example: XCHG The instruction loads the contents of the H and L registers into the stack pointer register, the contents of the H register provide the high-order address and the contents of the Copy H and L registers to the stack L register provide the low-order address. The contents of the H pointer and L registers are not altered. Example: SPHL The contents of the L register are exchanged with the stack location pointed out by the contents of the stack pointer register. The contents of the H register are Exchange H and L exchanged with the next stack location (SP+1); with top of stack however, the contents of the stack pointer register are not altered. Example: XTHL The contents of the register pair designated in the operand are copied onto the stack in the following sequence. The stack pointer register is decremented and the contents of the highorder register (B, D, H, A) are copied into that location. The stack pointer register is decremented again and the contents of the low-order register (C, E, L, flags) are copied to that location. Example: PUSH B or PUSH A The contents of the memory location pointed out by the stack pointer register are copied to the low-order register (C, E, L, status flags) of the operand. The stack pointer is incremented by 1 and the contents of that memory location are copied to the high-order register (B, D, H, A) of the operand. The stack pointer register is again incremented by 1. Example: POP H or POP A OUT 8-bit port address Output data from accumulator to a port with 8-bit address The contents of the accumulator are copied into the I/O port specified by the operand. Example: OUT F8H

XCHG

none

SPHL

none

XTHL

none

PUSH

Reg. pair

Push register pair onto stack

POP

Reg. pair

Pop off stack to register pair

IN

The contents of the input port designated in the Input data to 8-bit port accumulator from a operand are read and loaded into the accumulator. address port with 8-bit

address

Example: IN 8CH

Opcode

Operand

Explanation of Instruction

Description The contents of the operand (register or memory) are added to the contents of the accumulator and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the addition. Example: ADD B or ADD M

R ADD M

Add register or memory, to accumulator

R ADC M

The contents of the operand (register or memory) and M the Carry flag are added to the contents of the accumulator and the result is stored in the accumulator. If Add register to the operand is a memory location, its location is specified accumulator with by the contents of the HL registers. All flags are modified carry to reflect the result of the addition. Example: ADC B or ADC M

ADI

The 8-bit data (operand) is added to the contents of the accumulator and the result is stored in the accumulator. Add immediate to All flags are modified to reflect the result of the addition. 8-bit data accumulator Example: ADI 45H The 8-bit data (operand) and the Carry flag are added to the contents of the accumulator and the result is stored in Add immediate to the accumulator. All flags are modified to reflect the 8-bit data accumulator with result of the addition. carry Example: ACI 45H The instruction loads 16-bit data in the register pair Reg. pair, Load register pair designated in the operand. 16-bit data immediate Example: LXI H, 2034H or LXI H, XYZ The 16-bit contents of the specified register pair are added to the contents of the HL register and the sum is Add register pair stored in the HL register. The contents of the source register pair are not altered. If the result is larger than 16 to H and L bits, the CY flag is set. No other flags are affected. registers Example: DAD H

ACI

LXI

DAD

Reg. pair

R SUB M

The contents of the operand (register or memory ) are subtracted from the contents of the accumulator, and the result is stored in the accumulator. If the operand is a Subtract register memory location, its location is specified by the contents or memory from of the HL registers. All flags are modified to reflect the accumulator result of the subtraction. Example: SUB B or SUB M The contents of the operand (register or memory ) and M the Borrow flag are subtracted from the contents of the accumulator and the result is placed in the accumulator. If Subtract source the operand is a memory location, its location is specified and borrow from by the contents of the HL registers. All flags are modified accumulator to reflect the result of the subtraction. Example: SBB B or SBB M The 8-bit data (operand) is subtracted from the contents of the accumulator and the result is stored in the Subtract accumulator. All flags are modified to reflect the result of immediate from the subtraction. accumulator Example: SUI 45H

R SBB M

SUI

8-bit data

SBI

The contents of register H are exchanged with the Subtract contents of register D, and the contents of register L are immediate from exchanged with the contents of register E. 8-bit data accumulator with borrow Example: XCHG R The contents of the designated register or memory) are incremented by 1 and the result is stored in the same Increment register place. If the operand is a memory location, its location is or memory by 1 specified by the contents of the HL registers. Example: INR B or INR M The contents of the designated register pair are incremented by 1 and the result is stored in the same Increment register place. pair by 1 Example: INX H R Decrement register or memory by 1 The contents of the designated register or memory are M decremented by 1 and the result is stored in the same place. If the operand is a memory location, its location is specified by the contents of the HL registers. Example: DCR B or DCR M

INR M

INX

DCR M

DCX

The contents of the designated register pair are decremented by 1 and the result is stored in the same Decrement register pair by 1 place.

Example: DCX H The contents of the accumulator are changed from a binary value to two 4-bit binary coded decimal (BCD) digits. This is the only instruction that uses the auxiliary flag to perform the binary to BCD conversion, and the conversion procedure is described below. S, Z, AC, P, CY flags are altered to reflect the results of the operation. DAA none Decimal adjust accumulator If the value of the low-order 4-bits in the accumulator is greater than 9 or if AC flag is set, the instruction adds 6 to the low-order four bits. If the value of the high-order 4-bits in the accumulator is greater than 9 or if the Carry flag is set, the instruction adds 6 to the high-order four bits. Example: DAA

BRANCHING INSTRUCTIONS
Opcode Operand Explanation of Instruction Description The program sequence is transferred to the memory location specified by the 16-bit address given in the operand. Example: JMP 2034H or JMP XYZ Opcode JC JNC JP JM JZ JNZ JPE Description Flag Status The program sequence is transferred to the memory location specified by the 16-bit address given in the operand based on the specified flag of the PSW as described below. Example: JZ 2034H or JZ XYZ

JMP

16-bit address

Jump unconditionally

Jump on Carry CY = 1 Jump on no Carry Jump on positive Jump on zero CY = 0 S=0 16-bit address Jump conditionally

Jump on minus S = 1 Z=1 Jump on no zero Z = 0 Jump on parity P=1 even

JPO Opcode CC CNC CP CM CZ CNZ CPE CPO

Jump on parity P=0 odd Description Call on Carry Call on no Carry Call on minus Call on zero Call on parity even Call on parity odd Flag Status CY = 1 CY = 0 16-bit address The program sequence is transferred to the memory location specified by the 16-bit address given in the operand. Before the transfer, the address of the next Unconditional instruction after CALL (the subroutine call contents of the program counter) is pushed onto the stack. Example: CALL 2034H or CALL XYZ

Call on positive S = 0 S=1 Z=1

Call on no zero Z = 0 P=1 P=0

RET

none

The program sequence is transferred from the subroutine to the calling program. The two bytes Return from from the top of the stack are copied subroutine into the program counter,and unconditionally program execution begins at the new address. Example: RET

Opcode RC RNC RP RM RZ RNZ RPE RPO

Description

Flag Status The program sequence is transferred from the subroutine to the calling program based on the specified flag of the PSW as described below. The two bytes from the top of the stack are copied into the program counter, and program execution begins at the new address. Example: RZ

Return on Carry CY = 1 Return on no Carry Return on positive Return on zero Return on no zero CY = 0 S=0 none Return from subroutine conditionally

Return on minus S = 1 Z=1 Z=0

Return on parity P=1 even Return on parity P=0 odd

PCHL

none

The contents of registers H and L Load program are copied into the program counter with HL counter. The contents of H are contents placed as the high-order byte and

the contents of L as the low-order byte. Example: PCHL The RST instruction is equivalent to a 1-byte call instruction to one of eight memory locations depending upon the number. The instructions are generally used in conjunction with interrupts and inserted using external hardware. However these can be used as software instructions in a program to transfer program execution to one of the eight locations. The addresses are: Instruction RST 0 RST1 RST 2 RST 3 RST 0-7 Restart RST 4 RST 5 RST 6 RST 7 Restart Address 0000H 0008H 0010H 0018H 0020H 0028H 0030H 0038H

The 8085 has four additional interrupts and these interrupts generate RST instructions internally and thus do not require any external hardware. These instructions and their Restart addresses are: Interrupt TRAP Restart Address 0024H

RST 5.5 002CH RST 6.5 0034H RST 7.5 003CH

LOGICAL INSTRUCTIONS
Opcode Operand Explanation of Instruction Description The contents of the operand (register or memory) are M compared with the contents of the accumulator. Both contents are preserved . The result of the comparison is shown by setting the flags of the PSW as follows: set set

R CMP M

Compare register or memory with if (A) < (reg/mem): carry flag is accumulator if (A) = (reg/mem): zero flag is if (A) > (reg/mem): carry and zero flags are reset Example: CMP B or CMP M

CPI

8-bit data

Compare immediate with if (A) < data: carry flag accumulator if (A) = data: zero flag if (A) > data: carry and zero flags are reset Example: CPI 89H

The second byte (8-bit data) is compared with the contents of the accumulator. The values being compared remain unchanged. The result of the comparison is shown by setting the flags of the PSW as follows: is is set set

R ANA M

Logical AND register or memory with accumulator

The contents of the accumulator are logically ANDed with M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY is reset. AC is set. Example: ANA B or ANA M

ANI

8-bit data

The contents of the accumulator are logically ANDed with the Logical AND 8-bit data (operand) and the result is placed in the immediate with accumulator. S, Z, P are modified to reflect the result of the operation. CY is reset. AC is set. accumulator Example: ANI 86H The contents of the accumulator are Exclusive ORed with M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: XRA B or XRA M

R XRA M

Exclusive OR register or memory with accumulator

XRI

8-bit

Exclusive OR

The contents of the accumulator are Exclusive ORed with

data

immediate with the 8-bit data (operand) and the result is placed in the accumulator accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: XRI 86H The contents of the accumulator are logically ORed with M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY and AC are reset. Example: ORA B or ORA M The contents of the accumulator are logically ORed with the 8-bit data (operand) and the result is placed in the Logical OR accumulator. S, Z, P are modified to reflect the result of the immediate with operation. CY and AC are reset. accumulator Example: ORI 86H Each binary bit of the accumulator is rotated left by one position. Bit D7 is placed in the position of D0 as well as in Rotate the Carry flag. CY is modified according to bit D7. S, Z, P, accumulator left AC are not affected. Example: RLC Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the position of D7 as well as in the Carry flag. CY is modified according to bit D0. S, Z, P, Rotate accumulator right AC are not affected. Example: RRC Each binary bit of the accumulator is rotated left by one position through the Carry flag. Bit D7 is placed in the Carry flag, and the Carry flag is placed in the least Rotate accumulator left significant position D0. CY is modified according to bit through carry D7. S, Z, P, AC are not affected. Example: RAL Each binary bit of the accumulator is rotated right by one position through the Carry flag. Bit D0 is placed in the Rotate Carry flag, and the Carry flag is placed in the most accumulator right significant position D7. CY is modified according to bit through carry D0. S, Z, P, AC are not affected. Example: RAR

R ORA M

Logical OR register or memory with accumulator

ORI

8-bit data

RLC

none

RRC

none

RAL

none

RAR

none

CMA

none

Complement accumulator

The contents of the accumulator are complemented. No flags are affected.

Example: CMA CMC none Complement carry The Carry flag is complemented. No other flags are affected. Example: CMC Set Carry STC none Set Carry Example: STC

CONTROL INSTRUCTIONS
Opcode Operand Explanation of Instruction No operation Halt and enter wait state Disable interrupts Description No operation is performed. The instruction is fetched and decoded. However no operation is executed. Example: NOP HLT none The CPU finishes executing the current instruction and halts any further execution. An interrupt or reset is necessary to exit from the halt state. Example: HLT The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled. No flags are affected. Example: DI The interrupt enable flip-flop is set and all interrupts are enabled. No flags are affected. After a system reset or the acknowledgement of an interrupt, the interrupt enable flipflop is reset, thus disabling the interrupts. This instruction is necessary to reenable the interrupts (except TRAP). Example: EI Read interrupt mas This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and read serial data input bit. The instruction loads eight bits in the accumulator with the following interpretations. Example: RIM

NOP

none

DI

none

EI

none

Enable interrupts

RIM

none

This is a multipurpose instruction and used to implement the 8085 interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interprets the accumulator contents as follows. Example: SIM

SIM

none

Set interrupt mask

Overview or Features of 8086

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It is a 16-bit Microprocessor( p).Its ALU, internal registers works with 16bit binary word. 8086 has a 20 bit address bus can access up to 220= 1 MB memory locations.

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8086 has a 16bit data bus. It can read or write data to a memory/port either 16bits or 8 bit at a time. It can support up to 64K I/O ports. It provides 14, 16 -bit registers. Frequency range of 8086 is 6-10 MHz It has multiplexed address and data bus AD0- AD15 and A16 A19. It requires single phase clock with 33% duty cycle to provide internal timing. It can prefetch upto 6 instruction bytes from memory and queues them in order to speed up instruction execution. It requires +5V power supply. A 40 pin dual in line package. 8086 is designed to operate in two modes, Minimum mode and Maximum mode. o The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This is a single microprocessor configuration. o The maximum mode is selected by applying logic 0 to the MN / MX# input pin. This is a multi micro processors configuration.

Pin Diagram of 8086 and Pin description of 8086

Figure shows the Pin diagram of 8086. The description follows it.

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The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged in a 40 pin CERDIP or plastic package. The 8086 operates in single processor or multiprocessor configuration to achieve high performance. The pins serve a particular function in minimum mode (single processor mode ) and other function in maximum mode configuration (multiprocessor mode ).

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The 8086 signals can be categorised in three groups. o The first are the signal having common functions in minimum as well as maximum mode. o The second are the signals which have special functions for minimum mode o The third are the signals having special functions for maximum mode. The following signal descriptions are common for both modes. AD15-AD0 : These are the time multiplexed memory I/O address and data lines. o Address remains on the lines during T1 state, while the data is available on the data bus during T2, T3, Tw and T4. These lines are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles. A19/S6,A18/S5,A17/S4,A16/S3 : These are the time multiplexed address and status lines. o During T1 these are the most significant address lines for memory operations. o During I/O operations, these lines are low. o During memory or I/O operations, status information is available on those lines for T2,T3,Tw and T4. o The status of the interrupt enable flag bit is updated at the beginning of each clock cycle. o The S4 and S3 combinely indicate which segment register is presently being used for memory accesses as in below fig. o These lines float to tri-state off during the local bus hold acknowledge. The status line S6 is always low. o The address bit are separated from the status bit using latches controlled by the ALE signal. S4 S3 Indication

0 0 1 1 0 0 1
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0 1 0 1 0 1 0

Alternate Data Stack Code or None Data Whole word Upper byte from or to even address Lower byte from or to even address

BHE/S7 : The bus high enable is used to indicate the transfer of data over the higher order ( D15-D8 ) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on

higher byte of data bus. The status information is available during T2, T3 and T4. The signal is active low and tristated during hold. It is low during T1 for the first pulse of the interrupt acknowledge cycle.
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RD Read : This signal on low indicates the peripheral that the processor is performing memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any read cycle. The signal remains tristated during the hold acknowledge. READY : This is the acknowledgement from the slow device or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. the signal is active high. INTR-Interrupt Request : This is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle. This can be internally masked by resulting the interrupt enable flag. This signal is active high and internally synchronized. TEST : This input is examined by a WAIT instruction. If the TEST pin goes low, execution will continue, else the processor remains in an idle state. The input is synchronized internally during each clock cycle on leading edge of clock. CLK- Clock Input : The clock input provides the basic timing for processor operation and bus control activity. Its an asymmetric square wave with 33% duty cycle.

Architechture of 8086 or Functional Block diagram of 8086

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8086 has two blocks Bus Interfacing Unit(BIU) and Execution Unit(EU). The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction system byte queue. Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register,Flag register.

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Level 1 cache

The Level 1 cache, or primary cache, is on the CPU and is used for temporary storage of instructions and data organised in blocks of 32 bytes. Primary cache is the fastest form of storage. Because its built in to the chip with a zero wait-state (delay) interface to the processors execution unit, it is limited in size. Level 1 cache is implemented using Static RAM (SRAM) and until recently was traditionally 16KB in size. SRAM uses two transistors per bit and can hold data without external assistance, for as long as power is supplied to the circuit. The second transistor controls the output of the first: a circuit known as a flip-flop so-called because it has two stable states which it can flip between. This is contrasted to dynamic RAM (DRAM), which must be refreshed many times per second in order to hold its data contents. SRAM is manufactured in a way rather similar to how processors are: highly integrated transistor patterns photoetched into silicon. Each SRAM bit is comprised of between four and six transistors, which is why SRAM takes up much more space compared to DRAM, which uses only one (plus a capacitor). This, plus the fact that SRAM is also several times the cost of DRAM, explains why it is not used more extensively in PC systems. Intels P55 MMX processor, launched at the start of 1997, was noteworthy for the increase in size of its Level 1 cache to 32KB. The AMD K6 and Cyrix M2 chips launched later that year upped the ante further by providing Level 1 caches of 64KB. 64Kb has remained the standard L1 cache size, though various multiple-core processors may utilise it differently.

For all L1 cache designs the control logic of the primary cache keeps the most frequently used data and code in the cache and updates external memory only when the CPU hands over control to other bus masters, or during direct memory access by peripherals such as optical drives and sound cards. Some chipsets, such as the Pentium based Triton FX (and later), support a write back cache rather than a write through cache. Write through happens when a processor writes data simultaneously into cache and into main memory (to assure coherency). Write back occurs when the processor writes to the cache and then proceeds to the next instruction. The cache holds the write-back data and writes it into main memory when that data line in cache is to be replaced. Write back offers about 10% higher performance than write-through, but cache that has this function is more costly. A third type of write mode, write through with buffer, gives similar performance to write back.

L2 CACHE

Most PCs are offered with a Level 2 cache to bridge the processor/memory performance gap. Level 2 cache also referred to as secondary cache) uses the same control logic as Level 1 cache and is also implemented in SRAM. Level 2 cache typically comes in two sizes, 256KB or 512KB, and can be found, or soldered onto themotherboard, in a Card Edge Low Profile (CELP) socket or, more recently, on a COAST (cache on a stick) module. The latter resembles a SIMM but is a little shorter and plugs into a COAST socket, which is normally located close to the processor and resembles a PCI expansion slot. The Pentium Pro deviated from this arrangement, siting the Level 2 cache on the processor chip itself. The aim of the Level 2 cache is to supply stored information to the processor without any delay (wait-state). For this purpose, the bus interface of the processor has a special transfer protocol called burst mode. A burst cycle consists of four data transfers where only the address of the first 64 are output on the address bus. The most common Level 2 cache is synchronous pipeline burst. To have a synchronous cache a chipset, such as Triton, is required to support it. It can provide a 3-5% increase in PC performance because it is timed to a clock cycle. This is achieved by use of specialised SRAM technology which has been developed to allow zero wait-state access for consecutive burst read cycles. Pipelined Burst Static RAM (PB SRAM) has an access time in the range 4.5 to 8 nanoseconds (ns) and allows a transfer timing of 3-1-1-1 for bus speeds up to 133MHz. These numbers refer to the number of clock cycles for each access of a burst mode memory read. For example, 3-1-1-1 refers to three clock cycles for the first word and one cycle for each subsequent word. For bus speeds up to 66MHz Synchronous Burst Static RAM (Sync SRAM) offers even faster performance, being capable of 2-1-1-1 burst cycles. However, with bus speeds above 66MHz its performance drops to 3-2-2-2, significantly slower than PB SRAM. There is also asynchronous cache, which is cheaper and slower because it isnt timed to a clock cycle. With asynchronous SRAM, available in speeds between 12 and 20ns, all burst read cycles have a timing of 3-2-2-2 on a 50 to 66MHz CPU bus, which means that there are two wait-states for the lead-off cycle and one wait-state for the following three transfers of the burst cycle.

A PCs third and principal level of system memory is referred to as main memory, or Random Access Memory (RAM). It is an impermanent source of data, but is the main memory area accessed by the hard disk. It acts, so to speak, as a staging post between the hard disk and the processor. The more data it is possible to have available in the RAM the faster the PC will run. Main memory is attached to the processor via its address and data buses. Each bus consists of a number of electrical circuits or bits. The width of the address bus dictates how many different memory locations can be accessed, and the width of the data bus how much information is stored at each location. Every time a bit is added to the width of the address bus, the address range doubles. In 1985, Intels 386 processor had a 32-bit address bus, enabling it to access up to 4GB of memory. The Pentium processor introduced in 1993 increased the data bus width to 64-bits, enabling it to access 8 bytes of data at a time. Each transaction between the CPU and memory is called a bus cycle. The number of data bits a CPU is able to transfer during a single bus cycle affects a computers performance and dictates what type of memory the computer requires. By the late 1990s, most desktop computers were using 168-pin DIMMs, which supported 64bit data paths. Main memory is built up using DRAM chips, short for Dynamic RAM. DRAM has been developed over the years on two main fronts: to be more compact, and to be faster to access. These developments are explored in the following pages of memory section see the menu below.

DRAM chips are large, rectangular arrays of memory cells with support logic that is used for reading and writing data in the arrays, and refresh circuitry to maintain the integrity of stored data. Memory arrays are arranged in rows and columns of memory cells called wordlines and bitlines, respectively. Each memory cell has a unique location or address defined by the intersection of a row and a column. DRAM is manufactured using a similar process to how processors are: a silicon substrate is etched with the patterns that make the transistors and capacitors (and support structures) that comprise each bit. It costs much less than a processor because it is a series of simple, repeated structures, so there isnt the complexity of making a single chip with several million individually-located transistors and DRAM is cheaper than SRAM and uses half as many transistors. Over the years, several different structures have been used to create the memory cells on a chip, and in todays technologies the support circuitry generally includes: sense amplifiers to amplify the signal or charge detected on a memory cell address logic to select rows and columns Row Address Select (RAS) and Column Address Select (CAS) logic to latch and resolve the row and column addresses and to initiate and terminate read and write operations read and write circuitry to store information in the memorys cells or read that which is stored there internal counters or registers to keep track of the refresh sequence, or to initiate refresh cycles as needed Output Enable logic to prevent data from appearing at the outputs unless specifically desired.

     

A transistor is effectively a switch which can control the flow of current either on, or off. In DRAM, each transistor holds a single bit: if the transistor is open, and the current can flow, thats a 1; if its closed, its a 0. A capacitor is used to hold the charge, but it soon escapes, losing the data. To overcome this problem, other circuitry refreshes the memory, reading the value before it disappears completely, and writing back a pristine version. This refreshing action is why the memory is called dynamic. The refresh speed is expressed in nanoseconds (ns) and it is this figure that represents the speed of the RAM. Most Pentium-based PCs use 60 or 70ns RAM. The process of refreshing actually interrupts/slows down the accessing of the data but clever cache design minimises this. However, as processor speeds passed the 200MHz mark, no amount of cacheing could compensate for the inherent slowness of DRAM and other, faster memory technologies have largely superseded it.

DRAM Timing and Signals

The most difficult aspect of working with DRAM devices is resolving the timing requirements. DRAMs are generally asynchronous, responding to input signals whenever they occur. As long as the signals are applied in the proper sequence, with signal durations and delays between signals that meet the specified limits, the DRAM will work properly. These are few in number, comprising: Row Address Select: The /RAS circuitry is used to latch the row address and to initiate the memory cycle. It is required at the beginning of every operation. /RAS is active low; that is, to enable /RAS, a transition from a high voltage to a low voltage level is required. The voltage must remain low until /RAS is no longer needed. During a complete memory cycle, there is a minimum amount of time that /RAS must be active, and a minimum amount of time that /RAS must be inactive, called the /RAS precharge time. /RAS may also be used to trigger a refresh cycle (/RAS Only Refresh, or ROR).

Column Address Select: /CAS is used to latch the column address and to initiate the read or write operation. /CAS may also be used to trigger a /CAS before /RAS refresh cycle. This refresh cycle requires /CAS to be active prior to /RAS and to remain active for a specified time. It is active low. The memory specification lists the minimum amount of time /CAS must remain active to initiate a read or write operation. For most memory operations, there is also a minimum amount of time that /CAS must be inactive, called the /CAS precharge time. (An ROR cycle does not require /CAS to be active.) Address: The addresses are used to select a memory location on the chip. The address pins on a memory device are used for both row and column address selection (multiplexing). The number of addresses depends on the memorys size and organisation. The voltage level present at each address at the time that /RAS or /CAS goes active determines the row or column address, respectively, that is selected. To ensure that the row or column address selected is the one that was intended, set up and hold times with respect to the /RAS and /CAS transitions to a low level are specified in the DRAM timing specification.

Write Enable: The /WE signal is used to choose a read operation or a write operation. A low voltage level signifies that a write operation is desired; a high voltage level is used to choose a read operation. The operation to be performed is usually determined by the voltage level on /WE when /CAS goes low (Delayed Write is an exception). To ensure that the correct operation is selected, set up and hold times with respect to /CAS are specified in the DRAM timing specification.

Output Enable: During a read operation, this control signal is used to prevent data from appearing at the output until needed. When /OE is low, data appears at the data outputs as soon as it is available. /OE is ignored during a write operation. In many applications, the /OE pin is grounded and is not used to control the DRAM timing.

Data In or Out: The DQ pins (also called Input/Output pins or I/Os) on the memory device are used for input and output. During a write operation, a voltage (high=1, low=0) is applied to the DQ. This voltage is translated into the appropriate signal and stored in the selected memory cell. During a read operation, data read from the selected memory cell appears at the DQ once access is complete and the output is enabled (/OE low). At most other times, the DQs are in a high impedance state; they do not source or sink any current, and do not present a signal to the system. This also prevents DQ contention when two or more devices share the data bus.

Flash memory is a solid-state, non-volatile, rewritable memory that works like RAM and a hard-disk drive combined. It resembles conventional memory, coming in the form of discrete chips, modules, or memory cards. Just like with DRAM and SRAM, bits of electronic data are stored in memory cells, and just like with a hard disk drive, flash memory is non-volatile, retaining its data even when the power is turned off. Notwithstanding its apparent advantages over both RAM (its non-volatility) and hard disk (the absence of moving parts), there are a number of reasons why flash memory is not a viable replacement for either. Because of its

design, flash memory must be erased in blocks of data rather than single bytes like RAM. This, together with its significantly higher cost and the fact that memory cells in a flash chip have a limited lifespan of around 100,000 write cycles, make it an inappropriate alternative to RAM for use as a PCs main memory. Whilst electronic flash drives are smaller, faster, consume less energy and are capable of withstanding shocks up to 2000 Gs equivalent to a 10 foot drop onto concrete without losing data, their limited capacity (around 100MB) make them an inappropriate alternative to a PCs hard disk drive. Even if capacity were not a problem, as with RAM, flash memory cannot compete with hard disks in price. Since its inception in the mid-1980s, flash memory has evolved into a versatile and practical storage solution. Several different implementation exist. NOR flash is a random access device appropriate for code storage applications. NAND flash optimised for mass storage applications is the most common form. Its high speed, durability, and low voltage requirements, have made it ideal for use in many applications such asdigital cameras, cell phones, printers, handheld computers, pagers, and audio recorders. Samsung Electronics is the leading flash memory producer, and indeed, the leading producer of memory products in general. Its SmartMedia flash memory cards first appeared in 1996 and along with CompactFlash have gone on to become one of predominant flash memory formats. In late 1999 the company announced the worlds first 1GB flash memory prototype, based on 0.15 micron process technology. The following year its largest capacity card to date at 128MB came to market, with a 512MB chip slated for mass production in 2001. However, at the very time capacities were growing apace, flash memory found itself facing a challenge from a radical new memory chip technology, in the shape of Magnetic RAM.

Micro-controllers may not implement an external address or data bus as they integrate RAM and nonvolatile memory on the same chip as the CPU. Using fewer pins, the chip can be placed in a much smaller, cheaper package. Integrating the memory and other peripherals on a single chip and testing them as a unit increases the cost of that chip, but often results in decreased net cost of the embedded system as a whole. Even if the cost of a CPU that has integrated peripherals is slightly more than the cost of a CPU and external peripherals, having fewer chips typically allows a smaller and cheaper circuit board, and reduces the labor required to assemble and test the circuit board. A micro-controller is a single integrated circuit, commonly with the following features:           central processing unit - ranging from small and simple 4-bit processors to complex 32- or 64-bit processors volatile memory (RAM) for data storage ROM, EPROM, EEPROM or Flash memory for program and operating parameter storage discrete input and output bits, allowing control or detection of the logic state of an individual package pin serial input/output such as serial ports (UARTs) other serial communications interfaces like IC, Serial Peripheral Interface and Controller Area Network for system interconnect peripherals such as timers, event counters, PWM generators, and watchdog clock generator - often an oscillator for a quartz timing crystal, resonator or RC circuit many include analog-to-digital converters, some include digital-to-analog converters in-circuit programming and debugging support