Mach1 2

MACH 1 and 2 CPLD Families
High-Performance EE CMOS Programmable Logic
FEATURES
x x x x x x
x x x x x x
High-performance electrically-erasable CMOS PLD families 32 to 128 macrocells 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages SpeedLocking guaranteed xed timing up to 16 product terms Commercial 5/5.5/6/7.5/10/12/15-ns tPD and Industrial 7.5/10/12/14/18-ns tPD Congurable macrocells Programmable polarity Registered or combinatorial outputs Internal and I/O feedback paths D-type or T-type ip-ops Output Enables Choice of clocks for each ip-op Input registers for MACH 2 family JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns Safe for mixed supply voltage system designs Bus-Friendly inputs and I/Os reduce risk of unwanted oscillatory outputs Programmable power-down mode results in power savings of up to 75% Supported by Vantis DesignDirect software for rapid logic development Supports HDL design methodologies with results optimized for Vantis Flexibility to adapt to user requirements Software partnerships that ensure customer success Lattice/Vantis and third-party hardware programming support Lattice/VantisPRO (formerly known as MACHPRO ) software for in-system programmability support on PCs and Automated Test Equipment Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General
Publication# 14051 Amendment/0
Rev: K Issue Date: November 1998
Table 1. MACH 1 and 2 Family Device Features 1

Feature Macrocells Maximum user I/O pins tP D (ns) tS (ns) tCO (ns) fCNT (MHz) MACH111 (SP) 32 32 5.0 3.5 3.5 182 MACH131 (SP) 64 64 5.5 3.0 4 182 MACH211 (SP) 64 32 7.5 (6.0) 5.5 (5) 4.5 (4) 133 (166) MACH221 (SP) 96 48 7.5 5.5 5 133 MACH231 (SP) 128 64 6.0 (10) 5 (6.5) 4 (6.5) 166 (100)
Note: 1. Values in parentheses ( ) are for the SP version.
GENERAL DESCRIPTION
The MACH 1 & 2 families from Lattice/Vantis offer high-performance, low cost Complex Programmable Logic Devices (CPLDs), addressing the growing need for speed in networking, telecommunications and computing. MACH 1 & 2 devices are available in speeds as fast as 5.0-ns tPD and in densities ranging from 32 to 128 macrocells (Tables 1 and 2). The overall benets for users include guaranteed high performance for entry-to-mid-level logic needs at a low cost.
Table 2. MACH 1 and 2 Family Speed Grades1
Device MACH111 MACH111SP MACH131 MACH131SP MACH211 MACH211SP MACH221 MACH221SP MACH231 MACH231SP Notes: 1. C = Commercial, I = Industrial 2. -5 speed grade for MACH111 (SP) = 5.0 ns tPD 3. -5 speed grade for MACH131(SP) = 5.5 ns tPD C C -5 C (Note 2) C (Note 2) C (Note 3) C (Note 3) -6 -7 C, I C, I C, I C, I C C C C C -10 C, I C, I C, I C, I C, I C, I C, I C, I C C -12 C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I -14 I I I I I I I I I I -15 C C C C C C C C C C -18 I I I I I I I I I I
The MACH 1 & 2 families consist of ten devicesve base options, each with a counterpart that includes JTAG-compatible in-system programming (ISP). These devices offer ve different densityI/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), and Plastic Leaded Chip Carrier (PLCC) packages from 44 to 100 pins (Table 3). Each MACH 1 & 2 device is PCI compliant and includes other features such as SpeedLocking architecture for guaranteed xed timing, Bus-Friendly inputs and I/Os, and programmable power-down mode for extra power savings.
MACH 1 & 2 Families
Table 3. MACH 1 and 2 Family Package and I/O Options

Device MACH111 MACH111SP MACH131 MACH131SP MACH211 MACH211SP MACH221 MACH221SP MACH231 MACH231SP X X X X X X X X X 44-pin PLCC X X 44-pin TQFP X X X X X 68-pin PLCC 84-pin PLCC 100-pin TQFP 100-pin PQFP
Note: 1. The MACH110, MACH120, MACH130, MACH210, MACHLV210, MACH215, MACH220 and MACH230 are not listed above and not recommended for new designs. However, they are still supported by Lattice/Vantis. For technical or sales support, please call your local Lattice/Vantis sales ofce or visit our Web site at www.vantis.com for more information.
Lattice/Vantis offers software design support for MACH devices in both the MACHXL and DesignDirect development systems. The DesignDirect development system is the Lattice/Vantis implementation software that includes support for all Lattice/Vantis CPLD, FPGA, and SPLD devices. This system is supported under Windows 95, 98 and NT as well as Sun Solaris and HPUX. DesignDirect software is designed for use with design entry, simulation and verication software from leading-edge tool vendors such as Cadence, Exemplar Logic, Mentor Graphics, Model Technology, Synopsys, Synplicity, Viewlogic and others. It accepts EDIF 2 0 0 input netlists, generates JEDEC les for Lattice/Vantis PLDs and creates industry-standard EDIF, Verilog, VITAL compliant VHDL and SDF simulation netlists for design verication. DesignDirect software is also available in product congurations that include VHDL and Verilog synthesis from Exemplar Logic and VHDL, Verilog RTL and gate level timing simulation from Model Technology. Schematic capture and ABEL entry, as well as functional simulation, are also provided.
MACH 1 & 2 Families
FUNCTIONAL DESCRIPTION
Each MACH 1 and 2 device consists of multiple, optimized PAL blocks interconnected by a switch matrix. The switch matrix allows communication between PAL blocks, and routes inputs to the PAL blocks. Together, the PAL blocks and switch matrix allow the logic designer to create large designs in a single device instead of using multiple devices.
Clock/Input Pins
Output Macrocells Array and Allocator I/O Pins PAL Block Buried Macrocells Buried Macrocell Feedback Output Macrocell Feedback I/O Pin Feedback
(note 1)
I/O Cells
I/O Pins
PAL Block
I/O Pins
PAL Block
Switch Matrix
PAL Block
I/O Pins
14051K-002
Note: 1. There are no buried macrocells in MACH 1 devices. All macrocells are output macrocells. Device MACH111(SP) MACH131(SP) MACH211(SP) MACH221(SP) MACH231(SP) PAL Blocks 2 4 4 8 8 Macrocells per Block 16 16 16 12 16 I/Os per Block 16 16 8 6 8 Product Terms per Block 70 70 68 52 68
Dedicated Input
Figure 1. Overall Architecture of MACH 1 & 2 Devices
The switch matrix takes all dedicated inputs and signals from the input switch matrices and routes them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must go through the switch matrix. This mechanism ensures that PAL blocks in MACH devices communicate with each other with guaranteed xed timing (SpeedLocking). The switch matrix makes a MACH device more advanced than simply several PAL devices on a single chip. It allows the designer to think of the device not as a collection of blocks, but as a single programmable device; the software partitions the design into PAL blocks through the central switch matrix so that the designer does not have to be concerned with the internal architecture of the device.
MACH 1 & 2 Families
Each PAL block consists of the following elements:

x x x x
Product-term array Logic Allocator Macrocells I/O cells
Each PAL block additionally contains an asynchronous reset product term and an asynchronous preset product term. This allows the ip-ops within a single PAL block to be initialized as a bank. There are also output enable product terms that provide tri-state control for the I/O cells. Product-Term Array The product-term array consists of a number of product terms that form the basis of the logic being implemented. The inputs to the AND gates come from the switch matrix (Table 4), and are provided in both true and complement forms for efcient logic implementation. Because the number of product terms available for a given function is not xed, the full sum of products is not realized in the array. The product terms drive the logic allocator, which allocates the appropriate number of product terms to generate the function.
Table 4. PAL Block Inputs
Device MACH111 MACH111SP MACH131 MACH131SP MACH211 Number of Inputs to PAL Block 26 26 26 26 26 MACH221 MACH221SP MACH231 MACH231SP Device MACH211SP Number of Inputs to PAL Block 26 26 26 32 32
Logic Allocator The logic allocator (Figure 2) is a block within which different product terms are allocated to the appropriate macrocells in groups of four product terms called product term clusters. The availability and distribution of product term clusters is automatically considered by the software as it ts functions within the PAL block. The size of the product term clusters has been designed to provide high utilization of product terms. Complex functions using many product terms are possible, and when few product terms are used, there will be a minimal number of unused, or wasted, product terms left over. The product term clusters do not wrap around the logic block. This means that the macrocells at the ends of the block have fewer product terms available (Tables 5, 6, 7, 8).
MACH 1 & 2 Families
To n-2
To n-1
From n-1
n
Product Term Cluster
To Macrocell n
* To n+1 From From n+1 n+2

Logic Allocator
14051K-003
*MACH 2 only
Figure 2. Product Term Clusters and the Logic Allocator
Table 5. Logic Allocation for MACH111(SP)

Output Macrocell M0 M1 M2 M3 M4 M5 M6 M7 Available Clusters C0, C1 C0, C1, C2 C1, C2, C3 C2, C3, C4 C3, C4, C5 C4, C5, C6 C5, C6, C7 C6, C7 Output Macrocell M8 M9 M10 M11 M12 M13 M14 M15 Available Clusters C8, C9 C8, C9, C10 C9, C10, C11 C10, C11, C12 C11, C12, C13 C12, C13, C14 C13, C14, C15 C14, C15

Output Macrocell M0 M1 M2 M3 M4 M5 M6 M7 Available Clusters C0, C1 C0, C1, C2 C1, C2, C3 C2, C3, C4 C3, C4, C5 C4, C5, C6 C5, C6, C7 C6, C7, C8 Output Macrocell M8 M9 M10 M11 M12 M13 M14 M15 Available Clusters C7, C8, C9 C8, C9, C10 C9, C10, C11 C10, C11, C12 C11, C12, C13 C12, C13, C14 C13, C14, C15 C14, C15
MACH 1 & 2 Families
Table 7. Logic Allocation for MACH211(SP) and MACH231(SP)

Macrocell Output M0 M1 M2 M3 M4 M5 M6 M7 Buried Available Clusters C0, C1, C2 C0, C1, C2, C3 C1, C2, C3, C4 C2, C3, C4, C5 C3, C4, C5, C6 C4, C5, C6, C7 C5, C6, C7, C8 C6, C7, C8, C9 M8 M9 M10 M11 M12 M13 M14 M15 Macrocell Output Buried Available Clusters C7, C8, C9, C10 C8, C9, C10, C11 C9, C10, C11, C12 C10, C11, C12, C13 C11, C12, C13, C14 C12, C13, C14, C15 C13, C14, C15 C14, C15

Macrocell Output M0 M1 M2 M3 M4 M5 Buried Available Clusters C0, C1, C2 C0, C1, C2, C3 C1, C2, C3, C4 C2, C3, C4, C5 C3, C4, C5, C6 C4, C5, C6, C7 M6 M7 M8 M9 M10 M11 Macrocell Output Buried Available Clusters C5, C6, C7, C8 C6, C7, C8, C9 C7, C8, C9, C10 C8, C9, C10, C11 C9, C10, C11 C10, C11
Macrocell There are two fundamental types of macrocell: the output macrocell and the buried macrocell. The buried macrocell is only found in MACH 2 devices. The use of buried macrocells effectively doubles the number of macrocells available without increasing the pin count. Both macrocell types can generate registered or combinatorial outputs. For the MACH 2 series, a transparent-low latch conguration is provided. If the register is used, it can be congured as a T-type or a D-type ip-op. Register and latch functionality is dened in Table 9. Programmable polarity (for output macrocells) and the T-type ip-op both give the software a way to minimize the number of product terms needed. These choices can be made automatically by the software when it ts the design into the device.
Table 9. Register/Latch Operation
Conguration D-Register D/T X 0 1 X T-Register 0 1 X Latch 0 1 CLK/LE 0,1, 0,1, 1 0 0 Q+ Q 0 1 Q Q Q Q 0 1
MACH 1 & 2 Families
The output macrocell (Figure 3) sends its output back to the switch matrix, via internal feedback, and to the I/O cell. The feedback is always available regardless of the conguration of the I/O cell. This allows for buried combinatorial or registered functions, freeing up the I/O pins for use as inputs if not needed as outputs. The basic output macrocell congurations are shown in Figure 4. The buried macrocell (Figure 5) does not send its output to an I/O cell. The output of a buried macrocell is provided only as an internal feedback signal which feeds the switch matrix. This allows the designer to generate additional logic without requiring additional pins. The buried macrocell can also be used to register or latch inputs. The input register is a D-type ip-op; the input latch is a transparent-low D-type latch. Once congured as a registered or latched input, the buried macrocell cannot generate logic from the product-term array. The basic buried macrocell congurations are shown in Figure 6.
PAL-Block Asynchronous Preset Sum of Products from Logic Allocator AP D/T/L1 Q
1 1 0 0 To I/O Cell
CLK0
CLKn PAL-Block Asynchronous Reset AR
To Switch Matrix
14051K-004
Note: 1. Latch option available on MACH 2 devices only.
Figure 3. Output Macrocell
MACH 1 & 2 Families
From Logic Allocator
To I/O Cell
To I/O Cell
To Switch Matrix
a. Combinatorial, active high
To Switch Matrix
b. Combinatorial, active low
From Logic Allocator CLK0 CLKn
D APQ AR
To I/O Cell
D AP Q AR
To I/O Cell
To Switch Matrix
To Switch Matrix
c. D-type register, active high
d. D-type register, active low
From Logic Allocator CLK0 CLKn To Switch Matrix
T AP Q AR
To I/O Cell
T AP Q AR
To I/O Cell
To Switch Matrix f. T-type register, active low
e. T-type register, active high
From Logic Allocator CLK0 CLKn To Switch Matrix
L APQ G
To I/O Cell
From Logic Allocator CLK0
L APQ G AR
To I/O Cell
AR
CLKn To Switch Matrix
g. Latch, active high (MACH 2 only)
h. Latch, active low (MACH 2 only)

14051K-005
Figure 4. Output Macrocell Congurations
MACH 1 & 2 Families
PAL-Block Asynchronous Preset Sum of Products From Logic IC Allocator CLK0 CLKn PAL-Block Asynchronous Reset 1 0 AP D/T/L Q
From I/O Pin 1
AR
To Switch Matrix
14051K-030
Figure 5. Buried Macrocell (MACH 2 only)

From Logic Allocator CLK0 To Switch Matrix CLKn To Switch Matrix a. Combinatorial From Logic Allocator CLK0 CLKn To Switch Matrix c. T-type register From Logic Allocator CLK0 CLKn To Switch Matrix To Switch Matrix e. Latch f. Input latch
14051K-006
AP
AR
b. D-type register AP From I/O Cell Q D AR CLK0 CLKn To Switch Matrix d. Input register AP From I/O Cell Q L G AR CLK0 CLKn G AP Q AR AP Q
AR
Figure 6. Buried Macrocell Congurations (MACH 2 only)
10
MACH 1 & 2 Families
The ip-ops in either macrocell type can be clocked by one of several clock pins (Table 10). Registers are clocked on the rising edge of the clock input. Latches hold their data when the gate input is HIGH. Clock pins are also available as inputs, although care must be taken when a signal acts as both clock and input to the same device.
Table 10. Macrocell Clocks
Device MACH111 MACH111SP MACH131 MACH131SP MACH211 Number of Clocks Available 4 2 4 4 4 MACH221 MACH221SP MACH231 MACH231SP Device MACH211SP Number of Clocks Available 2 4 4 4 4
All ip-ops have asynchronous reset and preset. This is controlled by the common product terms that control all ip-ops within a PAL block. For a single PAL block, all ip-ops, whether in an output or a buried macrocell, are initialized together. The initialization functionality of the ip-ops is illustrated in Table 11.
Table 11. Asynchronous Reset/Preset Operation
Conguration AR 0 Register 0 1 1 0 0 0 Latch 1 1 1 1 AP 0 1 0 1 0 1 1 0 0 1 1 CLK/LE X X X X X 0 1 0 1 0 1 Q+ See Table 9 1 0 0 See Table 9 Illegal 1 Illegal 0 Illegal 0
I/O Cells The I/O cells (Figure 7) provide a three-state output buffer. The three-state buffer can be left permanently enabled for use only as an output, permanently disabled for use as an input, or it can be controlled by one of two product terms for bi-directional signals and bus connections. The two product terms provided are common to a bank of I/O cells.
MACH 1 & 2 Families
11
Output Enable Product Terms (Common to bank of I/O Cells)
0 1 1 1
VCC
1 0 0 0
From Output Macrocell To Switch Matrix To Buried Macrocell (MACH 2 only)
14051K-007
Figure 7. I/O Cell
SPEEDLOCKING FOR GUARANTEED FIXED TIMING The unique MACH 1 & 2 architecture is designed for high performancea metric that is met in both raw speed, and even more importantly, guaranteed xed speed. The design of the switch matrix and PAL blocks guarantee a xed pin-to-pin delay that is independent of the logic required by the design. Other non-Lattice/Vantis CPLDs incur serious timing delays as product terms expand beyond their typical 4 or 5 product term limits (Figure 8). Speed and SpeedLocking combine to give designers easy access to the performance required in todays designs.
MACH 1 & 2 SpeedLocking Patented Architecture Path Independent Logic/Routing Independent Guaranteed Fixed Timing Up to 16 Product Terms per Output Non-MACH Variable Path Dependent Logic/Routing Dependent Delays Unpredictable 4-5 Product Terms before Delays
SpeedLocking
11 10 tPD (ns) 9 8 7 6 5 Shared Expander Delay 8.8 ns Parallel Expander Delay 6.6 ns 5.8 ns 5 ns 5 PT 10 PT 15 PT
14051K-001
10.4 ns Non-MACH 7.4 ns MACH 1 & 2
Product Terms
Figure 8. Timing in MACH 1 & 2 vs. Non-MACH Devices
12
MACH 1 & 2 Families
JTAG IN-SYSTEM PROGRAMMING Programming devices in-system provides a number of signicant benets including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-eld modications. All MACHxxxSP devices provide in-system programming (ISP) capability through their JTAG ports. This capability has been implemented in a manner that insures that the JTAG port remains compliant to the IEEE 1149.1 standard. By using JTAG as the communication interface through which ISP is achieved, customers benet from a standard, well-dened interface. MACHxxxSP devices can be programmed across the commercial temperature and voltage range. These devices tristate the outputs during programming. Lattice/Vantis provides its free PC-based Lattice/VantisPRO software to facilitate in-system programming. Lattice/VantisPRO software takes the JEDEC le output produced by Vantis design implementation software, along with information about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. Lattice/ VantisPRO software can use these vectors to drive a JTAG chain via the parallel port of a PC. Alternatively, Lattice/VantisPRO software can output les in formats understood by common automated test equipment. This equipment can then be used to program MACHxxxSP devices during the testing of a circuit board. For more information about in-system programming, refer to the separate document entitled MACH ISP Manual. BUS-FRIENDLY INPUTS AND I/Os The MACH 1 & 2 inputs and I/Os include two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state. For the circuit diagram, please refer to the Input/Output Equivalent Schematics (page 393) in the General Information Section of the Vantis 1999 Data Book. PCI COMPLIANT The MACH 1 & 2 families in -5/-6/-7/-10/-12 speed grades are fully compliant with the PCI Local Bus Specication published by the PCI Special Interest Group. The MACH 1 & 2 families predictable timing ensures compliance with the PCI AC specications independent of the design. POWER-DOWN MODE The MACH 1 & 2 families feature a programmable low-power mode in which individual signal paths can be programmed for low power. These low-power speed paths will be slower than the non-low-power paths. This feature allows speed critical paths to run at maximum frequency while the rest of the paths operate in the low-power mode, resulting in power savings of up to 75%. If all of the signals in a PAL block are in low-power mode, then the total power is reduced even further. SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS All MACHxxxSP and most of the MACH 1 & 2 devices are safe for mixed supply voltage system designs. These 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they can accept inputs from other 3.3-V devices. The MACH 1 & 2 families provide easy-touse mixed-voltage design compatibility. For more information, refer to the Technical Note entitled Mixed Supply Design with MACH 1 & 2 SP Devices. POWER-UP RESET All ip-ops power-up to a logic LOW for predictable system initialization. The actual values of the outputs of the MACH devices will depend on the conguration of the macrocell. To guarantee
MACH 1 & 2 Families
13
initialization values, the VCC rise must be monotonic and the clock must be inactive until the reset delay time has elapsed. SECURITY BIT A security bit is provided on the MACH devices as a deterrent to unauthorized copying of the array conguration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verication are also defeated by the security bit. The bit can only be reset by erasing the entire device.
14
MACH 1 & 2 Families
MACH111(SP) AND MACH131(SP) PAL BLOCK

0 4 8 12 16 20 24 28 32 36 40 43 47 51 Output Enable Output Enable Asynchronous Reset Asynchronous Preset
M0
Output Macro Cell
I/O Cell
I/O
M1
Output Macro Cell
I/O Cell
I/O
M2
Output Macro Cell
I/O Cell
I/O
M3
0
Output Macro Cell
I/O Cell
I/O
C0 C1 C2 C3 C4 C5 Logic Allocator
I/O Cell
M4
Output Macro Cell
I/O
M5
Output Macro Cell
I/O Cell
I/O
I/O Cell
I/O
M6
Output Macro Cell
Switch Matrix
C6 C7 C8 C9
I/O Cell
I/O
M7
Output Macro Cell
M8
Output Macro Cell
I/O Cell
I/O
C10 C11 C12 C13 C14 C15

63
M9
Output Macro Cell
I/O Cell
I/O
M10
Output Macro Cell
I/O Cell
I/O
M11
Output Macro Cell
I/O Cell
I/O
M12
Output Macro Cell
I/O Cell
I/O
I/O Cell
I/O
M13
Output Macro Cell
I/O Cell Output Macro Cell I/O Cell Output Macro Cell CLK
I/O
M14
I/O
M15
for MACH111SP for MACH111, MACH131, MACH131SP Output Enable Output Enable 0 4 8 16 16 12 16 20 24 28 32 36 40 43 47 51
2 4
14051K-013
MACH 1 & 2 Families
15
MACH211(SP) PAL BLOCK

M0
Output Macro Cell
I/O Cell
I/O
M1
Buried Macro Cell
M2
Output Macro Cell
I/O Cell
I/O
M3
0
Buried Macro Cell
C0 C1 C2 C3 C4 C5 Logic Allocator
I/O Cell
M4
Output Macro Cell
I/O
M5
Buried Macro Cell
I/O Cell
I/O
M6
Output Macro Cell
Switch Matrix
C6 C7 C8 C9
M7
Buried Macro Cell
M8
Output Macro Cell
I/O Cell
I/O
C10 C11 C12 C13 C14 C15

63
M9
Buried Macro Cell
M10
Output Macro Cell
I/O Cell
I/O
M11
Buried Macro Cell
M12
Output Macro Cell
I/O Cell
I/O
M13
Buried Macro Cell
I/O Cell
I/O
M14
Output Macro Cell
M15
CLK
Buried Macro Cell
for MACH211SP
for MACH211 0 4 8 16 8 12 16 20 24 28 32 36 40 43 47 51
14051K-015
16
MACH 1 & 2 Families

M0
Output Macro Cell
I/O Cell
I/O
M1
Buried Macro Cell
M2 C0 C1 C2 C3 C4 M4 Logic Allocator M3
Output Macro Cell
I/O Cell
I/O
Buried Macro Cell
Output Macro Cell
I/O Cell
I/O
Switch Matrix
C5 C6 C7 C8 C9
M5
Buried Macro Cell
M6
Output Macro Cell
I/O Cell
I/O
C10
47
M7
Buried Macro Cell
C11 M8
Output Macro Cell
I/O Cell
I/O
M9
Buried Macro Cell
M10
Output Macro Cell
I/O Cell
I/O
M11
Buried Macro Cell
12
16
20
24
28
32
36
40
43
47
51 CLK 4
12 6
14051K-016
MACH 1 & 2 Families
17

0 4 8 12 16 20 24 28 32 36 40 43 47 51 55 59 63 Output Enable Output Enable Asynchronous Reset Asynchronous Preset
M0
Output Macro Cell
I/O Cell
I/O
M1
Buried Macro Cell
M2
Output Macro Cell
I/O Cell
I/O
M3
Buried Macro Cell
I/O Cell
M4
Output Macro Cell
I/O
M5 C0 C1 M6
Buried Macro Cell
I/O Cell Output Macro Cell
I/O
Logic Allocator
C2 C3
Switch Matrix
M7
Buried Macro Cell
C4 C5 C6 C7 C8 C9
M8
Output Macro Cell
I/O Cell
I/O
M9
Buried Macro Cell
C10 C11 C12 C13 C14

63
M10
Output Macro Cell
I/O Cell
I/O
M11
Buried Macro Cell
M12
Output Macro Cell
I/O Cell
I/O
C15 M13
Buried Macro Cell
I/O Cell
I/O
M14
Output Macro Cell
M15
CLK
Buried Macro Cell
8 16
12
16
20
24
28
32
36
40
43
47
51
55
59
63
14051K-017
18
MACH 1 & 2 Families
BLOCK DIAGRAM (MACH111, MACH111SP)

CLK0 /I1 CLK1 /I2 CLK2/I4 CLK3 /I5 CLK0 /I0 CLK1 /I1 MACH111
Block A I/O0 I/O15
MACH111SP
16 16 I/O Cells 16 4 Macrocells 16 4 MACH111 2 MACH111SP
OE 52 x 70 AND Logic Array and Logic Allocator 26
Switch Matrix 26 52 x 70 AND Logic Array and Logic Allocator OE
Macrocells 16 16
I/O Cells 16 16
2 MACH111 Only
I/O16 I/O31 Block B
I0 I3
MACH111
14051K-008
MACH 1 & 2 Families
19

Block A I/O0 I/O15 Block B I/O16 I/O31 I2, I5
16 I/O Cells 4 16 Macrocells OE 52 x 70 AND Logic Array and Logic Allocator 26 16 4 OE 52 x 70 AND Logic Array and Logic Allocator 26 Switch Matrix 26 52 x 70 AND Logic Array and Logic Allocator OE 4 Macrocells 16 I/O Cells 16 16 4 4 OE Macrocells 16 I/O Cells 26 52 x 70 AND Logic Array and Logic Allocator 4 I/O Cells 16 Macrocells
16
16 4
4 16
16
I/O48 I/O63 Block D
I/O32 I/O47 Block C
CLK0/I0, CLK1/I1 CLK2/I3, CLK3/I4

14051K-009
20
MACH 1 & 2 Families

CLK0 /I1 CLK1 /I2 CLK2/I4 CLK3 /I5 Block A I/O0I/O7 8 I/O Cells 8 Macrocells 2 OE 52 x 68 AND Logic Array and 26 Switch Matrix 26 52 x 68 AND Logic Array and Logic Allocator OE 2 Macrocells 8 I/O Cells 8 8 Macrocells 8 26 52 x 68 AND Logic Array and Logic Allocator OE 2 Macrocells 8 I/O Cells 8 8 Macrocells 8 2 MACH211 only 8 8 Macrocells I/O Cells 8 Macrocells 2 OE 52 x 68 AND Logic Amrray and 26 I/O8I/O15 Block B MACH211 only CLK0 /I0 CLK1 /I1 MACH211
MACH211SP
8 8 8 Macrocells 2 MACH211SP 4 MACH211
I/O24I/O31 Block D
I/O16I/O23 Block C
I0 I3
MACH211
14051K-010
MACH 1 & 2 Families
21
22
Block B
I/O12 I/O17 I/O18 I/O23
Block A
Block C
Block D
I/O0 I/O5
I/O6 I/O11
I2I3, I6I7
6 I/O Cells 6 6 6 6 I/O Cells I/O Cells
I/O Cells
6
Macrocells Macrocells 2 O 52 x 52 AND Logic Array and Logic Allocator 26 Switch Matrix 26 52 x 52 AND Logic Array and Logic Allocator O 2 Macrocells Macrocells 6 6 Macrocells 2 Macrocells 6 6 Macrocells O 2 52 x 52 AND Logic Array and Logic Allocator 26 26 26 O 52 x 52 AND Logic Array and Logic Allocator 2 2 Macrocells Macrocells Macrocells
6
Macrocells 4 4
Macrocells
Macrocells
O 52 x 52 AND Logic Array and Logic Allocator
O 52 x 52 AND Logic Array and Logic Allocator 26
26
MACH 1 & 2 Families 6

I/O Cells 6
26
52 x 52 AND Logic Array and Logic Allocator
52 x 52 AND Logic Array and Logic Allocator O
Macrocells
Macrocells
Macrocells
6
I/O Cells
6
I/O Cells 6
I/O Cells
I/O42 I/O47
I/O36 I/O41
I/O30 I/O35
I/O24 I/O29
Block H
Block G
Block F
Block E
14051K-011
I/O0 I/O7 (Block A)
I/O8 I/O15 (Block B)
I/O16 I/O23 (Block C)
I/O24 I/O31 (Block D)
I2, I5
8 I/O Cells 8 8 8 8 I/O Cells I/O Cells
I/O Cells
8
Macrocells Macrocells 2 OE
64 x 68 AND Logic Array and Logic Allocator 64 x 68 AND Logic Array and Logic Allocator
8
Macrocells Macrocells 2 OE 2 OE Macrocells
8
Macrocells 4 2
Macrocells
Macrocells
OE
32 Switch Matrix 32
64 x 68 AND Logic Array and Logic Allocator 64 x 68 AND Logic Array and Logic Allocator
32
32
32
32
32
32
MACH 1 & 2 Families

2 Macrocells Macrocells 8 8 8 Macrocells OE 2 OE Macrocells 8 8 8
4 2 Macrocells OE
OE
Macrocells
Macrocells
Macrocells
8
I/O Cells
8
I/O Cells
8
I/O Cells
8 8
I/O Cells
I/O56 /O63 (Block
I/O48 I/O55 (Block G)
I/O40 I/O47 (Block F)
I/O32 I/O39 (Block E)
14051K-012
23
ABSOLUTE MAXIMUM RATINGS

Storage Temperature . . . . . . . . . . . . . .-65C to +150C Ambient Temperature With Power Applied . . . . . . . . . . . . . .-55C to +125C Device Junction Temperature . . . . . . . . . . . . . +150C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC +0.5 V DC Output or I/O Pin Voltage . . -0.5 V to VCC +0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40C to +85C). . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Operating ranges dene those limits between which the functionality of the device is guaranteed.
Industrial (I) Devices

Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . -40C to +85C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges dene those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS OVER OPERATING RANGES

Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Test Description IOH = 3.2 mA, VCC = Min, VIN = VIH or VIL IOH = 300 A, VCC = Max, VIN = VIH or VIL (Note 1) IOL = 16 mA, VCC = Min, VIN = VIH or VIL (Note 2) Guaranteed Input Logical HIGH Voltage for all Inputs (Note 3) Guaranteed Input Logical LOW Voltage for all Inputs (Note 3) VIN = 5.25 V, V VCC = Max (Note 4) VIN = 0 V, VCC = Max (Note 4) 2.0 0.8 10 10 10 10 30 130 (Note 6), 160 Min 2.4 3.5 0.5 Typ Max Unit V V V V V A A A A mA
Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max, VIN = VIH or VIL (Note 4) Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max, VIN = VIH or VIL (Note 4) Output Short-Circuit Current VOUT = 0.5 V VCC = Max (Note 5)
Notes: 1. This applies to MACH111SP, MACH131SP, and die code B or later for MACH211(SP) and MACH231(SP). This does not apply to MACH111, MACH131, MACH221(SP), and die code A for MACH211(SP) and MACH231(SP). 2. Total IOL for one PAL block should not exceed 64 mA. 3. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included. 4. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 5. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 6. For commercial temperature range only.
24
MACH 1 & 2 Families
MACH111 AND MACH111SP SWITCHING CHARACTERISTICS OVER OPERATING RANGES1

Parameter Symbol
-5 Parameter Description
-7
-10
-12
-14
-15
-18
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
tPD tS tH tCO tWL tWH
Input, I/O, or Feedback to Combinatorial Output Setup Time from Input, I/O, or Feedback D-type to Clock T-type Register Data Hold Time Clock to Output Clock Width External Feedback 1/(tS + tCO) LOW HIGH D-type T-type D-type T-type 2.5 2.5 143 133 182 167 200 3.5 4 0
5 5.5 6.5 0 3.5 3 3 95 87 133 125 167 7.5 4.5 4.5 7.5 4.5 4.5 7.5 7.5 10 7 3 10 5 5 5 5
7.5 6.5 7.5 0 5 5 5 80 74 100 91 100 9.5 7.5 7.5 9.5 7.5 7.5 9.5 9.5 10 7 3 10
10 7 8 0 6 6 6 66.7 62.5 76.9 71.4 83.3 11 12 8 11 12 8 10 10 10 7 3 10
12 8.5 10 0 8 6 6 54 50 69 57 83.3 16 14.5 10 16 14.5 10 12 12 10 7 3 10
14 10 11 0 10 6 6 50 47.6 66.6 55.5 83.3 19.5 15 10 19.5 15 10 14.5 14.5 10 7 3 10
15 12 13.5 0 10 7.5 7.5 42 39 53 44 66.7 20 18 12 20 18 12 15 15 10 7 3 10
18
ns ns ns ns
12
ns ns ns MHz MHz MHz MHz MHz
fMAX
Maximum Frequency Internal Feedback (fCNT) No Feedback 1/(tWL + tWH)
tAR tARW tARR tAP tAPW tAPR tEA tER tLP tLPS tLPCO tLPEA
Asynchronous Reset to Registered Output Asynchronous Reset Width (Note 2) Asynchronous Reset Recovery Time (Note 2) Asynchronous Preset to Registered Output Asynchronous Preset Width (Note 2) Asynchronous Preset Recovery Time (Note 2) Input, I/O, or Feedback to Output Enable Input, I/O, or Feedback to Output Disable tPD Increase for Powered-down Macrocell (Note 3) tS Increase for Powered-down Macrocell (Note 3) tCO Increase for Powered-down Macrocell (Note 3) tEA Increase for Powered-down Macrocell (Note 3)
24
ns ns ns
24
ns ns ns
18 18 10 7 3 10
ns ns ns ns ns ns
Notes: 1. See Switching Test Circuit in the General Information Section of the Vantis 1999 Data Book. 2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modied where this parameter may be affected. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
MACH 1 & 2 Families
25
MACH131 AND MACH131SP SWITCHING CHARACTERISTICS OVER OPERATING RANGES1

-5
Parameter Symbol
-7
-10
-12
-14
-15
-18
Parameter Description
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Input, I/O, or Feedback to Combinatorial Output Setup Time from Input, I/O, or Feedback Hold Time Clock to Output Clock Width External Feedback LOW HIGH 1/(tS + tCO) D-type T-type D-type T-type 2.5 2.5 143 133 182 167 200 D-type T-type 3.0 3.5 0
5.5 5.5 6.5 0 4 3 3 95 87 133 125 167 8.5 4.5 4.5 8.5 4.5 4.5 7.5 7.5 10 7 3 10 5 5 5 5
7.5 6.5 7.5 0 5 4 4 80 74 100 91 125 9.5 7.5 7.5 9.5 7.5 7.5 9.5 9.5 10 7 3 10
10 7 8 0 6 6 6 66.7 62.5 76.9 71.4 83.3 11 12 8 11 12 8 10 10 10 7 3 10
12 8.5 10 0 8 6 6 54 50 69 57 83.3 16 14.5 10 16 14.5 10 12 12 10 7 3 10
14 10 11 0 10 6 6 50 47.6 66.6 55.5 83.3 19.5 15 10 19.5 15 10 14.5 14.5 10 7 3 10
15 12 13.5 0 10 7.5 7.5 42 39 53 44 66.7 20 18 12 20 18 12 15 15 10 7 3 10
18
ns ns ns ns
12
ns ns ns MHz MHz MHz MHz MHz
fMAX
Maximum Frequency
Internal Feedback (fCNT) No Feedback 1/(tWL + tWH)
Asynchronous Reset to Registered Output Asynchronous Reset Width (Note 2) Asynchronous Reset Recovery Time (Note 2) Asynchronous Preset to Registered Output Asynchronous Preset Width (Note 2) Asynchronous Preset Recovery Time (Note 2) Input, I/O, or Feedback to Output Enable Input, I/O, or Feedback to Output Disable tPD Increase for Powered-Down Macrocell (Note 3) tS Increase for Powered-Down Macrocell (Note 3) tCO Increase for Powered-Down Macrocell (Note 3) tEA Increase for Powered-Down Macrocell (Note 3)
24
ns ns ns
24
ns ns ns
18 18 10 7 3 10
ns ns ns ns ns ns
Notes: 1. See Switching Test Circuit in the General Information Section of the Vantis 1999 Data Book.. 2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modied where this parameter may be affected. 3. If a signal is powered down, this parameter must be added to its respective high-speed parameter.
26
MACH 1 & 2 Families
MACH211 AND MACH211SP SWITCHING CHARACTERISTICS OVER OPERATING RANGES

Parameter Symbol -6 Parameter Description Input, I/O, or Feedback to Combinatorial Output Setup Time from Input, I/O, or Feedback D-type to Clock T-type Register Data Hold Time Clock to Output Clock Width External Feedback LOW HIGH 1/(tS + tCO) D-type T-type D-type T-type 2.5 2.5 111 105 166 150 200 5 0 7 2.5 9 1.5 1.5 10 8 9 2.5 2.5 200 1.5 1.5 12 13 7 9 2.5 12 7.5 10 3 12.5 9 10 3 3 167 2 2 12 14 8.5 11 5 14 2 2 11 10 11 5 5 100 2 2 14 16 9 13 6 16 3 9.5 2 2 13 12 13 6 6 83.3 2 2 17 19 11 16 6 19 5 5.5 0 4 3 3 100 91 133 125 167 5.5 0 7 7.5
(note 4)
1
-15 -18 Max Unit 18 12 13.5 0 10 6 6 50 47.6 66.6 62.5 83.3 10 0 11 11 6 17 17 2 2.5 18 18 15 16 6 6 83.3 2 2.5 20 22 12 16 6 19 20 22 14.5 19.5 7.5 23 18 19.5 7.5 7.5 66.7 2.5 3.5 24 26.5 2.5 3.5 20
(note 6)
-7 Min Max 7.5 5.5 6.5 0 4.5 5 5 80 74 100 91 100 6.5 0 6.5 7.5 0 Min
-10 Max 10 7 8 0 6 6 6
-12
-14
Min Max 6
Min Max Min Max Min Max Min 12 8.5 10 0 8 6 6 54 50 69 62.5 83.3 8.5 0 10 6 6 14 2 2 15 14.5 16 6 6 83.3 2 2.5 2 2.5 10 14 10 11 0 15
ns ns ns ns
12 7.5 7.5 42 39 55.6 51.3 66.7 12 0 13

(note 6)
ns ns ns MHz MHz MHz MHz MHz ns ns ns ns
66.7 62.5 83.3 76.9 83.3 7 0 7 8

(note 5)
fMAX
Maximum Frequency
tSL tHL tGO tGWL tPDL tSIR tHIR tICO tICS tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL tSLL tIGS tWIGL tPDLL
Setup Time from Input, I/O, or Feedback to Gate Latch Data Hold Time Gate to Output Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input or Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock to Combinatorial Output Input Register Clock to Output Register Setup Input Register Clock Width Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate Input Latch Gate to Output Latch Setup Input Latch Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input and Output Latches D-type T-type LOW HIGH 1/(tWICL + tWICH)
13.5 7.5 20
(note 6)
5 12
ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns ns
20.5
22
MACH 1 & 2 Families
27
MACH211 AND MACH211SP (CONTINUED) SWITCHING CHARACTERISTICS OVER OPERATING RANGES

Parameter Symbol -6 Parameter Description Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 2) Asynchronous Reset Recovery Time (Note 2) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 2) Asynchronous Preset Recovery Time (Note 2) Input, I/O, or Feedback to Output Enable Input, I/O, or Feedback to Output Disable tPD Increase for Powered-down Macrocell (Note 3) tS Increase for Powered-down Macrocell (Note 3) tCO Increase for Powered-down Macrocell (Note 3) tEA Increase for Powered-down Macrocell (Note 3) 4 4 9 9 10 10 0 10 4 4 9 5 5 9.5 9.5 10 10 0 10 Min Max 9 5 5 9.5 10 10 10 10 10 10 0 10 Min -7 Max 9.5 10 10 15 12 10 12 12 10 10 0 10 Min -10 Max 15 12 10 16 14.5 10 14 14 10 10 0 10 -12 -14
1
-15 -18 Max Unit 24 18 12 20 15 10 15 15 10 10 0 10 18 12 18 18 10 10 0 10 24 ns ns ns ns ns ns ns ns ns ns ns ns
Min Max Min Max Min Max Min 16 14.5 10 19.5 19.5 15 10 20
Notes: 1. See Switching Test Circuit in the General Information Section of the Vantis 1999 Data Book. 2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modied where this parameter may be affected. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter. 4. MACH211 tGO = 7 ns. MACH211SP tGO = 7.5 ns. 5. MACH211, commercial tGO = 7 ns. 6. The faster -18 tGO, tPDL, tICO, apply to MACH211 only, not MACH211SP.
28
MACH 1 & 2 Families
MACH221 and MACH221SP SWITCHING CHARACTERISTICS OVER OPERATING RANGES

Parameter Symbol -7 Parameter Description Input, I/O, or Feedback to Combinatorial Output Setup Time from Input, I/O, or Feedback to Clock Register Data Hold Time Clock to Output Clock Width External Feedback LOW HIGH 1/(tS + tCO) D-type T-type D-type T-type 3 3 95 87 133 125 167 5.5 0 7 3 9.5 2 2 11 D-type T-type LOW HIGH 1/(tWICL + tWICH) 9 10 3 3 167 2 2 12 14 7.5 10 3 11.5 9.5 5 5 9.5 10 8 15 8.5 11 5 14 15 12 10 16 10 11 5 5 100 2 2 14 16 9 13 6 16 16 14.5 10 19.5 2 2 13 12 13 6 6 83.3 2 2 17 19 11 16 6 19 19.5 5 12 2 2 15 14.5 16 6 6 83.3 2 2.5 20 22 D-type T-type 5.5 6.5 0 5 5 5 80 74 100 91 100 6.5 0 7
(note 2)
1
-15 Min Max 15 10 11 0 12 13.5 0 10 6 6 50 47.6 66.6 62.5 83.3 10 0 7.5 7.5 42 39 55.6 51.3 66.7 12 0 11 6 7.5 17 2 2.5 2.5 3.5 18 15 16 6 6 83.3 2 2.5 20 22 12 16 6 19 20 15 10 20 18 12 24 14.5 19.5 7.5 23 24 18 19.5 7.5 7.5 66.7 2.5 3.5 24 26.5 22 20.5 13.5 12 -18 Min Max 18 Unit ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns
-10 Max 7.5 6.5 7.5 0 6 6 6 Min Max 10 7 8 0
-12 Min Max 12 8.5 10 0 8 6 6 54 50 69
-14 Min Max 14
Min
tPD ts tH tCO tWL tWH
10
66.7 62.5 83.3 76.9 83.3 7 0 10 6 14
fMAX
Maximum Frequency
62.5 83.3 8.5 0 11 6 17 2 2.5 18
tSL tHL tGO tGWL tPDL tSIR tHIR tICO tICS tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL tSLL tIGS tWIGL tPDLL tAR tARW tARR tAP
Setup Time from Input, I/O, or Feedback to Gate Latch Data Hold Time Gate to Output Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input or Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock to Combinatorial Output Input Register Clock to Output Register Setup Input Register Clock Width Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate Input Latch Gate to Output Latch Setup Input Latch Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 3) Asynchronous Reset Recovery Time (Note 3) Asynchronous Preset to Registered or Latched Output
MACH 1 & 2 Families
29
MACH221 and MACH221SP (CONTINUED) SWITCHING CHARACTERISTICS OVER OPERATING RANGES

Parameter Symbol -7 Parameter Description Asynchronous Preset Width (Note 3) Asynchronous Preset Recovery Time (Note 3) Input, I/O, or Feedback to Output Enable Input, I/O, or Feedback to Output Disable tPD Increase for Powered-down Macrocell (Note 4) tS Increase for Powered-down Macrocell (Note 4) tCO Increase for Powered-down Macrocell (Note 4) tEA Increase for Powered-down Macrocell (Note 4) Min 5 5 9.5 9.5 10 10 0 10 Max -10 Min 10 8 12 12 10 10 0 10 Max -12 Min 12 10 12 12 10 10 0 10 Max -14 Min 14.5 10 14 14 10 10 0 10 Max
1
-15 Min 15 10 15 15 10 10 0 10 Max -18 Min 18 12 18 18 10 10 0 10 Max Unit ns ns ns ns ns ns ns ns
tAPW tAPR tEA tER tLP tLPS tLPCO tLPEA
Notes: 1. See Switching Test Circuits in the General Information section of the Vantis 1999 Data Book. 2. MACH221 tGO = 7 ns. MACH221SP tGO = 8 ns. 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modied where this parameter may be affected. 4. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
30
MACH 1 & 2 Families
MACH231 AND MACH231SP SWITCHING CHARACTERISTICS OVER OPERATING RANGES

Parameter Symbol -6 Parameter Description Input, I/O, or Feedback to Combinatorial Output Setup Time from Input, I/O, or Feedback D-type to Clock T-type Register Data Hold Time Clock to Output LOW Clock Width HIGH External Feedback D-type 1/(tS + tCO) T-type D-type Internal Feedback (fCNT) No Feedback T-type 2.5 111 100 166 150 200 5 0 5 2 9 1.5 1.5 10 8 9 2.5 2.5 200 1.5 1.5 11 13 7 9 7.5 10 9 10 3 3 167 2 2 12 14 10 11 2 2 11 11 12 4 4 125 2 2.5 17 18 10.5 13.5 3 9.5 2 2.5 15.5 12 13 6 6 83.3 2.5 3 17 19.5 11 16 3 95 87 133 125 167 5.5 0 6 4 14 2 2.5 16 14.5 16 6 6 83.3 2.5 3 4 77 72 100 91 125 6.5 0 7.5 6 14.5 2 2.5 6 66.7 62.5 83.3 76.9 83.3 7 0 8.5 6 6 54 50 69 62.5 83.3 8.5 0 2.5 5 6 0 4 3 Min Max 6 5.5 6.5 0 5 4 Min -7 Max 7.5 6.5 7.5 0 6.5 6 -10 Min Max 10 7 8 0 8 6 -12 Min Max 12 8.5 10 0 -14 Min
1
-15 Min Max 15 10 11 0 10 6 6 50 47.6 66.6 62.5 83.3 10 0 11 6 17 2 2.5 18 15 16 6 6 83.3 2.5 3 20 22 12 16 20 22 14.5 19.5 18 18 19.5 7.5 7.5 66.7 2.5 3.5 24 26.5 17 2.5 3.5 22 11 7.5 20.5 10 7.5 7.5 42 39 55.6 51.3 66.7 12 0 13.5 12 13.5 0 12 -18 Min Max Unit 18 ns ns ns ns ns ns ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns
Max 14
fMAX
Maximum Frequency
1/(tWL + tWH)
tSL tHL tGO tGWL tPDL tSIR tHIR tICO tICS tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL tSLL tIGS
Setup Time from Input, I/O, or Feedback to Gate Latch Data Hold Time Gate to Output Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input or Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock to Combinatorial Output Input Register Clock to output Register Setup Input Register Clock Width Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate Input Latch Gate to Output Latch Setup D-type T-type LOW HIGH
MACH 1 & 2 Families
31
MACH231 AND MACH231SP (CONTINUED) SWITCHING CHARACTERISTICS OVER OPERATING RANGES

Parameter Symbol -6 Parameter Description Input Latch Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 2) Asynchronous Reset Recovery Time (Note 2) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 2) Asynchronous Preset Recovery Time (Note 2) Input, I/O, or Feedback to Output Enable Input, I/O, or Feedback to Output Disable tPD Increase for Powered-down Macrocell (Note 3) tS Increase for Powered-down Macrocell (Note 3) tCO Increase for Powered-down Macrocell (Note 3) tEA Increase for Powered-down Macrocell (Note 3) 4 4 9 9 9 6 0 9 4 4 9 5 5 9.5 9.5 10 7 0 10 Min 2 11 9 5 5 9.5 10 7.5 10 10 10 7 0 10 Max Min 3 12.5 9.5 10 7.5 13 12 8 12 12 10 7 0 10 -7 Max -10 Min 4 16 13 12 8 16 14.5 10 Max -12 Min 6 17 16 14.5 10 Max -14 Min 6
1
-15 Min 6 19 19.5 15 10 19.5 15 10 15 15 10 7 0 10 15 15 10 7 0 10 20 18 12 18 18 10 7 0 10 19 20 18 12 24 Max -18 Min 7.5 23 24 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Max
tWIGL tPDLL tAR tARW tARR tAP tAPW tAPR tEA tER tLP tLPS tLPCO tLPEA
Notes: 1. See Switching Test Circuit in the General Information section of the Vantis 1999 Data Book. 2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modied where this parameter may be affected. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
CAPACITANCE 1
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance VIN = 2.0V VOUT = 2.0V Test Conditions VCC = 5.0V, TA = 25C f = 1 MHz Typ 6 8 Unit pF pF
Note: 1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modied where these parameters may be affected.
32
MACH 1 & 2 Families
ICC vs. FREQUENCY

These curves represent the typical power consumption for a particular device at system frequency. The selected typical pattern is a 16-bit up-down counter. This pattern lls the device and exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type register.
TA = 25C, VCC =5V MACH111(SP)
150 125 ICC (mA) 100 75 50 25 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Low Power High Speed 250 225 200 175 150 125 100 75 50 25 0 0 10 20 30 40 50 60 70 80 90
MACH131(SP)
High Speed Low Power
ICC (mA)
Frequency (MHz)
Frequency (MHz)
MACH211(SP)
High Speed 150 125 ICC (mA) 100 75 50 25 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Low Power ICC (mA) 275 250 225 200 175 150 125 100 75 50 25 0 0 10 20 30
MACH 221(SP)
High Speed Low Power
40
50
60
70
80
90
Frequency (MHz)
Frequency (MHz)
MACH231
400 350 300 ICC (mA) ICC (mA) 250 200 Low Power 150 100 0 0 10 20 30 40 50 60 70 80 High Speed
400 350 300
MACH231SP
High Speed 250 200 150 100 50 0 0 10 20 30 40 50 60 70 80 Low Power
Frequency (MHz)
Frequency (MHz)
MACH 1 & 2 Families
33
Table 12. ICC

Device MACH111(SP) MACH211(SP) MACH221(SP) MACH131(SP) MACH231SP MACH231 MACH111(SP) MACH211(SP) MACH221(SP) MACH131(SP) MACH231SP MACH231 Supply Current (Active) ICC VCC = 5V, TA = 25C, f = 1 MHz Supply Current (Static) VCC = 5V, TA = 25C, f = 0 MHz Parameter Symbol Parameter Description Test Description Typ 40 70 75 80 135 45 75 80 100 150 mA Unit
34
MACH 1 & 2 Families
44- PIN PLCC CONNECTION DIAGRAM (MACH111-5/7/10/12/15 AND MACH111SP-5/7/10/12/15)

Top View
44-Pin PLCC
I/O31
I/O30
I/O29
6 I/O5 I/O6 I/O7 (TDI) I0 (CLK 0/I0) CLK0/I1 Block A GND (TCK) CLK1/I2 I/O8 I/O9 I/O10 I/O11 7 8 9 10 11 12 13 14 15 16 17
5 4
3 2
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 I/O27 I/O26 I/O25 I/O24 CLK3/I5 (TDO) GND CLK2/I4 (CLK 1/I1) I3 (TMS) I/O23 I/O22 I/O21 Block B
18 19 20 21 22 23 24 25 26 27 28 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 I/O18 I/O19 I/O20 GND VCC
I/O28
GND
VCC
I/O4
I/O3
I/O2
I/O1
I/O0
14051K-018
PIN DESIGNATIONS
CLK/I GND I I/O VCC = = = = = Clock or Input Ground Input Input/Output Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out
Note: 1. Pin designators in parentheses ( ) apply to the MACH111SP
MACH 1 & 2 Families
35
44-PIN TQFP CONNECTION DIAGRAM (MACH111-5/7/10/12/15 AND MACH111SP-5/7/10/12/15)

Top View
44-Pin TQFP
Block A
I/O5 I/O6 I/O7 (TDI) I0 (CLK 0/I0) CLK0/I1 GND (TCK) CLK1/I2 I/O8 I/O9 I/O10 I/O11
1 2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34
I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28
33 32 31 30 29 28 27 26 25 24 23
I/O27 I/O26 I/O25 I/O24 CLK3/I5 (TDO) GND CLK2/I4 (CLK 1/I1) I3 (TMS) I/O23 I/O22 I/O21
Block B
I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20
14051K-019
PIN DESIGNATIONS
CLK/I GND I I/O VCC = = = = = Clock or Input Ground Input Input/Output Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out
36
MACH 1 & 2 Families
84-PIN PLCC CONNECTION DIAGRAM (MACH131-5/7/10/12/15)

Top View
84-Pin PLCC
Block A
Block D
I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I0 VCC GND CLK1/I1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 12 73 13 72 14 15 71 70 16 69 17 68 18 67 19 66 20 65 21 64 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCC GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND
GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND VCC I5 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3/I4 GND VCC CLK2/I3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40
Block B
Block C
14051K-020
PIN DESIGNATIONS
CLK/I GND I I/O VCC = = = = = Clock or Input Ground Input Input/Output Supply Voltage
MACH 1 & 2 Families
37
100-PIN PQFP CONNECTION DIAGRAM (MACH131SP-5/7/10/12/15)

Top View
100-Pin PQFP
Block A Block D
GND GND TDI I5 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 IO/CLK0 VCC VCC GND GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 N/C TCK GND GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND GND VCC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56
GND GND TDO N/C I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND GND VCC VCC I3/CLK2 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 I2 TMS GND GND
Block B
Block C
14051K-021
PIN DESIGNATIONS
CLK/I GND I I/O VCC = = = = = Clock or Input Ground Input Input/Output Supply Voltage TDI TCK TMS TDO = = = = Test Test Test Test Data In Clock Mode Select Data Out
38
MACH 1 & 2 Families
100-PIN TQFP CONNECTION DIAGRAM (MACH131SP-5/7/10/12/15)

Top View
100-Pin TQFP
Block A Block D
TDI I/5 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I0/CLK0 VCC GND GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC TCK
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
GND GND NC I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND GND VCC NC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
GND TDO NC I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND VCC I3/CLK2 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 I2 TMS
GND GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 NC VCC GND GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND GND
Block B
Block C
14051K-022
PIN DESIGNATIONS
MACH 1 & 2 Families
39
44-PIN PLCC CONNECTION DIAGRAM (MACH211-7/10/12/15 AND MACH211SP-6/7/10/12/15)

Top View
44-Pin PLCC Block A I/O31 I/O30 I/O29 I/O28 Block D
GND
6 I/O5 I/O6 I/O7 (TDI) I0 (CLK 0/I0) CLK0/I1 GND (TCK) CLK1/I2 I/O8 I/O9 I/O10 I/O11 7 8 9 10 11 12 13 14 15 16 17
5 4
3 2
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 I/O27 I/O26 I/O25 I/O24 CLK3/I5 (TDO) GND CLK2/I4 (CLK 1/I1) I3 (TMS) I/O23 I/O22 I/O21
18 19 20 21 22 23 24 25 26 27 28 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 I/O18 I/O19 I/O20 Block C
14051K-023
VCC
Block B
PIN DESIGNATIONS
40
MACH 1 & 2 Families
GND
VCC
I/O4
I/O3
I/O2
I/O1
I/O0
44-PIN TQFP CONNECTION DIAGRAM (MACH211-7/10/12/15 AND MACH211SP-6/7/10/12/15)

Top View
44-Pin TQFP Block A I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Block D
I/O5 I/O6 I/O7 (TDI) I0 (CLK 0/I0) CLK0/I1 GND (TCK) CLK1/I2 I/O8 I/O9 I/O10 I/O11
I/O27 I/O26 I/O25 I/O24 CLK3/I5 (TDO) GND CLK2/I4 (CLK 1/I1) I3 (TMS) I/O23 I/O22 I/O21
Block B
I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 Block C
14051K-024
PIN DESIGNATIONS
MACH 1 & 2 Families
41
68-PIN PLCC CONNECTION DIAGRAM (MACH221-7/10/12/15)

Top View
68-Pin PLCC Block A Block H
Block B
I/O7 I/O8 I/O9 I/O10 I/O11 CLK0/I0 CLK1/I1 I2 VCC GND I3 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O6 GND I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 GND I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 I7 GND VCC I6 CLK3/I5 CLK2/I4 I/O35 I/O34 I/O33 I/O32 I/O31
Block G
Block C
Block F
GND I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCC GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 GND I/O30 Block D Block E
14051K-025
PIN DESIGNATIONS
42
MACH 1 & 2 Families
100-PIN PQFP CONNECTION DIAGRAM (MACH221SP-7/10/12/15)

Top View
100-Pin PQFP Block A Block H
GND GND TDI I7 N/C I/O6 N/C I/O7 I/O8 I/O9 I/O10 I/O11 IO/CLK0 VCC VCC GND GND I1/CLK1 I/O12 I/O13 I/O14 I/O15 I/O16 N/C I/O17 I2 N/C TCK GND GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
N/C I/O5 N/C I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND GND VCC I/O47 I/O46 I/O45 I/O44 I/O43 N/C I/O42 N/C
GND GND TDO N/C I6 I/O41 N/C I/O40 I/O39 I/O38 I/O37 I/O36 I5/CLK3 GND GND VCC VCC I4/CLK2 I/O35 I/O34 I/O33 I/O32 I/O31 N/C I/O30 N/C I3 TMS GND GND
Block B
Block C
N/C I/O18 N/C I/O19 I/O20 I/O21 I/O22 I/O23 VCC GND GND VCC I/O24 I/O25 I/O26 I/O27 I/O28 N/C I/O29 N/C
Block F
14051K-026
Block D
Block E
PIN DESIGNATIONS
I/CLK GND I I/O VCC = = = = = Input or Clock Ground Input Input/Output Supply Voltage TDI TCK TMS TDO = = = = Test Test Test Test Data In Clock Mode Select Data Out
MACH 1 & 2 Families
Block G
43
84-PIN PLCC CONNECTION DIAGRAM (MACH231-6/7/10/12/15)

Top View
84-Pin PLCC Block A Block H
I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I0 VCC GND CLK1/I1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 72 14 71 15 70 16 17 69 68 18 67 19 66 20 21 65 64 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND VCC I5 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56
GND I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3/I4 GND VCC CLK2/I3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 Block B
Block C
I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCC GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND
Block F
14051K-027
Block D
Block E
PIN DESIGNATIONS
44
MACH 1 & 2 Families
Block G
100-PIN PQFP CONNECTION DIAGRAM (MACH231SP-10/12/15)

Top View
100-Pin PQFP Block A Block H
GND GND TDI I5 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 IO/CLK0 VCC VCC GND GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 N/C TCK GND GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
GND GND TDO N/C I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND GND VCC VCC I3/CLK2 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 I2 TMS GND GND
Block C
Block F
14051K-028
Block D
Block E
PIN DESIGNATIONS
I/CLK GND I I/O VCC = = = = = Input or Clock Ground Input Input/Output Supply Voltage TDI TCK TMS TDO = = = = Test Test Test Test Data In Clock Mode Select Data Out
MACH 1 & 2 Families
Block G
Block B
45
100-PIN TQFP CONNECTION DIAGRAM (MACH231SP-10/12/15)

Top View
100-Pin TQFP Block A Block H
TDI I5 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I0/CLK0 VCC GND GND I1/CLK1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC TCK
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
GND GND NC I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND GND VCC NC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
GND TDO NC I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND VCC I3/CLK2 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 I2 TMS
Block B
Block C
GND GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 NC VCC GND GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND GND
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Block D
Block E
14051K-029
PIN DESIGNATIONS
46
MACH 1 & 2 Families
Block F
Block G
ORDERING INFORMATION
Lattice/Vantis programmable logic products are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH 131 SP -5 Y C
FAMILY TYPE MACH = Macro Array CMOS High-Density
PROGRAMMING DESIGNATOR Blank = Initial Algorithm /1 = First Revision OPERATING CONDITIONS C = Commercial (0C to +70C) I = Industrial (-40C to +85C) PACKAGE TYPE J = Plastic Leaded Chip Carrier (PLCC) V = Thin Quad Flat Pack (TQFP) Y = Plastic Quad Flat Pack (PQFP) SPEED -5 = 5.0 or 5.5 ns tPD -6 = 6.0 ns tPD -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -14 = 14 ns tPD -15 = 15 ns tPD -18 = 18 ns tPD
MACROCELL DENSITY 111 = 32 Macrocells, 32 I/Os 131 = 64 Macrocells, 64 I/Os 211 = 64 Macrocells, 32 I/Os 221 = 96 Macrocells, 48 I/Os 231 = 128 Macrocells, 64 I/Os PRODUCT DESIGNATION SP = JTAG-compatible, In-system Programmable
Valid Combinations Commercial MACH111 MACH111SP MACH131 MACH131SP MACH211 MACH211SP MACH221 MACH221SP MACH231 MACH231SP -5, -7, -10, -12, -15 -5, -7, -10, -12, -15 -5, -7, -10, -12, -15 -5, -7, -10, -12, -15 -7, -10, -12, -15 -6, -7, -10, -12, -15 -7, -10, -12, -15 -7, -10, -12, -15 -6, -7 -10, -12, -15 -10, -12, -15 JC, VC JC, VC JC/1 VC, YC JC, VC JC, VC JC YC JC JC/1 VC, YC MACH111
Valid Combinations Industrial -7, -10, -12, -14, -18 -7, -10, -12, -14, -18 -7, -10, -12, -14, -18 -7, -10, -12, -14, -18 -10, -12, -14, -18 -10, -12, -14, -18 -10, -12, -14, -18 -10, -12, -14, -18 -12, -14, -18 -12, -14, -18 JI JI JI/1 YI JI JI JI YI JI/1 YI
MACH111SP MACH131 MACH131SP MACH211 MACH211SP MACH221 MACH221SP MACH231 MACH231SP
Valid Combinations The Valid Combinations list congurations planned to be supported in volume for this device. Consult the local Lattice/ Vantis sales ofce to conrm availability of specic valid combinations and to check on newly released combinations. Note: 1. All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial grade is slower, i.e. MACH131SP-5YC-7YI
MACH 1 & 2 Families
47
48
MACH 1 & 2 Families

Mach1 2

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MACH 1 and 2 CPLD Families

High-Performance EE CMOS Programmable Logic

Publication# 14051 Amendment/0

Rev: K Issue Date: November 1998

Table 1. MACH 1 and 2 Family Device Features 1

Note: 1. Values in parentheses ( ) are for the SP version.

MACH 1 & 2 Families

Table 3. MACH 1 and 2 Family Package and I/O Options

MACH 1 & 2 Families

Figure 1. Overall Architecture of MACH 1 & 2 Devices

MACH 1 & 2 Families

Each PAL block consists of the following elements:

Product-term array Logic Allocator Macrocells I/O cells

MACH 1 & 2 Families

* To n+1 From From n+1 n+2

Figure 2. Product Term Clusters and the Logic Allocator

Table 5. Logic Allocation for MACH111(SP)

Table 6. Logic Allocation for MACH131(SP)

MACH 1 & 2 Families

Table 7. Logic Allocation for MACH211(SP) and MACH231(SP)

Table 8. Logic Allocation for MACH221(SP)

MACH 1 & 2 Families

Note: 1. Latch option available on MACH 2 devices only.

Figure 3. Output Macrocell

MACH 1 & 2 Families

From Logic Allocator

From Logic Allocator

From Logic Allocator CLK0 CLKn

From Logic Allocator CLK0 CLKn

c. D-type register, active high

d. D-type register, active low

From Logic Allocator CLK0 CLKn To Switch Matrix

From Logic Allocator CLK0 CLKn

To Switch Matrix f. T-type register, active low

e. T-type register, active high

From Logic Allocator CLK0 CLKn To Switch Matrix

From Logic Allocator CLK0

CLKn To Switch Matrix

g. Latch, active high (MACH 2 only)

h. Latch, active low (MACH 2 only)

Figure 4. Output Macrocell Congurations

MACH 1 & 2 Families

From I/O Pin 1

Figure 5. Buried Macrocell (MACH 2 only)

From Logic Allocator

Figure 6. Buried Macrocell Congurations (MACH 2 only)

MACH 1 & 2 Families

MACH 1 & 2 Families

Output Enable Product Terms (Common to bank of I/O Cells)

From Output Macrocell To Switch Matrix To Buried Macrocell (MACH 2 only)

Figure 7. I/O Cell

10.4 ns Non-MACH 7.4 ns MACH 1 & 2

Figure 8. Timing in MACH 1 & 2 vs. Non-MACH Devices

MACH 1 & 2 Families

MACH 1 & 2 Families

MACH 1 & 2 Families

MACH111(SP) AND MACH131(SP) PAL BLOCK

Output Macro Cell

Output Macro Cell

Output Macro Cell

Output Macro Cell

Output Macro Cell