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Spartan-6 FPGA Packaging and Pinouts

Product Specification

UG385 (v2.2) August 24, 2011

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps. Copyright 20092011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

Revision History
The following table shows the revision history for this document.
Date 06/24/09 12/08/09 Version 1.0 1.1 Initial Xilinx release. Revised User I/O and Differential Pair numbers in Table 1-4. Updated descriptions of SUSPEND, CMPCS_B_2, VFS, and RFUSE. Added data for the LX4 and LX75/LX75T devices and CPG196, FG(G)900, and CSG484 packages along with a complete revamping of Chapter 2, Pinout Tables and Chapter 3, Pinout and I/O Bank Diagrams including the LX45 in the FG(G)676 package. Added Figure 4-2, the mechanical drawing for the CPG196 package. Revised Figure 4-1, Figure 4-3, and Figure 4-5. Added values to Table 5-1, page 342. 02/22/10 1.2 Added Table 1-5, page 15. In Table 1-6, updated the LDC, HDC, SCPn, VBATT, VFS, and RFUSE descriptions. Added Spartan-6 FPGA Banks, GTP Transceiver Locations, Clock Inputs and BUFIO2 Clocking Regions, and Supply Voltages for I/O and Configuration Pins. Revised all the pinout tables in Chapter 2 to add the BUFIO2 clocking regions. Changed the CSG225 PackageLX4 discussion. Added a note to Figure 3-37 and updated Figure 3-65. Added MDDS and PCB design reference notes to Chapter 4. Added values to Table 5-1. Changed the package marking in Figure 6-1. Also updated descriptions in Table 6-1 for engineering samples and L1C. Added a new chapter: Chapter 7, Density Migration. Revision

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UG385 (v2.2) August 24, 2011

Date 10/12/10

Version 1.3

Revision In Table 1-6, revised description for IO_LXXY_ZZZ_#, Dn, VFS, RFUSE and added notes 1 and 2. Edited Clock Inputs and BUFIO2 Clocking Regions. In Table 2-3, revised the BUFIO2 regions for bank 3 pins D3, D4, E1, E2, F1, F2, F3, F4,H1, and H2. In Table 2-5, revised the BUFIO2 regions for bank 3 pins H1, K4, J3, G2, G1, K5, J4, F1, F3, J5, H4, G5, G3, H6, H5, F5, F4, E5, and E4. In Table 2-6, revised the BUFIO2 regions for bank 3 pins H13, H14, J11, J12, J13, K14, J6, H5, H4, H3, L4, and L5 to add separate information for the LX25 devices. In Table 2-7, revised the BUFIO2 regions for bank 1 pins C17, C18, F14, G14, D17, D18, H12, G13, E16, E18, K12, K13, F17, F18, H13, H14, H15, H16, G16, and G18, and to also add separate information for the LX25 device to bank 1 pins J13, K14, L12, L13, K15, and K16. Revised the BUFIO2 regions for bank 2 pins R15, T15, U16, V16, R13, T13, U15, V15, T14, V14, N12, P12, U13, V13, M11, N11, R11, T11, T12, V12, N10, P11, N9, U11, V11, R10, T10, U10, and V10. Revised the BUFIO2 regions for bank 3 pins N4, N3, P4, P3, L6, M5, U2, U1, T2, T1, P2, P1, N2, N1, M3, M1, L2, L1, K2, K1, L4, L3, J3, J1, H2, H1, K4, and K3, and to also add separate information for the LX25 device to bank 3 pins L5, K5, H4, H3, L7, and K6. In Table 2-8, revised the BUFIO2 regions for bank 1 pins C17, C18, F14, G14, D17, D18, H12, G13, E16, E18, K12, K13, F17, F18, H13, H14, H15, H16, G16, and G18, and to also add separate information for the LX25T device to bank 1 pins J13, K14, L12, L13, K15, and K16. Revised the BUFIO2 regions for bank 2 pins R15, T15, U16, V16, R13, T13, U15, V15, T14, V14, N12, P12, U13, V13, M11, N11, R11, T11, T12, V12, N10, P11, N9, U11, V11, R10, T10, U10, and V10. Revised the BUFIO2 regions for bank 3 pins N4, N3, P4, P3, L6, M5, U2, U1, T2, T1, P2, P1, N2, N1, M3, M1, L2, L1, K2, K1, L4, L3, J3, J1, H2, H1, K4, and K3, and to also add separate information for the LX25 device to bank 3 pins L5, K5, H4, H3, L7, and K6. In Table 2-9, revised the BUFIO2 regions to add separate information for the LX75 device to bank 0 pins E12, D12, F13, D13. Revised the BUFIO2 regions to add separate information for the LX25 device to bank 1 pins G20, G22, K20, K9, H21, H22. Revised the BUFIO2 regions to add separate information for the LX25 device to bank 3 pins K5, K4, K3, J4, K5, J6. In Table 2-10, revised the BUFIO2 regions to add separate information for the LX25T device to bank 0 pins J20, J22, M20, M19, K21, and K22. In Table 2-13, revised the BUFIO2 regions for bank 1 pins N25, N26, L19, K19, L23, L24, P20, N21, M23, N24, L17, K18, P24, P26, M19, L18, R25, R26, M18, N19, N22, N23, N17, N18, R23, R24, N20, M21, P21, and P22. Revised the BUFIO2 regions for bank 2 pins AD22, AF22, AE21, AF21, AD20, AF20, AE19, AF19, AC20, AD21, Y18, AA19, AC19, AD19, V16, W17, AD18, AF18, Y16, AA17, AA18, AB18, AE17, AF17, AD16, AF16, AE15, AF15, AB17, AC17, AC15, AD15, AC16, AD17, V15, W16, AB15, AC14, Y15, AA15, Y14, AA14, AD14, AF14, AE13, AF13. Revised the BUFIO2 regions for bank 3 pins AC7, AD7, AE3, AF2, AC4, AD4, AA7, Y6, AB7, AB6, AC5, AD5, AA5,AB5, W8, W7, AB4, AC3, AA4, AA3, W5, Y5, U8, U7, U5, V5, U4, U3, T8, T6, R5, T4, R7, R6, AB3, AB1, AD3,AD1, AC2, AC1, AE2, AE1, AA2, AA1, Y3, Y1, W2, W1, V3, V1, U2, U1, T3, T1, V4, and W3. In Table 5-1, added and updated values. Updated Chapter 6 to add more information about the various packages offered for Spartan-6 FPGAs. Added LX25 and LX25T Migration in Chapter 7.

02/24/11

2.0

Revised the notation for the Ag content in Figure 4-4: FT(G)256 Fine-Pitch Thin BGA Package. Updated LX25 and LX25T Migration in Chapter 7.

UG385 (v2.2) August 24, 2011

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Spartan-6 FPGA Packaging

Date 06/07/11

Version 2.1

Revision Updated document descriptions in Additional Documentation. Added reference to Spartan-6 FPGA PCB Design and Pin Planning Guide in Introduction. Added reference to Spartan-6 FPGA SelectIO Resources User Guide to text preceding Table 1-4. Added reference to Spartan-6 FPGA SelectIO Resources User Guide to Table 1-6. Revised the tolerances for package type FG(G)676, symbol A in Figure 4-7. Added reference to Spartan-6 FPGA PCB Design and Pin Planning Guide in Chapter 4, Summary. Added reference to Spartan-6 FPGA PCB Design and Pin Planning Guide in Chapter 7, Introduction. Updated the entire document to add the Defense-grade Spartan-6Q and XA Spartan-6 Automotive FPGAs. Added the CS484 package, where applicable, throughout the guide. Added Soldering Guidelines in Chapter 5.

08/24/11

2.2

Spartan-6 FPGA Packaging

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UG385 (v2.2) August 24, 2011

Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Preface: About This Guide


Organization of This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 1: Packaging Overview


Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pb-free Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device/Package Combinations and Maximum I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan-6 FPGA Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Spartan-6 FPGA I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan-6 LXT FPGA GTP Transceiver Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan-6 FPGA Bank Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GTP Transceiver Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 12 12 17 21 21 21 22 25

Clock Inputs and BUFIO2 Clocking Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Supply Voltages for I/O and Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Chapter 2: Pinout Tables


Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TQG144 PackageLX4 and LX9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 CPG196 PackageLX4, LX9, and LX16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 CSG225 PackageLX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CSG225 PackageLX9 and LX16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 FT(G)256 PackageLX9, LX16, and LX25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 CSG324 PackageLX9, LX16, LX25, and LX45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 CSG324 PackageLX25T and LX45T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150. . . . . . . . . . . . . . . . . . . . . 87 FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T . . . . . . . . . . . . 103 CS(G)484 PackageLX45, LX75, LX100, and LX150 . . . . . . . . . . . . . . . . . . . . . . . . . . 119 CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T . . . . . . . . . . . . . . . . . . . . 135 FG(G)676 PackageLX45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 FG(G)676 PackageLX75, LX100, and LX150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 FG(G)676 PackageLX75T, LX100T, and LX150T . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 FG(G)900 PackageLX150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 FG(G)900 PackageLX100T and LX150T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

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Chapter 3: Pinout and I/O Bank Diagrams


Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TQG144 PackageLX4 and LX9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPG196 PackageLX4, LX9, and LX16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSG225 PackageLX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSG225 PackageLX9 and LX16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FT(G)256 PackageLX9, LX16, and LX25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSG324 PackageLX9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSG324 PackageLX16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSG324 PackageLX25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSG324 PackageLX25T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSG324 PackageLX45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSG324 PackageLX45T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)484 PackageLX25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)484 PackageLX25T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)484 PackageLX45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)484 PackageLX75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)484 PackageLX75T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)484 PackageLX100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)484 PackageLX150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)484 PackageLX45T, LX100T, and LX150T . . . . . . . . . . . . . . . . . . . . . . . . . . . CSG484 PackageLX45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CS(G)484 PackageLX75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CS(G)484 PackageLX100 and LX150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CS(G)484 PackageLX75T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CS(G)484 PackageLX45T, LX100T, and LX150T . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)676 PackageLX45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)676 PackageLX75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)676 PackageLX75T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)676 PackageLX100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)676 PackageLX100T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)676 PackageLX150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)676 PackageLX150T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)900 PackageLX100T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)900 PackageLX150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FG(G)900 PackageLX150T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
271 272 274 275 276 277 278 279 280 281 282 283 284 286 288 290 292 294 296 298 300 302 304 306 308 310 312 314 316 318 320 322 324 326 328

Chapter 4: Mechanical Drawings


Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TQG144 Thin Quad Flat-Pack Package Specifications (0.5 mm Pitch) . . . . . . . . CPG196 Chip-Scale BGA Package Specifications (0.5 mm Pitch) . . . . . . . . . . . . . CSG225 Chip-Scale BGA Package Specifications (0.8 mm Pitch) . . . . . . . . . . . . . FT(G)256 Fine-Pitch Thin BGA Package Specifications (1.00 mm Pitch) . . . . . .
331 332 333 334 335

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG324 Chip-Scale BGA Package Specifications (0.8 mm Pitch) . . . . . . . . . . . . . FG(G)484 Fine-Pitch BGA Package Specifications (1.00 mm Pitch) . . . . . . . . . . . CS(G)484 Chip-Scale BGA Package Specifications (0.8 mm Pitch) . . . . . . . . . . . FG(G)676 Fine-Pitch BGA Package Specifications (1.00 mm Pitch) . . . . . . . . . . . FG(G)900 Chip-Scale BGA Package Specifications (1.00 mm Pitch) . . . . . . . . . .

336 337 338 339 340

Chapter 5: Thermal Specifications


Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 Package Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Cavity-Up Plastic BGA Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key Features/Advantages of Cavity-Up BGA Packages . . . . . . . . . . . . . . . . . . . . . . . Chip Scale Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key Features/Advantages of CSP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 344 344 344 345

Support for Compact Thermal Models (CTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 Soldering Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Sn/Pb Reflow Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 Notes for Figure 5-4: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 Pb-Free Reflow Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

Chapter 6: Package Marking Chapter 7: Density Migration


Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Connects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCBs and Parallel Configuration in the LX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GTP Transceiver Connections in the LX25T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Encryption Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCBs and I/O Banks in the FG(G)676 and FG(G)900 . . . . . . . . . . . . . . . . . . . . . . . . . GTP Transceiver Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LX25 and LX25T Migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Names and Physical Pad Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Migrating Between Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 353 354 356 356 356 357 357 358 358 358 358

PlanAhead Software Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

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Preface

About This Guide


This guide describes Spartan-6 device pinouts and package specifications; it also includes pinout diagrams and thermal data.

Organization of This Guide


This document is comprised of the following chapters: Chapter 1, Packaging Overview Provides an introduction to the Spartan-6 family with a summary of maximum I/Os available in each device/package combination. Also includes table of pin definitions. Chapter 2, Pinout Tables Provides pinout information for all Spartan-6 devices and packages. Chapter 3, Pinout and I/O Bank Diagrams Provides pinout diagrams for all Spartan-6 FPGA package/device combinations. Chapter 4, Mechanical Drawings Provides mechanical drawings of Spartan-6 FPGA packages. Chapter 5, Thermal Specifications Provides thermal data associated with Spartan-6 FPGA packages. Discusses Spartan-6 FPGA power management strategy and thermal management options. Chapter 6, Package Marking Provides example and description of the marking on top of the package (topmark). Chapter 7, Density Migration The guidelines in this chapter facilitate migration of designs between different Spartan-6 device/package combinations.

Additional Documentation
A complete suite of documentation is available for the commercial (XC) Spartan-6 FPGAs at: http://www.xilinx.com/support/documentation/spartan-6.htm. Additional specific documentation for the Defense-grade Spartan-6Q FPGAs (XQ) is available at: http://www.xilinx.com/support/documentation/spartan-6q.htm. Additional specific documentation for the XA Spartan-6 Automotive FPGAs is available at: http://www.xilinx.com/support/documentation/automotive_xa_devices.htm.

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Preface: About This Guide

Additional Support Resources


To search the database of silicon and software questions and answers, or to create a technical support case in WebCase, visit the following Xilinx website: http://www.xilinx.com/support

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Chapter 1

Packaging Overview
Summary
This chapter covers the following topics: Introduction Pb-free Packaging Device/Package Combinations and Maximum I/Os Pin Definitions Spartan-6 FPGA Banks Clock Inputs and BUFIO2 Clocking Regions Supply Voltages for I/O and Configuration Pins

Introduction
This section describes the pinouts for Spartan-6 devices in various packages. Spartan-6 devices are offered in low-cost, space-saving packages that are optimally designed for the maximum number of user I/Os. Package inductance is minimized as a result of optimal placement and even distribution as well as an increased number of Power and GND pins. All of the Spartan-6 LX devices supported in a particular package are pinout compatible. All of the Spartan-6 LXT devices supported in a particular package are pinout compatible. The Spartan-6 LX devices are not pin compatible with the Spartan-6 LXT devices. Pins that are not available in some of the devices are listed in the No Connects column of each table. Each device is split into I/O banks to allow for flexibility in the choice of I/O standards (see UG381, Spartan-6 FPGA SelectIO Resources User Guide). Global pins and power/ground pins, are listed at the end of each table. Table 1-6 provides definitions for all pin types. See UG393, Spartan-6 FPGA PCB Design and Pin Planning Guide for recommendations for board layout, PCB design rules, and pin planning.

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Chapter 1: Packaging Overview

Pb-free Packaging
Xilinx offers lead-free devices (Pb-free) that comply with the European Unions RoHS directive (2002/95/EC). Information on the material composition of our Pb-free, RoHS compliant FPGAs is available as either material declaration data sheets or IPC 1752 forms, at http://www.xilinx.com/support/documentation/spartan-6.htm#131532. For more information on Pb-free packaging, see www.xilinx.com/pbfree. The Pb-free packages include an extra G in the package code. For example, FTG256 is the Pb-free version of the FT256 package. When referenced together, the G is incorporated as FT(G)256. The Pb and Pb-free packages are identical in pin-out, size, and thermal characteristics.

Device/Package Combinations and Maximum I/Os


Table 1-1 shows the package specifications and the maximum number of user I/Os possible in Spartan-6 FPGA packages. Specific information on device/package combinations by family is available at: Table 1-1: DS160: Spartan-6 Family Overview DS170: XA Spartan-6 Automotive Family Overview DS172: Defense-grade Spartan-6Q Family Overview

Spartan-6 FPGA Packages


Packages TQG144(1) CPG196 CSG225 FT(G)256(2) CSG324 FG(G)484(2) CS(G)484(2) FG(G)676(2) FG(G)900(2)

Package Quad Flat Type Pack Pitch (mm) 0.5

Chip Scale 0.5 8x8 106

Chip Scale 0.8 13 x 13 160

BGA 1.00 17 x 17 186

Chip Scale 0.8 15 x 15 232

BGA 1.00 23 x 23 338

Chip Scale 0.8 19 x 19 338

BGA 1.00 27 x 27 498

BGA 1.00 31 x 31 576

Size (mm) 22 x 22(1) Maximum I/Os


Notes:

102

1. The footprint for the TQG144 package (22 x 22 mm) is larger than the package body (20 x 20 mm). 2. These devices are available in both Pb and Pb-free (additional G) packages as standard ordering options. See the specific family overview for more information on packages offered by density.

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Device/Package Combinations and Maximum I/Os

The number of I/Os per package includes all user I/Os except the dedicated pins listed in Table 1-2 and the GTP serial transceiver I/O channels for the devices listed in Table 1-3. Table 1-2: Spartan-6 FPGA Dedicated Configuration Pins
PROGRAM_B_2 CMPCS_B_2 TDI TDO TMS TCK VFS(1) RFUSE(1) VBATT(1)

SUSPEND DONE_2
Notes:

1. Only available in LX75, LX75T, LX100, LX100T, LX150, and LX150T devices.

Table 1-3:

Number of Serial Transceivers (GTs) I/O Channels/Device


Device

I/O Channels LX25T MGTRXP MGTRXN MGTTXP MGTTXN


Notes: 2 2 2 2

LX45T
4 4 4 4

LX75T(1) 4 or 8 4 or 8 4 or 8 4 or 8

LX100T(2)
4 or 8 4 or 8 4 or 8 4 or 8

LX150T(2)
4 or 8 4 or 8 4 or 8 4 or 8

1. The LX75T has 4 GTP I/O channels in the FG(G)484 and CS(G)484 packages and 8 GTP I/O channels in the FG(G)676 package. 2. The LX100T and the LX150T have 4 GTP I/O channels in the FG(G)484 and CS(G)484 packages and 8 GTP I/O channels in the FG(G)676 and FG(G)900 packages.

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Chapter 1: Packaging Overview

Table 1-4 shows the number of available I/Os and the number of differential pairs for each Spartan-6 FPGA device/package combination. Not all I/O standards can be used on all pins. For example, for many differential standards, the outputs are only available in banks 0 and 2. For information on banking rules, see UG381, Spartan-6 FPGA SelectIO Resources User Guide. Table 1-4:
Spartan-6 Device

Available I/O Pin/Device/Package Combinations


Spartan-6 FPGA Package
User I/O Pins TQG144 CPG196 CSG225 FT(G)256 CSG324 FG(G)484 CS(G)484 FG(G)676 FG(G)900
Available User I/Os

LX4
Differential Pairs Available User I/Os

102 51 102 51

106 53 106 53 106 53


132 66 160 80 160 80


LX9
Differential Pairs Available User I/Os

186 93 186 93 186 93


200 100 232 116 226 113 218 109


LX16
Differential Pairs Available User I/Os

LX25
Differential Pairs Available User I/Os

266 133 316 158 280 140 326 163 338 169 250 125 296 148 268 134 296 148 296 148

LX45
Differential Pairs Available User I/Os

320 160 328 164 338 169 338 169


358 179 408 204 480 240 498 249


LX75
Differential Pairs Available User I/Os

LX100
Differential Pairs Available User I/Os

LX150
Differential Pairs Available User I/Os

576 288

LX25T
Differential Pairs Available User I/Os

190 95 190 95

LX45T
Differential Pairs Available User I/Os

296 148 292 146 296 148 296 148

LX75T
Differential Pairs Available User I/Os

348 174 376 188 396 198

LX100T
Differential Pairs Available User I/Os

498 249 540 270

LX150T
Differential Pairs

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Device/Package Combinations and Maximum I/Os

Table 1-5 shows the number of I/O available per bank for each Spartan-6 FPGA device/package combination. Bank diagram are shown in Chapter 3. For information on banking rules, see UG381, Spartan-6 FPGA SelectIO Resources User Guide. Table 1-5:
Package TQG144

Number of I/Os per Bank for Each Device/Package Combination


Device LX4 LX9 LX4 Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total I/O 26 26 26 26 26 34 40 40 40 40 40 44 60 54 46 18 18 46 56 56 56 40 40 40 40 24 24 26 26 26 32 40 40 54 54 54 56 56 56 56 56 56 112 112 112 112 98 98 98 98 26 26 28 28 28 34 38 38 38 38 38 44 60 60 60 60 60 58 52 62 62 52 48 52 52 26 26 26 26 26 32 42 42 54 54 54 56 56 56 56 56 56 104 108 108 108 106 106 106 106 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 102 102 106 106 106 132 160 160 186 186 186 200 232 226 218 190 190 320 328 338 338 296 292 296 296

CPG196

LX9 LX16 LX4

CSG225

LX9 LX16 LX9

FT(G)256

LX16 LX25 LX9 LX16

CSG324

LX25 LX45 LX25T LX45T LX45 LX75 LX100

CS(G)484

LX150 LX45T LX75T LX100T LX150T

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Chapter 1: Packaging Overview

Table 1-5:
Package

Number of I/Os per Bank for Each Device/Package Combination (Contd)


Device LX25 LX45 LX75 LX100 Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total I/O 58 46 56 68 68 46 46 46 46 46 46 56 92 110 56 70 80 132 92 114 64 82 82 82 82 64 82 82 82 82 112 92 92 92 62 62 62 94 94 94 80 100 54 88 100 76 82 54 82 82 88 56 92 92 56 70 80 130 92 112 64 88 88 88 88 64 86 86 86 86 112 98 98 98 68 68 68 114 114 114 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 52 52 52 52 52 52 52 52 52 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 54 54 54 54 54 54 54 54 54 266 316 280 326 338 250 296 268 296 296 358 408 480 498 348 376 396 576 498 540

FG(G)484

LX150 LX25T LX45T LX75T LX100T LX150T LX45 LX75 LX100

FG(G)676

LX150 LX75T LX100T LX150T LX150

FG(G)900

LX100T LX150T

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Pin Definitions

Pin Definitions
Table 1-6 lists the pin definitions used in Spartan-6 FPGA packages. Further details on pin functionality is available in the device user guides: http://www.xilinx.com/support/documentation/spartan-6.htm. Table 1-6: Spartan-6 FPGA Pin Definitions
Direction Description

Pin Name User I/O Pins

All user I/O pins are capable of differential signaling and can implement pairs(1). Each user I/O is labeled IO_LXXY_#, where: IO_LXXY_# Input/ Output IO indicates a user I/O pin. LXXY indicates a differential pair, with XX a unique pair in the bank and Y = [P|N] for the positive/negative sides of the differential pair. # indicates the bank number. Multi-Function Pins Multi-function pins are labelled IO_LXXY_ZZZ_#, where ZZZ represents one or more of the following functions in addition to being general purpose user I/O. When not used for their special function, these pins can be user I/O. In SelectMAP/BPI modes, D0 through D15 are configuration data pins. Input/ During slave SelectMAP readback, the pins become outputs when Output RDWR_B = 1. These pins become user I/Os after configuration, unless (during readback) the SelectMAP port is retained. In Parallel (SelectMAP and BPI) modes, D0 is the LSB of the data bus. In Bit-serial modes, DIN is the single-data input. In SPI mode, MISO is the Master Input/Slave Output. In SPI x2 or x4 modes, MISO1 is the second bit of the SPI bus. In Parallel modes, D1 and D2 are lower-order bits of the data bus. In SPI x4 mode, MISO2 and MISO3 are two MSBs of the SPI bus. Address A0A25 BPI address output. These pins become user I/O after configuration. Status output pin for the power-saving Suspend mode. SUSPEND is a dedicated pin and AWAKE is a multi-function pin. Unless Suspend mode is enabled in the application, AWAKE is available as user I/O. In SPI modes, Master Output/Slave Input (MOSI) connects from the FPGA to the SPI flash slave data input to send read commands and starting addresses. In SelectMAP mode, CSI_B is the active-low chipselect signal. In SPI x2 or x4 modes, MISO0 is the first bit of the SPI bus. BPI flash chip select. BPI flash output enable. BPI flash write enable. Low during configuration in BPI mode.

IO_LXXY_ZZZ_#

Dn

D0_DIN_MISO_MISO1 Input

D1_MISO2, D2_MISO3 An AWAKE

Input Output

Output MOSI_CSI_B_MISO0 Input/ Output

FCS_B FOE_B FWE_B LDC

Output Output Output Output

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Table 1-6:

Spartan-6 FPGA Pin Definitions (Contd)


Direction Output Output Description High during configuration in BPI mode. In Parallel modes, parallel daisy-chain chip select. In SPI mode, SPI flash chip select. Used with LogiCORE IP for PCI designs. An instantiation of the Xilinx core requires the use of either IRDY1 and TRDY1 or IRDY2 and TRDY2. See the core documentation for more details. These pins are available as user I/O when not being used for PCI designs. In SelectMAP mode, BUSY indicates the device status. Output In Bit-serial modes, DOUT gives configuration data to down-stream devices in a daisy chain. In SelectMAP mode, this is the active-low write-enable signal. After configuration and if needed, RDWR_B can become a VREF in bank 2. When Low, enables I/O pullups before and during configuration. When Low, this pin indicates that the configuration memory is being cleared. When held Low, the start of configuration is delayed. During configuration, a Low on this output indicates that a configuration data error has occurred. Can be used after configuration (optional) to indicate POST_CRC status. Suspend control pins SCP0-SCP7. Used for SUSPEND multi-pin wakeup feature. Reserved for future use. Use these pins as general-purpose I/O. N/A Configuration mode selection. M0 = Parallel (Low) or Serial (High). M1 = Master (Low) or Slave (High). Configuration clock. Output in Master mode or input in Slave mode. Optional user configuration clock input in Master modes. These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for clocks. These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed (per bank). When used as a reference voltage within a bank, all VREF pins within that bank must be connected.

Pin Name HDC CSO_B IRDY1/2, TRDY1/2

Output

DOUT_BUSY

RDWR_B_VREF HSWAPEN INIT_B

Input Input

Bidirectional (open-drain)

SCPn CMPMOSI, CMPMISO, CMPCLK M0, M1 CCLK USERCCLK GCLK VREF_#

Input

Input Input/ Output Input Input

N/A

Multi-Function Memory Controller Pins(2) M#DQn M#LDQS M#LDQSN Input/ Output Input/ Output Input/ Output Memory controller data D[0:15] in bank #. Memory controller lower data strobe in bank #. Memory controller lower data strobe N in bank #.

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Pin Definitions

Table 1-6:

Spartan-6 FPGA Pin Definitions (Contd)


Direction Input/ Output Input/ Output Output Output Output Output Output Output Output Output Output Output Output Output Description Memory controller upper data strobe in bank #. Memory controller upper data strobe N in bank #. Memory controller address A[0:14] in bank #. Memory controller bank address BA[0:2] in bank #. Memory controller lower data mask in bank #. Memory controller upper data mask in bank #. Memory controller clock in bank #. Memory controller active-Low clock in bank #. Memory controller active-Low column address strobe in bank #. Memory controller active-Low row address strobe in bank #. Memory controller on-die termination control for external memory in bank #. Memory controller write enable in bank #. Memory controller clock enable in bank #. Memory controller reset in bank #.

Pin Name M#UDQS M#UDQSN M#An M#BAn M#LDM M#UDM M#CLK M#CLKN M#CASN M#RASN M#ODT M#WE M#CKE M#RESET Dedicated Pins(3)

DONE_2

Input/ Output

DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, this pin indicates completion of the configuration process. As an input, a Low level on DONE can be configured to delay the startup sequence. Active-Low asynchronous reset to configuration logic. This pin has a default weak pull-up resistor. Active-High control input pin for the power-saving Suspend mode. SUSPEND is a dedicated pin and AWAKE is a multi-function pin. Must be enabled by configuration option. When Suspend mode is not used, connect this pin to GND. JTAG Boundary-scan clock. JTAG Boundary-scan data input. JTAG Boundary-scan data output. JTAG Boundary-scan mode select.

PROGRAM_B_2

Input

SUSPEND

Input

TCK TDI TDO TMS

Input Input Output Input

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Table 1-6:

Spartan-6 FPGA Pin Definitions (Contd)


Direction Description

Pin Name Reserved Pins

NC

N/A

When found in a table or text file, an NC indicates that this pin is not connected in the specific device/package combination. However, in some devices in the same package, another pin name is used to describe this pin. Reserved. Leave unconnected or connect High (VCCO_2).

CMPCS_B_2 Other Pins GND

Input

N/A

Ground. Decryptor key RAM memory backup supply. Once VCCAUX is applied, VBATT can be unconnected. If key RAM is not used, connecting VBATT to VCCAUX or GND is recommended, or the pin can be left unconnected. Only available in the LX75, LX75T, LX100, LX100T, LX150, and LX150T devices. Power-supply pins for auxiliary circuits. Power-supply pins for the internal core logic. Power-supply pins for the output drivers (per bank). Decryptor key EFUSE power supply pin for programming. When not programming, tie this pin to a voltage between GND and 3.45V. When not using the key EFUSE, the recommendation is to connect VFS to VCCAUX or GND, however, the pin can be left unconnected. Only available in the LX75, LX75T, LX100, LX100T, LX150, and LX150T devices. Decryptor key EFUSE resistor to GND for programming. When not programming or when not using the key EFUSE, connecting RFUSE to VCCAUX or GND is recommended, however, the pin can be left unconnected. Only available in the LX75, LX75T, LX100, LX100T, LX150, and LX150T devices.

VBATT

N/A

VCCAUX VCCINT VCCO_#

N/A N/A N/A

VFS

Input

RFUSE

Input

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Spartan-6 FPGA Banks

Table 1-6:

Spartan-6 FPGA Pin Definitions (Contd)


Direction Description

Pin Name

GTP Transceiver Pins (GTPA1_DUAL Primitive)(4) MGTAVCC MGTAVTTTX, MGTAVTTRX MGTAVTTRCAL MGTAVCCPLL0 MGTAVCCPLL1 MGTREFCLK0/1P MGTREFCLK0/1N MGTRREF MGTRXP[0:1] MGTRXN[0:1] MGTTXP[0:1] MGTTXN[0:1]
Notes:
1. 2. 3. 4. See banking rules in UG381: Spartan-6 FPGA SelectIO Resources User Guide. For further information, see UG388: Spartan-6 FPGA Memory Controller User Guide. Dedicated pins without a bank number (JTAG and SUSPEND) are powered by VCCAUX. For further information, see UG386: Spartan-6 FPGA GTP Transceivers User Guide.

N/A N/A N/A N/A Input Input Input Input Input Output Output

Power-supply pin for transceiver mixed-signal circuitry. Power-supply pin for TX and RX circuitry.

Power-supply pin for the resistor calibration circuit. Power-supply pin for PLL. Positive differential reference clock. Negative differential reference clock. Precision reference resistor pin for internal calibration termination. Positive differential receive port. Negative differential receive port. Positive differential transmit port. Negative differential transmit port.

Spartan-6 FPGA Banks


Bank designations at the end of each pin name indicate the bank number for that pin. There are both I/O banks and GTP transceiver banks in the Spartan-6 family.

Spartan-6 FPGA I/O Banks


Each Spartan-6 device contains either four or six I/O banks depending on device size and package. Each bank varies in the number of available and bonded I/O, with as few as 18 and as many as 114 I/O available in one bank. LX45/LX45T and smaller and all devices in the CS(G)484 and FG(G)484 packages have four I/O banks, one on each side of the device. LX75/LX75T and larger in the FG(G)676 and FG(G)900 packages have two I/O banks on the left and right sides for a total of six I/O banks.

Spartan-6 LXT FPGA GTP Transceiver Banks


There are from one to four GTPA1_DUAL tiles in each Spartan-6 LXT device. Each GTPA1_DUAL tile has its own power supplies and bank designation. GTP transceiver banks 101 and 123 are embedded in I/O bank 0, and GTP transceiver banks 245 and 267 are embedded in I/O bank 2.

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Spartan-6 FPGA Bank Information


Table 1-7 shows the bank names and locations. Not all banks are available in every device/package combination. Table 1-7:
Bank 0 1 2 3 4 5 101 123 245 267

Spartan-6 FPGA Bank Numbering


Locations Description All devices All devices All devices; contains most configuration pins All devices Extra bank in LX75/LX75T, LX100/LX100T, LX150/LX150T in FG(G)676 and FG(G)900 packages Extra bank in LX75/LX75T, LX100/LX100T, LX150/LX150T in FG(G)676 and FG(G)900 packages GTP transceiver bank in all LXT devices GTP transceiver bank in LX45T, LX75T, LX100T, LX150T GTP transceiver bank in LX75T, LX100T, LX150T in FG(G)676 and FG(G)900 packages GTP transceiver bank in LX75T, LX100T, LX150T in FG(G)676 and FG(G)900 packages

Top Right Bottom Left Left, Top Right, Top Top, Left Top, Right Bottom, Left Bottom, Right

Figure 1-1 through Figure 1-5 visually describe a device view of the FPGA bank numbering.
X-Ref Target - Figure 1-1

BANK 0

BANK 3

BANK 1

BANK 2
UG385_c1_01_012810

Figure 1-1: I/O Banks for All LX4, LX9, LX16, LX25, and LX45 Devices and for the LX75, LX100 and LX150 Devices in the CS(G)484 and FG(G)484 Packages

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Spartan-6 FPGA Banks

X-Ref Target - Figure 1-2

BANK 0 BANK 4 BANK 5

BANK 3 BANK 2

BANK 1

UG385_c1_02_020910

Figure 1-2: I/O Banks for LX75, LX100, and LX150 Devices in the FG(G)676 and FG(G)900 Packages
X-Ref Target - Figure 1-3

BANK 0

BANK 101

BANK 0

BANK 3

BANK 1

BANK 2
UG385_c1_03_012810

Figure 1-3:

I/O and GTP Banks for All LX25T Devices

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Chapter 1: Packaging Overview

X-Ref Target - Figure 1-4

BANK 0

BANK 101 BANK 0

BANK 123

BANK 0

BANK 3

BANK 1

BANK 2
UG385_c1_04_012810

Figure 1-4:

I/O and GTP Banks for LX45T, LX75T, LX100T, and LX150T Devices in the CSG324, FG(G)484, and CS(G)484 Packages

X-Ref Target - Figure 1-5

BANK 0

BANK 101 BANK 0

BANK 123

BANK 0

BANK 4

BANK 5

BANK 3

BANK 1

BANK 2

BANK 245

BANK 2

BANK 267

BANK 2
UG385_c1_05_020910

Figure 1-5:

I/O and GTP Banks for LX75T, LX100T, and LX150T Devices in the FG(G)676 and FG(G)900 Packages

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Clock Inputs and BUFIO2 Clocking Regions

GTP Transceiver Locations


The position of GTPA1_DUAL tiles is specified by an XY coordinate system (where X = column, Y = row) for location constraints. The Spartan-6 LX25T and LX45T devices have all the GTP transceivers located in a row along the top of the device. For these devices with only a top row, the value of the Y coordinate is always 0. The LX75T, LX100T, and LX150T devices have one GTP transceiver row at the top and one GTP transceiver row at the bottom of the device. For these devices, the value of the Y coordinate of the bottom row is 0, and for the top row is 1. Table 1-8 shows the association between GTP transceiver locations and GTP transceiver I/O banks. See UG386, Spartan-6 FPGA GTP Transceivers User Guide for more information. Table 1-8: GTP Transceiver Bank to GTP Transceiver Location
GTP Transceiver Bank Number GTP Transceiver Location 101 X0Y0 X0Y1 X1Y0 X1Y1 X0Y0 X1Y0

Devices LX25T, LX45T LX75T, LX100T, LX150T LX45T LX75T, LX100T, LX150T LX75T, LX100T, LX150T LX75T, LX100T, LX150T

123 245 267

Clock Inputs and BUFIO2 Clocking Regions


Banks 0, 1, 2, and 3 each contain eight GCLK input pins, providing a total of 32 dualpurpose pins for use as clock inputs. The CPG196 package connects only four of the eight clock inputs in bank 2. Global clock (GCLK) input pins can connect directly to the global clock buffers (BUFGs), to the BUFIO2 and then to local I/O clocking, or to the BUFIO2 and then to DCMs and PLLs. Each Spartan-6 device has 16 BUFGs. Each BUFG can be driven by one of two GCLK pins. When driving a global clock buffer directly with a global clock input, the global clock inputs from banks 0 and 1 share the same eight BUFGs. Similarly, banks 2 and 3 share eight BUFGs. There are four high-speed I/O clocks in every half-edge of the device, driven by four dedicated BUFIO2 buffers. Each side of the device has two separated I/O clock regions. These BUFIO2 clocking regions are noted in the pinout tables in Chapter 2. For example, TL indicates that the I/O is driven by the BUFIO2 clocking region in the left half of the top edge (bank 0) of the device. It is possible to span an entire bank with a single I/O clock input that is connected to the BUFIO2 buffers on both sides. For further details on global and I/O clocks, see UG382, Spartan-6 FPGA Clocking Resources User Guide.

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Chapter 1: Packaging Overview

Supply Voltages for I/O and Configuration Pins


Output buffers within a given I/O bank (banks 0 through 5) must share the same output drive source voltage, VCCO. The dedicated DONE and PROGRAM_B configuration pins are in bank 2. The other dedicated configuration pins are powered by VCCAUX. Dual-purpose configuration pins are powered by the VCCO of the bank in which they are located. For more details on configuration pins, see UG380, Spartan-6 FPGA Configuration User Guide.

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Chapter 2

Pinout Tables
Summary
This chapter includes the pinout information tables for the packages cross-referenced by device in Table 2-1. The ASCII text files of each device/package combination are available at http://www.xilinx.com/support/packagefiles/spartan-6-pkgs.htm. Table 2-1:
Device/ Package LX4 LX9 LX16 LX25 LX25T LX45 LX45T LX75 LX75T LX100 LX100T LX150 LX150T

Cross-Reference for Pinout Tables


TQG144 CPG196 CSG225 FT(G)256 CSG324 FG(G)484 CS(G)484 FG(G)676 FG(G)900

Table 2-2, Table 2-3, Table 2-4, page 28 page 33 page 40 Table 2-2, Table 2-3, Table 2-5, Table 2-6, Table 2-7, page 28 page 33 page 48 page 56 page 65 Table 2-3, Table 2-5, Table 2-6, Table 2-7, page 33 page 48 page 56 page 65 Table 2-6, Table 2-7, Table 2-9, page 56 page 65 page 87 Table 2-8, Table 2-10, page 76 page 103 Table 2-7, Table 2-9, page 65 page 87 Table 2-11, Table 2-13, page 119 page 151

Table 2-8, Table 2-10, Table 2-12, page 76 page 103 page 135 Table 2-9, page 87 Table 2-11, Table 2-14, page 119 page 172

Table 2-10, Table 2-12, Table 2-15, page 103 page 135 page 193 Table 2-9, page 87 Table 2-11, Table 2-14, page 119 page 172

Table 2-10, Table 2-12, Table 2-15, Table 2-17, page 103 page 135 page 193 page 242 Table 2-9, page 87 Table 2-11, Table 2-14, Table 2-16, page 119 page 172 page 214

Table 2-10, Table 2-12, Table 2-15, Table 2-17, page 135 page 193 page 242 page 103

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Chapter 2: Pinout Tables

TQG144 PackageLX4 and LX9


The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/O clock input for the associated pin. For more information see Clock Inputs and BUFIO2 Clocking Regions in Chapter 1.
BUFIO2 Region TL TR RT RB BL BR LT LB Description I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 3 (left). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 3 (left).

Table 2-2:
Bank

TQG144 PackageLX4 and LX9


Pin Description Pin Number P144 P143 P142 P141 P140 P139 P138 P137 P134 P133 P132 P131 P127 P126 P124 P123 P121 P120 P119 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TR TR TR TR TR TR TR No Connect (NC)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L35N_GCLK16_0 IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L62P_0 IO_L62N_VREF_0 IO_L63P_SCP7_0

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TQG144 PackageLX4 and LX9

Table 2-2:
Bank

TQG144 PackageLX4 and LX9 (Contd)


Pin Description Pin Number P118 P117 P116 P115 P114 P112 P111 P109 P110 P107 P106 P105 P104 P102 P101 P100 P99 P98 P97 P95 P94 P93 P92 P88 P87 P85 P84 P83 P82 P81 P80 P79 P78 BUFIO2 Region TR TR TR TR TR TR TR NA NA NA NA RT RT RT RT RT RT RT RT RT RT RT RT RB RB RB RB RB RB RB RB RB RB No Connect (NC)

0 0 0 0 0 0 0 NA NA NA NA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 TCK TDI TMS TDO IO_L1P_1 IO_L1N_VREF_1 IO_L32P_1 IO_L32N_1 IO_L33P_1 IO_L33N_1 IO_L34P_1 IO_L34N_1 IO_L40P_GCLK11_1 IO_L40N_GCLK10_1 IO_L41P_GCLK9_IRDY1_1 IO_L41N_GCLK8_1 IO_L42P_GCLK7_1 IO_L42N_GCLK6_TRDY1_1 IO_L43P_GCLK5_1 IO_L43N_GCLK4_1 IO_L45P_1 IO_L45N_1 IO_L46P_1 IO_L46N_1 IO_L47P_1 IO_L47N_1

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Chapter 2: Pinout Tables

Table 2-2:
Bank

TQG144 PackageLX4 and LX9 (Contd)


Pin Description Pin Number P75 P74 P73 P72 P71 P70 P69 P67 P66 P65 P64 P62 P61 P60 P59 P58 P57 P56 P55 P51 P50 P48 P47 P46 P45 P44 P43 P41 P40 P39 P38 P37 P35 BUFIO2 Region RB RB NA NA NA BR BR BR BR BR BR BR BR BR BR BR BR BR BR BL BL BL BL BL BL BL BL BL BL BL BL NA LB No Connect (NC)

1 1 NA 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3

IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1 SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2 IO_L2N_CMPMOSI_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2 IO_L13P_M1_2 IO_L13N_D10_2 IO_L14P_D11_2 IO_L14N_D12_2 IO_L30P_GCLK1_D13_2 IO_L30N_GCLK0_USERCCLK_2 IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2 IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L49N_D4_2 IO_L62P_D5_2 IO_L62N_D6_2 IO_L64P_D8_2 IO_L64N_D9_2 IO_L65P_INIT_B_2 IO_L65N_CSO_B_2 PROGRAM_B_2 IO_L1P_3

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TQG144 PackageLX4 and LX9

Table 2-2:
Bank

TQG144 PackageLX4 and LX9 (Contd)


Pin Description Pin Number P34 P33 P32 P30 P29 P27 P26 P24 P23 P22 P21 P17 P16 P15 P14 P12 P11 P10 P9 P8 P7 P6 P5 P2 P1 P108 P113 P13 P130 P136 P25 P3 P49 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LT LT LT LT LT LT LT LT LT LT LT LT LT LT NA NA NA NA NA NA NA NA No Connect (NC)

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 NA NA NA NA NA NA NA NA

IO_L1N_VREF_3 IO_L2P_3 IO_L2N_3 IO_L36P_3 IO_L36N_3 IO_L37P_3 IO_L37N_3 IO_L41P_GCLK27_3 IO_L41N_GCLK26_3 IO_L42P_GCLK25_TRDY2_3 IO_L42N_GCLK24_3 IO_L43P_GCLK23_3 IO_L43N_GCLK22_IRDY2_3 IO_L44P_GCLK21_3 IO_L44N_GCLK20_3 IO_L49P_3 IO_L49N_3 IO_L50P_3 IO_L50N_3 IO_L51P_3 IO_L51N_3 IO_L52P_3 IO_L52N_3 IO_L83P_3 IO_L83N_VREF_3 GND GND GND GND GND GND GND GND

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Chapter 2: Pinout Tables

Table 2-2:
Bank

TQG144 PackageLX4 and LX9 (Contd)


Pin Description Pin Number P54 P68 P77 P91 P96 P129 P20 P36 P53 P90 P128 P19 P28 P52 P89 P122 P125 P135 P103 P76 P86 P42 P63 P18 P31 P4 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 0 0 0 1 1 1 2 2 3 3 3

GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3

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CPG196 PackageLX4, LX9, and LX16

CPG196 PackageLX4, LX9, and LX16


The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/O clock input for the associated pin. For more information see Clock Inputs and BUFIO2 Clocking Regions in Chapter 1.
BUFIO2 Region TL TR RT RB BL BR LT LB Description I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 3 (left). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 3 (left).

Table 2-3:
Bank

CPG196 PackageLX4, LX9, and LX16


Pin Description Pin Number B2 A2 B3 A3 B4 A4 B5 A5 B6 A6 B7 A7 D8 C8 B8 A8 B9 A9 B10 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TR TR TR TR TR TR TR No Connect (NC)

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L35N_GCLK16_0 IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L62P_0 IO_L62N_VREF_0 IO_L63P_SCP7_0

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Chapter 2: Pinout Tables

Table 2-3:
Bank

CPG196 PackageLX4, LX9, and LX16 (Contd)


Pin Description Pin Number A10 B11 A11 B12 A12 D11 C11 B13 A13 B14 C14 C12 C13 D13 D14 E13 E14 F11 F12 G13 G14 F13 F14 H13 H14 H11 H12 J13 J14 J11 J12 K13 K14 BUFIO2 Region TR TR TR TR TR TR TR NA NA NA NA RT RT RT RT RT RT RT RT RT RT RT RT RB RB RB RB RB RB RB RB RB RB No Connect (NC)

0 0 0 0 0 0 0 NA NA NA NA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 TCK TDI TMS TDO IO_L1P_1 IO_L1N_VREF_1 IO_L32P_1 IO_L32N_1 IO_L33P_1 IO_L33N_1 IO_L34P_1 IO_L34N_1 IO_L40P_GCLK11_1 IO_L40N_GCLK10_1 IO_L41P_GCLK9_IRDY1_1 IO_L41N_GCLK8_1 IO_L42P_GCLK7_1 IO_L42N_GCLK6_TRDY1_1 IO_L43P_GCLK5_1 IO_L43N_GCLK4_1 IO_L45P_1 IO_L45N_1 IO_L46P_1 IO_L46N_1 IO_L47P_1 IO_L47N_1

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CPG196 PackageLX4, LX9, and LX16

Table 2-3:
Bank

CPG196 PackageLX4, LX9, and LX16 (Contd)


Pin Description Pin Number L13 L14 M13 M14 L12 M12 N14 N13 P13 N12 P12 N11 P11 N10 P10 N9 P9 L8 M8 N8 P8 N7 P7 N6 P6 N5 P5 L4 M4 N4 P4 N3 P3 BUFIO2 Region RB RB RB RB NA NA NA BR BR BR BR BR BR BR BR BR BR BR BR BR BR BL BL BL BL BL BL BL BL BL BL BL BL No Connect (NC)

1 1 1 1 NA 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

IO_L53P_1 IO_L53N_VREF_1 IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1 SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2 IO_L2N_CMPMOSI_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2 IO_L13P_M1_2 IO_L13N_D10_2 IO_L14P_D11_2 IO_L14N_D12_2 IO_L30P_GCLK1_D13_2 IO_L30N_GCLK0_USERCCLK_2 IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2 IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L49N_D4_2 IO_L62P_D5_2 IO_L62N_D6_2 IO_L63P_2 IO_L63N_2 IO_L64P_D8_2 IO_L64N_D9_2

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Chapter 2: Pinout Tables

Table 2-3:
Bank

CPG196 PackageLX4, LX9, and LX16 (Contd)


Pin Description Pin Number N2 P2 N1 M2 M1 L2 L1 K2 K1 J4 J3 J2 J1 G2 G1 H2 H1 F2 F1 F4 F3 E2 E1 D4 D3 D2 D1 C1 B1 A1 A14 C2 C3 BUFIO2 Region BL BL NA LB LB LB LB LB LB LB LB LB LB LB LB LT LT LT LT LT LT LT LT LT LT LT LT LT LT NA NA NA NA No Connect (NC)

2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 NA NA NA NA

IO_L65P_INIT_B_2 IO_L65N_CSO_B_2 PROGRAM_B_2 IO_L1P_3 IO_L1N_VREF_3 IO_L2P_3 IO_L2N_3 IO_L36P_3 IO_L36N_3 IO_L37P_3 IO_L37N_3 IO_L41P_GCLK27_3 IO_L41N_GCLK26_3 IO_L42P_GCLK25_TRDY2_3 IO_L42N_GCLK24_3 IO_L43P_GCLK23_3 IO_L43N_GCLK22_IRDY2_3 IO_L44P_GCLK21_3 IO_L44N_GCLK20_3 IO_L49P_3 IO_L49N_3 IO_L50P_3 IO_L50N_3 IO_L51P_3 IO_L51N_3 IO_L52P_3 IO_L52N_3 IO_L83P_3 IO_L83N_VREF_3 GND GND GND GND

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CPG196 PackageLX4, LX9, and LX16

Table 2-3:
Bank

CPG196 PackageLX4, LX9, and LX16 (Contd)


Pin Description Pin Number C6 C7 D10 D5 D6 D9 E11 E8 F7 F8 G5 G6 G7 G8 H10 H4 H7 H8 H9 J10 J7 J8 K8 L10 L11 L3 L5 L6 L9 M11 M3 M7 P1 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Chapter 2: Pinout Tables

Table 2-3:
Bank

CPG196 PackageLX4, LX9, and LX16 (Contd)


Pin Description Pin Number P14 G4 E10 E5 E6 E9 F10 F5 F6 F9 J5 J6 J9 K10 K5 K6 K9 E7 G10 G9 H5 H6 K7 L7 D7 C10 C4 C5 C9 D12 E12 G11 G12 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 0 0 0 0 1 1 1 1

GND GND VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1

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CPG196 PackageLX4, LX9, and LX16

Table 2-3:
Bank

CPG196 PackageLX4, LX9, and LX16 (Contd)


Pin Description Pin Number K11 K12 M10 M5 M6 M9 G3 E3 E4 H3 K3 K4 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

1 1 2 2 2 2 3 3 3 3 3 3

VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3

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Chapter 2: Pinout Tables

CSG225 PackageLX4
Although the LX4 devices are pin compatible with the LX9 and LX16 devices in the CSG225 package (see Table 2-5, CSG225 PackageLX9 and LX16, on page 48), the LX4 does not contain the Memory Controller block or support for BPI/Master Parallel mode. The dual-purpose pin names for these features are not the same as the LX4 pin names. For convenience, the No Connect column in Table 2-5 lists the LX4 pins that are not connected. The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/O clock input for the associated pin. For more information see Clock Inputs and BUFIO2 Clocking Regions in Chapter 1.
BUFIO2 Region TL TR RT RB BL BR LT LB Description I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 3 (left). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 3 (left).

Table 2-4:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CSG225 PackageLX4
Pin Description Pin Number B2 A2 B3 A3 D5 C5 C4 A4 B5 A5 C6 A6 E7 D8 B7 A7 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL No Connect (NC)

IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L6P_0 IO_L6N_0 IO_L33P_0 IO_L33N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L35N_GCLK16_0

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CSG225 PackageLX4

Table 2-4:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NA NA NA NA 1 1 1 1 1 1 1 1 1 1 1

CSG225 PackageLX4 (Contd)


Pin Description Pin Number C8 A8 B9 A9 D10 C9 F10 E9 C10 A10 B11 A11 D11 C11 B13 A13 C12 A12 A14 E10 E13 D12 B14 B15 C14 C15 D13 D15 J11 J13 E14 E15 K10 BUFIO2 Region TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR NA NA NA NA RT RT RT RT RT RT RT RT RT RT RT No Connect (NC)

IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L39P_0 IO_L39N_0 IO_L40P_0 IO_L40N_0 IO_L62P_0 IO_L62N_VREF_0 IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 TCK TDI TMS TDO IO_L1P_1 IO_L1N_VREF_1 IO_L33P_1 IO_L33N_1 IO_L35P_1 IO_L35N_1 IO_L36P_1 IO_L36N_1 IO_L37P_1 IO_L37N_1 IO_L38P_1

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Chapter 2: Pinout Tables

Table 2-4:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NA 2 2 2 2 2 2 2 2 2 2 2

CSG225 PackageLX4 (Contd)


Pin Description Pin Number K11 F13 F15 K12 L12 G14 G15 H13 H15 J14 J15 K13 K15 L14 L15 M13 M15 N14 N15 P14 P15 L13 L10 R14 N12 R12 P13 R13 P11 R11 M11 N11 N10 BUFIO2 Region RT RT RT RT RT RT RT RB RB RB RB RB RB RB RB RB RB RB RB RB RB NA NA NA BR BR BR BR BR BR BR BR BR No Connect (NC)

IO_L38N_1 IO_L39P_1 IO_L39N_1 IO_L40P_GCLK11_1 IO_L40N_GCLK10_1 IO_L41P_GCLK9_IRDY1_1 IO_L41N_GCLK8_1 IO_L42P_GCLK7_1 IO_L42N_GCLK6_TRDY1_1 IO_L43P_GCLK5_1 IO_L43N_GCLK4_1 IO_L44P_1 IO_L44N_1 IO_L45P_1 IO_L45N_1 IO_L46P_1 IO_L46N_1 IO_L47P_1 IO_L47N_1 IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1 SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2 IO_L2N_CMPMOSI_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2 IO_L13P_M1_2

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG225 PackageLX4

Table 2-4:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3

CSG225 PackageLX4 (Contd)


Pin Description Pin Number R10 L9 M10 P9 R9 N8 R8 M8 N7 K8 L8 P7 R7 N6 R6 P5 R5 L6 L5 N4 R4 M5 N5 P3 R3 R2 M4 L3 P2 P1 N2 N1 M3 BUFIO2 Region BR BR BR BR BR BR BR BR BR BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL NA LB LB LB LB LB LB LB No Connect (NC)

IO_L13N_D10_2 IO_L14P_D11_2 IO_L14N_D12_2 IO_L16P_2 IO_L16N_VREF_2 IO_L29P_GCLK3_2 IO_L29N_GCLK2_2 IO_L30P_GCLK1_D13_2 IO_L30N_GCLK0_USERCCLK_2 IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2 IO_L32P_GCLK29_2 IO_L32N_GCLK28_2 IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L49N_D4_2 IO_L62P_D5_2 IO_L62N_D6_2 IO_L63P_2 IO_L63N_2 IO_L64P_D8_2 IO_L64N_D9_2 IO_L65P_INIT_B_2 IO_L65N_CSO_B_2 PROGRAM_B_2 IO_L1P_3 IO_L1N_VREF_3 IO_L2P_3 IO_L2N_3 IO_L37P_3 IO_L37N_3 IO_L38P_3

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Chapter 2: Pinout Tables

Table 2-4:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 NA NA NA NA NA NA NA NA

CSG225 PackageLX4 (Contd)


Pin Description Pin Number M1 L2 L1 K3 K1 J2 J1 H3 H1 K4 J3 G2 G1 K5 J4 F3 F1 E2 E1 D4 E3 D3 D1 C2 C1 A1 A15 B10 B6 C13 C3 E11 F14 BUFIO2 Region LB LB LB LB LB LB LB LB LB LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT NA NA NA NA NA NA NA NA No Connect (NC)

IO_L38N_3 IO_L39P_3 IO_L39N_3 IO_L40P_3 IO_L40N_3 IO_L41P_GCLK27_3 IO_L41N_GCLK26_3 IO_L42P_GCLK25_TRDY2_3 IO_L42N_GCLK24_3 IO_L43P_GCLK23_3 IO_L43N_GCLK22_IRDY2_3 IO_L44P_GCLK21_3 IO_L44N_GCLK20_3 IO_L45P_3 IO_L45N_3 IO_L46P_3 IO_L46N_3 IO_L52P_3 IO_L52N_3 IO_L53P_3 IO_L53N_3 IO_L54P_3 IO_L54N_3 IO_L83P_3 IO_L83N_VREF_3 GND GND GND GND GND GND GND GND

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG225 PackageLX4

Table 2-4:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

CSG225 PackageLX4 (Contd)


Pin Description Pin Number F2 F6 G7 G9 H8 J7 J9 K14 K2 K6 L11 N13 N3 P10 P6 R1 R15 F9 G6 G8 H7 H9 J10 J8 K7 B1 E12 F7 G10 J6 K9 L4 M12 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX

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Chapter 2: Pinout Tables

Table 2-4:
Bank 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

CSG225 PackageLX4 (Contd)


Pin Description Pin Number B12 B4 B8 D9 D14 H14 J12 M14 M7 P12 P4 P8 D2 G4 H2 M2 E6 D6 D7 C7 F8 E8 G11 G12 F11 F12 H10 H11 H12 G13 M9 N9 L7 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG225 PackageLX4

Table 2-4:
Bank NA NA NA NA NA NA NA NA NA NA NA

CSG225 PackageLX4 (Contd)


Pin Description Pin Number M6 J5 H4 G5 G3 H6 H5 F5 F4 E5 E4 BUFIO2 Region No Connect (NC)

NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED NOPAD/UNCONNECTED

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Chapter 2: Pinout Tables

CSG225 PackageLX9 and LX16


See Table 2-4, CSG225 PackageLX4, on page 40 for LX4 pinouts. The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/O clock input for the associated pin. For more information see Clock Inputs and BUFIO2 Clocking Regions in Chapter 1.
BUFIO2 Region TL TR RT RB BL BR LT LB Description I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 3 (left). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 3 (left).

Table 2-5:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CSG225 PackageLX9 and LX16


Pin Description Pin Number B2 A2 B3 A3 D5 C5 C4 A4 E6 D6 B5 A5 D7 C7 C6 A6 E7 D8 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL LX4 LX4 LX4 LX4 No Connect (NC)

IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L5P_0 IO_L5N_0 IO_L6P_0 IO_L6N_0 IO_L7P_0 IO_L7N_0 IO_L33P_0 IO_L33N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG225 PackageLX9 and LX16

Table 2-5:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NA NA NA NA 1 1 1 1 1 1 1

CSG225 PackageLX9 and LX16 (Contd)


Pin Description Pin Number B7 A7 C8 A8 B9 A9 F8 E8 D10 C9 F10 E9 C10 A10 B11 A11 D11 C11 B13 A13 C12 A12 A14 E10 E13 D12 B14 B15 G11 G12 F11 F12 H10 BUFIO2 Region TL TL TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR NA NA NA NA RT RT RT RT RT RT RT LX4 LX4 LX4 LX4 LX4 LX4 LX4 No Connect (NC)

IO_L35P_GCLK17_0 IO_L35N_GCLK16_0 IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L38P_0 IO_L38N_VREF_0 IO_L39P_0 IO_L39N_0 IO_L40P_0 IO_L40N_0 IO_L62P_0 IO_L62N_VREF_0 IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 TCK TDI TMS TDO IO_L1P_A25_1 IO_L1N_A24_VREF_1 IO_L30P_A21_M1RESET_1 IO_L30N_A20_M1A11_1 IO_L31P_A19_M1CKE_1 IO_L31N_A18_M1A12_1 IO_L32P_A17_M1A8_1

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Chapter 2: Pinout Tables

Table 2-5:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CSG225 PackageLX9 and LX16 (Contd)


Pin Description Pin Number H11 C14 C15 H12 G13 D13 D15 J11 J13 E14 E15 K10 K11 F13 F15 K12 L12 G14 G15 H13 H15 J14 J15 K13 K15 L14 L15 M13 M15 N14 N15 P14 P15 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RB RB RB RB RB RB RB RB RB RB RB RB RB RB LX4 LX4 No Connect (NC) LX4

IO_L32N_A16_M1A9_1 IO_L33P_A15_M1A10_1 IO_L33N_A14_M1A4_1 IO_L34P_A13_M1WE_1 IO_L34N_A12_M1BA2_1 IO_L35P_A11_M1A7_1 IO_L35N_A10_M1A2_1 IO_L36P_A9_M1BA0_1 IO_L36N_A8_M1BA1_1 IO_L37P_A7_M1A0_1 IO_L37N_A6_M1A1_1 IO_L38P_A5_M1CLK_1 IO_L38N_A4_M1CLKN_1 IO_L39P_M1A3_1 IO_L39N_M1ODT_1 IO_L40P_GCLK11_M1A5_1 IO_L40N_GCLK10_M1A6_1 IO_L41P_GCLK9_IRDY1_M1RASN_1 IO_L41N_GCLK8_M1CASN_1 IO_L42P_GCLK7_M1UDM_1 IO_L42N_GCLK6_TRDY1_M1LDM_1 IO_L43P_GCLK5_M1DQ4_1 IO_L43N_GCLK4_M1DQ5_1 IO_L44P_A3_M1DQ6_1 IO_L44N_A2_M1DQ7_1 IO_L45P_A1_M1LDQS_1 IO_L45N_A0_M1LDQSN_1 IO_L46P_FCS_B_M1DQ2_1 IO_L46N_FOE_B_M1DQ3_1 IO_L47P_FWE_B_M1DQ0_1 IO_L47N_LDC_M1DQ1_1 IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG225 PackageLX9 and LX16

Table 2-5:
Bank NA 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

CSG225 PackageLX9 and LX16 (Contd)


Pin Description Pin Number L13 L10 R14 N12 R12 P13 R13 P11 R11 M11 N11 N10 R10 L9 M10 M9 N9 P9 R9 N8 R8 M8 N7 K8 L8 P7 R7 L7 M6 N6 R6 P5 R5 BUFIO2 Region NA NA NA BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BL BL BL BL BL BL BL BL BL BL LX4 LX4 LX4 LX4 No Connect (NC)

SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2 IO_L2N_CMPMOSI_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2 IO_L13P_M1_2 IO_L13N_D10_2 IO_L14P_D11_2 IO_L14N_D12_2 IO_L15P_2 IO_L15N_2 IO_L16P_2 IO_L16N_VREF_2 IO_L29P_GCLK3_2 IO_L29N_GCLK2_2 IO_L30P_GCLK1_D13_2 IO_L30N_GCLK0_USERCCLK_2 IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2 IO_L32P_GCLK29_2 IO_L32N_GCLK28_2 IO_L47P_2 IO_L47N_2 IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L49N_D4_2

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Chapter 2: Pinout Tables

Table 2-5:
Bank 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

CSG225 PackageLX9 and LX16 (Contd)


Pin Description Pin Number L6 L5 N4 R4 M5 N5 P3 R3 R2 M4 L3 P2 P1 N2 N1 M3 M1 L2 L1 K3 K1 J2 J1 H3 H1 K4 J3 G2 G1 K5 J4 F3 F1 BUFIO2 Region BL BL BL BL BL BL BL BL NA LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LT LT LT LT LT LT LT LT No Connect (NC)

IO_L62P_D5_2 IO_L62N_D6_2 IO_L63P_2 IO_L63N_2 IO_L64P_D8_2 IO_L64N_D9_2 IO_L65P_INIT_B_2 IO_L65N_CSO_B_2 PROGRAM_B_2 IO_L1P_3 IO_L1N_VREF_3 IO_L2P_3 IO_L2N_3 IO_L37P_M3DQ0_3 IO_L37N_M3DQ1_3 IO_L38P_M3DQ2_3 IO_L38N_M3DQ3_3 IO_L39P_M3LDQS_3 IO_L39N_M3LDQSN_3 IO_L40P_M3DQ6_3 IO_L40N_M3DQ7_3 IO_L41P_GCLK27_M3DQ4_3 IO_L41N_GCLK26_M3DQ5_3 IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L42N_GCLK24_M3LDM_3 IO_L43P_GCLK23_M3RASN_3 IO_L43N_GCLK22_IRDY2_M3CASN_3 IO_L44P_GCLK21_M3A5_3 IO_L44N_GCLK20_M3A6_3 IO_L45P_M3A3_3 IO_L45N_M3ODT_3 IO_L46P_M3CLK_3 IO_L46N_M3CLKN_3

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG225 PackageLX9 and LX16

Table 2-5:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

CSG225 PackageLX9 and LX16 (Contd)


Pin Description Pin Number J5 H4 G5 G3 H6 H5 F5 F4 E5 E4 E2 E1 D4 E3 D3 D1 C2 C1 A1 A15 B10 B6 C13 C3 E11 F14 F2 F6 G7 G9 H8 J7 J9 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC) LX4 LX4 LX4 LX4 LX4 LX4 LX4 LX4 LX4 LX4

IO_L47P_M3A0_3 IO_L47N_M3A1_3 IO_L48P_M3BA0_3 IO_L48N_M3BA1_3 IO_L49P_M3A7_3 IO_L49N_M3A2_3 IO_L50P_M3WE_3 IO_L50N_M3BA2_3 IO_L51P_M3A10_3 IO_L51N_M3A4_3 IO_L52P_M3A8_3 IO_L52N_M3A9_3 IO_L53P_M3CKE_3 IO_L53N_M3A12_3 IO_L54P_M3RESET_3 IO_L54N_M3A11_3 IO_L83P_3 IO_L83N_VREF_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Chapter 2: Pinout Tables

Table 2-5:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 0 0 0 0 1 1 1

CSG225 PackageLX9 and LX16 (Contd)


Pin Description Pin Number K14 K2 K6 L11 N13 N3 P10 P6 R1 R15 B1 E12 F7 G10 J6 K9 L4 M12 F9 G6 G8 H7 H9 J10 J8 K7 B12 B4 B8 D9 D14 H14 J12 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG225 PackageLX9 and LX16

Table 2-5:
Bank 1 2 2 2 2 3 3 3 3

CSG225 PackageLX9 and LX16 (Contd)


Pin Description Pin Number M14 M7 P12 P4 P8 D2 G4 H2 M2 BUFIO2 Region NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3

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Chapter 2: Pinout Tables

FT(G)256 PackageLX9, LX16, and LX25


The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/O clock input for the associated pin. For more information see Clock Inputs and BUFIO2 Clocking Regions in Chapter 1.
BUFIO2 Region TL TR RT RB BL BR LT LB Description I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 3 (left). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 3 (left).

Table 2-6:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FT(G)256 PackageLX9, LX16, and LX25


Pin Description Pin Number C4 A4 B5 A5 D5 C5 B6 A6 F7 E6 C7 A7 D6 C6 B8 A8 C9 A9 B10 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL No Connect (NC)

IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L5P_0 IO_L5N_0 IO_L6P_0 IO_L6N_0 IO_L7P_0 IO_L7N_0 IO_L33P_0 IO_L33N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0

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FT(G)256 PackageLX9, LX16, and LX25

Table 2-6:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NA NA NA NA 1 1 1 1 1 1 1 1

FT(G)256 PackageLX9, LX16, and LX25 (Contd)


Pin Description Pin Number A10 E7 E8 E10 C10 D8 C8 C11 A11 F9 D9 B12 A12 C13 A13 F10 E11 B14 A14 D11 D12 C14 C12 A15 E14 E13 E12 B15 B16 F12 G11 D14 D16 BUFIO2 Region TL TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR NA NA NA NA RT RT RT RT RT RT RT RT No Connect (NC)

IO_L35N_GCLK16_0 IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L38P_0 IO_L38N_VREF_0 IO_L39P_0 IO_L39N_0 IO_L40P_0 IO_L40N_0 IO_L62P_0 IO_L62N_VREF_0 IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 TCK TDI TMS TDO IO_L1P_A25_1 IO_L1N_A24_VREF_1 IO_L29P_A23_M1A13_1 IO_L29N_A22_M1A14_1 IO_L30P_A21_M1RESET_1 IO_L30N_A20_M1A11_1 IO_L31P_A19_M1CKE_1 IO_L31N_A18_M1A12_1

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Chapter 2: Pinout Tables

Table 2-6:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FT(G)256 PackageLX9, LX16, and LX25 (Contd)


Pin Description Pin Number F13 F14 C15 C16 E15 E16 F15 F16 G14 G16 H15 H16 G12 H11 H13 H14 J11 J12 J13 K14 K12 K11 J14 J16 K15 K16 N14 N16 M15 M16 L14 L16 P15 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT (RB in LX25) RT (RB in LX25) RT (RB in LX25) RT (RB in LX25) RT (RB in LX25) RT (RB in LX25) RB RB RB RB RB RB RB RB RB RB RB RB RB No Connect (NC)

IO_L32P_A17_M1A8_1 IO_L32N_A16_M1A9_1 IO_L33P_A15_M1A10_1 IO_L33N_A14_M1A4_1 IO_L34P_A13_M1WE_1 IO_L34N_A12_M1BA2_1 IO_L35P_A11_M1A7_1 IO_L35N_A10_M1A2_1 IO_L36P_A9_M1BA0_1 IO_L36N_A8_M1BA1_1 IO_L37P_A7_M1A0_1 IO_L37N_A6_M1A1_1 IO_L38P_A5_M1CLK_1 IO_L38N_A4_M1CLKN_1 IO_L39P_M1A3_1 IO_L39N_M1ODT_1 IO_L40P_GCLK11_M1A5_1 IO_L40N_GCLK10_M1A6_1 IO_L41P_GCLK9_IRDY1_M1RASN_1 IO_L41N_GCLK8_M1CASN_1 IO_L42P_GCLK7_M1UDM_1 IO_L42N_GCLK6_TRDY1_M1LDM_1 IO_L43P_GCLK5_M1DQ4_1 IO_L43N_GCLK4_M1DQ5_1 IO_L44P_A3_M1DQ6_1 IO_L44N_A2_M1DQ7_1 IO_L45P_A1_M1LDQS_1 IO_L45N_A0_M1LDQSN_1 IO_L46P_FCS_B_M1DQ2_1 IO_L46N_FOE_B_M1DQ3_1 IO_L47P_FWE_B_M1DQ0_1 IO_L47N_LDC_M1DQ1_1 IO_L48P_HDC_M1DQ8_1

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FT(G)256 PackageLX9, LX16, and LX25

Table 2-6:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 NA 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FT(G)256 PackageLX9, LX16, and LX25 (Contd)


Pin Description Pin Number P16 R15 R16 R14 T15 T14 T13 R12 T12 L12 L13 M13 M14 P14 L11 P13 R11 T11 M12 M11 P10 T10 N12 P12 N11 P11 N9 P9 L10 M10 R9 T9 M9 BUFIO2 Region RB RB RB RB RB RB RB RB RB RB RB RB RB NA NA NA BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR No Connect (NC)

IO_L48N_M1DQ9_1 IO_L49P_M1DQ10_1 IO_L49N_M1DQ11_1 IO_L50P_M1UDQS_1 IO_L50N_M1UDQSN_1 IO_L51P_M1DQ12_1 IO_L51N_M1DQ13_1 IO_L52P_M1DQ14_1 IO_L52N_M1DQ15_1 IO_L53P_1 IO_L53N_VREF_1 IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1 SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2 IO_L2N_CMPMOSI_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2 IO_L13P_M1_2 IO_L13N_D10_2 IO_L14P_D11_2 IO_L14N_D12_2 IO_L16P_2 IO_L16N_VREF_2 IO_L23P_2 IO_L23N_2 IO_L29P_GCLK3_2

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Chapter 2: Pinout Tables

Table 2-6:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3

FT(G)256 PackageLX9, LX16, and LX25 (Contd)


Pin Description Pin Number N8 P8 T8 P7 M7 R7 T7 P6 T6 R5 T5 N5 P5 L8 L7 P4 T4 M6 N6 R3 T3 T2 M4 M3 M5 N4 R2 R1 P2 P1 N3 N1 M2 BUFIO2 Region BR BR BR BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL NA LB LB LB LB LB LB LB LB LB LB LB No Connect (NC)

IO_L29N_GCLK2_2 IO_L30P_GCLK1_D13_2 IO_L30N_GCLK0_USERCCLK_2 IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2 IO_L32P_GCLK29_2 IO_L32N_GCLK28_2 IO_L47P_2 IO_L47N_2 IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L49N_D4_2 IO_L62P_D5_2 IO_L62N_D6_2 IO_L63P_2 IO_L63N_2 IO_L64P_D8_2 IO_L64N_D9_2 IO_L65P_INIT_B_2 IO_L65N_CSO_B_2 PROGRAM_B_2 IO_L1P_3 IO_L1N_VREF_3 IO_L2P_3 IO_L2N_3 IO_L32P_M3DQ14_3 IO_L32N_M3DQ15_3 IO_L33P_M3DQ12_3 IO_L33N_M3DQ13_3 IO_L34P_M3UDQS_3 IO_L34N_M3UDQSN_3 IO_L35P_M3DQ10_3

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FT(G)256 PackageLX9, LX16, and LX25

Table 2-6:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FT(G)256 PackageLX9, LX16, and LX25 (Contd)


Pin Description Pin Number M1 L3 L1 K2 K1 J3 J1 H2 H1 G3 G1 F2 F1 K3 J4 J6 H5 H4 H3 L4 L5 E2 E1 K5 K6 C3 C2 D3 D1 C1 B1 G6 G5 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LT (LB in LX25) LT (LB in LX25) LT (LB in LX25) LT (LB in LX25) LT (LB in LX25) LT (LB in LX25) LT LT LT LT LT LT LT LT LT LT LT LT No Connect (NC)

IO_L35N_M3DQ11_3 IO_L36P_M3DQ8_3 IO_L36N_M3DQ9_3 IO_L37P_M3DQ0_3 IO_L37N_M3DQ1_3 IO_L38P_M3DQ2_3 IO_L38N_M3DQ3_3 IO_L39P_M3LDQS_3 IO_L39N_M3LDQSN_3 IO_L40P_M3DQ6_3 IO_L40N_M3DQ7_3 IO_L41P_GCLK27_M3DQ4_3 IO_L41N_GCLK26_M3DQ5_3 IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L42N_GCLK24_M3LDM_3 IO_L43P_GCLK23_M3RASN_3 IO_L43N_GCLK22_IRDY2_M3CASN_3 IO_L44P_GCLK21_M3A5_3 IO_L44N_GCLK20_M3A6_3 IO_L45P_M3A3_3 IO_L45N_M3ODT_3 IO_L46P_M3CLK_3 IO_L46N_M3CLKN_3 IO_L47P_M3A0_3 IO_L47N_M3A1_3 IO_L48P_M3BA0_3 IO_L48N_M3BA1_3 IO_L49P_M3A7_3 IO_L49N_M3A2_3 IO_L50P_M3WE_3 IO_L50N_M3BA2_3 IO_L51P_M3A10_3 IO_L51N_M3A4_3

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Chapter 2: Pinout Tables

Table 2-6:
Bank 3 3 3 3 3 3 3 3 3 3 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FT(G)256 PackageLX9, LX16, and LX25 (Contd)


Pin Description Pin Number B2 A2 F4 F3 E4 E3 F6 F5 B3 A3 A1 A16 B11 B7 D13 D4 E9 G15 G2 G8 H12 H7 H9 J5 J8 K7 K9 L15 L2 M8 N13 P3 R10 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

IO_L52P_M3A8_3 IO_L52N_M3A9_3 IO_L53P_M3CKE_3 IO_L53N_M3A12_3 IO_L54P_M3RESET_3 IO_L54N_M3A11_3 IO_L55P_M3A13_3 IO_L55N_M3A14_3 IO_L83P_3 IO_L83N_VREF_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FT(G)256 PackageLX9, LX16, and LX25

Table 2-6:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 0 0 0 0 0 1 1 1 1 1 1 2 2 2

FT(G)256 PackageLX9, LX16, and LX25 (Contd)


Pin Description Pin Number R6 T1 T16 E5 F11 F8 G10 H6 J10 L6 L9 G7 G9 H10 H8 J7 J9 K10 K8 B13 B4 B9 D10 D7 D15 G13 J15 K13 N15 R13 N10 N7 R4 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2

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Chapter 2: Pinout Tables

Table 2-6:
Bank 2 3 3 3 3 3

FT(G)256 PackageLX9, LX16, and LX25 (Contd)


Pin Description Pin Number R8 D2 G4 J2 K4 N2 BUFIO2 Region NA NA NA NA NA NA No Connect (NC)

VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG324 PackageLX9, LX16, LX25, and LX45

CSG324 PackageLX9, LX16, LX25, and LX45


The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/O clock input for the associated pin. For more information see Clock Inputs and BUFIO2 Clocking Regions in Chapter 1.
BUFIO2 Region TL TR RT RB BL BR LT LB Description I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 3 (left). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 3 (left).

Table 2-7:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CSG324 PackageLX9, LX16, LX25, and LX45


Pin Description Pin Number D4 C4 B2 A2 D6 C6 B3 A3 B4 A4 C5 A5 F7 E6 B6 A6 E7 E8 C7 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL LX9, LX25, LX45 LX9, LX25, LX45 LX9, LX25, LX45 LX9, LX25, LX45 No Connect (NC)

IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L5P_0 IO_L5N_0 IO_L6P_0 IO_L6N_0 IO_L7P_0 IO_L7N_0 IO_L8P_0 IO_L8N_VREF_0 IO_L9P_0 IO_L9N_0 IO_L10P_0

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Chapter 2: Pinout Tables

Table 2-7:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CSG324 PackageLX9, LX16, LX25, and LX45 (Contd)


Pin Description Pin Number A7 D8 C8 G8 F8 B8 A8 D9 C9 B9 A9 D11 C11 C10 A10 G9 F9 B11 A11 G11 F10 B12 A12 F11 E11 D12 C12 C13 A13 F12 E12 B14 A14 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR LX9, LX45 LX9, LX45 LX9, LX45 LX9, LX45 LX9 LX9 LX9, LX45 LX9, LX45 LX9, LX45 LX9, LX45 LX9, LX25, LX45 LX9, LX25, LX45 No Connect (NC)

IO_L10N_0 IO_L11P_0 IO_L11N_0 IO_L32P_0 IO_L32N_0 IO_L33P_0 IO_L33N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L35N_GCLK16_0 IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L38P_0 IO_L38N_VREF_0 IO_L39P_0 IO_L39N_0 IO_L40P_0 IO_L40N_0 IO_L41P_0 IO_L41N_0 IO_L42P_0 IO_L42N_0 IO_L47P_0 IO_L47N_0 IO_L50P_0 IO_L50N_0 IO_L51P_0 IO_L51N_0 IO_L62P_0 IO_L62N_VREF_0

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG324 PackageLX9, LX16, LX25, and LX45

Table 2-7:
Bank 0 0 0 0 0 0 0 0 NA NA NA NA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CSG324 PackageLX9, LX16, LX25, and LX45 (Contd)


Pin Description Pin Number F13 E13 C15 A15 D14 C14 B16 A16 A17 D15 B18 D16 F15 F16 C17 C18 F14 G14 D17 D18 H12 G13 E16 E18 K12 K13 F17 F18 H13 H14 H15 H16 G16 BUFIO2 Region TR TR TR TR TR TR TR TR NA NA NA NA RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT No Connect (NC)

IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 TCK TDI TMS TDO IO_L1P_A25_1 IO_L1N_A24_VREF_1 IO_L29P_A23_M1A13_1 IO_L29N_A22_M1A14_1 IO_L30P_A21_M1RESET_1 IO_L30N_A20_M1A11_1 IO_L31P_A19_M1CKE_1 IO_L31N_A18_M1A12_1 IO_L32P_A17_M1A8_1 IO_L32N_A16_M1A9_1 IO_L33P_A15_M1A10_1 IO_L33N_A14_M1A4_1 IO_L34P_A13_M1WE_1 IO_L34N_A12_M1BA2_1 IO_L35P_A11_M1A7_1 IO_L35N_A10_M1A2_1 IO_L36P_A9_M1BA0_1 IO_L36N_A8_M1BA1_1 IO_L37P_A7_M1A0_1 IO_L37N_A6_M1A1_1 IO_L38P_A5_M1CLK_1

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Chapter 2: Pinout Tables

Table 2-7:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CSG324 PackageLX9, LX16, LX25, and LX45 (Contd)


Pin Description Pin Number G18 J13 K14 L12 L13 K15 K16 L15 L16 H17 H18 J16 J18 K17 K18 L17 L18 M16 M18 N17 N18 P17 P18 N15 N16 T17 T18 U17 U18 M14 N14 L14 M13 BUFIO2 Region RT RT (RB in LX25) RT (RB in LX25) RT (RB in LX25) RT (RB in LX25) RT (RB in LX25) RT (RB in LX25) RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB No Connect (NC)

IO_L38N_A4_M1CLKN_1 IO_L39P_M1A3_1 IO_L39N_M1ODT_1 IO_L40P_GCLK11_M1A5_1 IO_L40N_GCLK10_M1A6_1 IO_L41P_GCLK9_IRDY1_M1RASN_1 IO_L41N_GCLK8_M1CASN_1 IO_L42P_GCLK7_M1UDM_1 IO_L42N_GCLK6_TRDY1_M1LDM_1 IO_L43P_GCLK5_M1DQ4_1 IO_L43N_GCLK4_M1DQ5_1 IO_L44P_A3_M1DQ6_1 IO_L44N_A2_M1DQ7_1 IO_L45P_A1_M1LDQS_1 IO_L45N_A0_M1LDQSN_1 IO_L46P_FCS_B_M1DQ2_1 IO_L46N_FOE_B_M1DQ3_1 IO_L47P_FWE_B_M1DQ0_1 IO_L47N_LDC_M1DQ1_1 IO_L48P_HDC_M1DQ8_1 IO_L48N_M1DQ9_1 IO_L49P_M1DQ10_1 IO_L49N_M1DQ11_1 IO_L50P_M1UDQS_1 IO_L50N_M1UDQSN_1 IO_L51P_M1DQ12_1 IO_L51N_M1DQ13_1 IO_L52P_M1DQ14_1 IO_L52N_M1DQ15_1 IO_L53P_1 IO_L53N_VREF_1 IO_L61P_1 IO_L61N_1

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG324 PackageLX9, LX16, LX25, and LX45

Table 2-7:
Bank 1 1 NA 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

CSG324 PackageLX9, LX16, LX25, and LX45 (Contd)


Pin Description Pin Number P15 P16 R16 P13 V17 R15 T15 U16 V16 R13 T13 U15 V15 T14 V14 N12 P12 U13 V13 M11 N11 R11 T11 T12 V12 N10 P11 M10 N9 U11 V11 R10 T10 BUFIO2 Region RB RB NA NA NA BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR LX9 LX9 LX9 LX9 LX9 LX9 LX9 LX9 LX9 LX9 No Connect (NC)

IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1 SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2 IO_L2N_CMPMOSI_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L5P_2 IO_L5N_2 IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2 IO_L13P_M1_2 IO_L13N_D10_2 IO_L14P_D11_2 IO_L14N_D12_2 IO_L15P_2 IO_L15N_2 IO_L16P_2 IO_L16N_VREF_2 IO_L19P_2 IO_L19N_2 IO_L20P_2 IO_L20N_2 IO_L22P_2 IO_L22N_2 IO_L23P_2 IO_L23N_2 IO_L29P_GCLK3_2 IO_L29N_GCLK2_2

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Chapter 2: Pinout Tables

Table 2-7:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

CSG324 PackageLX9, LX16, LX25, and LX45 (Contd)


Pin Description Pin Number U10 V10 R8 T8 T9 V9 M8 N8 U8 V8 U7 V7 N7 P8 T6 V6 R7 T7 N6 P7 R5 T5 U5 V5 R3 T3 T4 V4 N5 P6 U3 V3 V2 BUFIO2 Region BR BR BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL NA LX9 LX9 LX9 LX9 LX9 LX9 No Connect (NC)

IO_L30P_GCLK1_D13_2 IO_L30N_GCLK0_USERCCLK_2 IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2 IO_L32P_GCLK29_2 IO_L32N_GCLK28_2 IO_L40P_2 IO_L40N_2 IO_L41P_2 IO_L41N_VREF_2 IO_L43P_2 IO_L43N_2 IO_L44P_2 IO_L44N_2 IO_L45P_2 IO_L45N_2 IO_L46P_2 IO_L46N_2 IO_L47P_2 IO_L47N_2 IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L49N_D4_2 IO_L62P_D5_2 IO_L62N_D6_2 IO_L63P_2 IO_L63N_2 IO_L64P_D8_2 IO_L64N_D9_2 IO_L65P_INIT_B_2 IO_L65N_CSO_B_2 PROGRAM_B_2

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG324 PackageLX9, LX16, LX25, and LX45

Table 2-7:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

CSG324 PackageLX9, LX16, LX25, and LX45 (Contd)


Pin Description Pin Number N4 N3 P4 P3 L6 M5 U2 U1 T2 T1 P2 P1 N2 N1 M3 M1 L2 L1 K2 K1 L4 L3 J3 J1 H2 H1 K4 K3 L5 K5 H4 H3 L7 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LT (LB in LX25) LT (LB in LX25) LT (LB in LX25) LT (LB in LX25) LT (LB in LX25) No Connect (NC)

IO_L1P_3 IO_L1N_VREF_3 IO_L2P_3 IO_L2N_3 IO_L31P_3 IO_L31N_VREF_3 IO_L32P_M3DQ14_3 IO_L32N_M3DQ15_3 IO_L33P_M3DQ12_3 IO_L33N_M3DQ13_3 IO_L34P_M3UDQS_3 IO_L34N_M3UDQSN_3 IO_L35P_M3DQ10_3 IO_L35N_M3DQ11_3 IO_L36P_M3DQ8_3 IO_L36N_M3DQ9_3 IO_L37P_M3DQ0_3 IO_L37N_M3DQ1_3 IO_L38P_M3DQ2_3 IO_L38N_M3DQ3_3 IO_L39P_M3LDQS_3 IO_L39N_M3LDQSN_3 IO_L40P_M3DQ6_3 IO_L40N_M3DQ7_3 IO_L41P_GCLK27_M3DQ4_3 IO_L41N_GCLK26_M3DQ5_3 IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L42N_GCLK24_M3LDM_3 IO_L43P_GCLK23_M3RASN_3 IO_L43N_GCLK22_IRDY2_M3CASN_3 IO_L44P_GCLK21_M3A5_3 IO_L44N_GCLK20_M3A6_3 IO_L45P_M3A3_3

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Chapter 2: Pinout Tables

Table 2-7:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 NA NA NA NA NA NA NA NA NA NA

CSG324 PackageLX9, LX16, LX25, and LX45 (Contd)


Pin Description Pin Number K6 G3 G1 J7 J6 F2 F1 H6 H5 E3 E1 F4 F3 D2 D1 H7 G6 E4 D3 F6 F5 C2 C1 A1 A18 B13 B7 C16 C3 D10 D5 E15 G12 BUFIO2 Region LT (LB in LX25) LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT NA NA NA NA NA NA NA NA NA NA No Connect (NC)

IO_L45N_M3ODT_3 IO_L46P_M3CLK_3 IO_L46N_M3CLKN_3 IO_L47P_M3A0_3 IO_L47N_M3A1_3 IO_L48P_M3BA0_3 IO_L48N_M3BA1_3 IO_L49P_M3A7_3 IO_L49N_M3A2_3 IO_L50P_M3WE_3 IO_L50N_M3BA2_3 IO_L51P_M3A10_3 IO_L51N_M3A4_3 IO_L52P_M3A8_3 IO_L52N_M3A9_3 IO_L53P_M3CKE_3 IO_L53N_M3A12_3 IO_L54P_M3RESET_3 IO_L54N_M3A11_3 IO_L55P_M3A13_3 IO_L55N_M3A14_3 IO_L83P_3 IO_L83N_VREF_3 GND GND GND GND GND GND GND GND GND GND

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CSG324 PackageLX9, LX16, LX25, and LX45

Table 2-7:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

CSG324 PackageLX9, LX16, LX25, and LX45 (Contd)


Pin Description Pin Number G17 G2 G5 H10 H8 J11 J15 J4 J9 K10 K8 L11 L9 M17 M2 M6 N13 R1 R14 R18 R4 R9 T16 U12 U6 V1 V18 B1 B17 E14 E5 E9 G10 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX

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Chapter 2: Pinout Tables

Table 2-7:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 0 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2

CSG324 PackageLX9, LX16, LX25, and LX45 (Contd)


Pin Description Pin Number J12 K7 M9 P10 P14 P5 G7 H11 H9 J10 J8 K11 K9 L10 L8 M12 M7 B10 B15 B5 D13 D7 E10 E17 G15 J14 J17 M15 R17 P9 R12 R6 U14 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG324 PackageLX9, LX16, LX25, and LX45

Table 2-7:
Bank 2 2 3 3 3 3 3 3

CSG324 PackageLX9, LX16, LX25, and LX45 (Contd)


Pin Description Pin Number U4 U9 E2 G4 J2 J5 M4 R2 BUFIO2 Region NA NA NA NA NA NA NA NA No Connect (NC)

VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3

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Chapter 2: Pinout Tables

CSG324 PackageLX25T and LX45T


The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/O clock input for the associated pin. For more information see Clock Inputs and BUFIO2 Clocking Regions in Chapter 1.
BUFIO2 Region TL TR RT RB BL BR LT LB Description I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 3 (left). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 3 (left).

Table 2-8:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NA

CSG324 PackageLX25T and LX45T


Pin Description Pin Number B2 A2 B3 A3 E6 F7 G8 E8 G9 G11 F12 E12 C15 A15 B16 A16 E14 D15 A17 BUFIO2 Region TL TL TL TL TL TL TL TL TR TR TR TR TR TR TR TR TR TR NA No Connect (NC)

IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L35N_GCLK16_0 IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 TCK

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CSG324 PackageLX25T and LX45T

Table 2-8:
Bank NA NA NA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CSG324 PackageLX25T and LX45T (Contd)


Pin Description Pin Number F13 B18 D16 F15 F16 C17 C18 F14 G14 D17 D18 H12 G13 E16 E18 K12 K13 F17 F18 H13 H14 H15 H16 G16 G18 J13 K14 L12 L13 K15 K16 L15 L16 BUFIO2 Region NA NA NA RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT (RB in LX25T) RT (RB in LX25T) RT (RB in LX25T) RT (RB in LX25T) RT (RB in LX25T) RT (RB in LX25T) RB RB No Connect (NC)

TDI TMS TDO IO_L1P_A25_1 IO_L1N_A24_VREF_1 IO_L29P_A23_M1A13_1 IO_L29N_A22_M1A14_1 IO_L30P_A21_M1RESET_1 IO_L30N_A20_M1A11_1 IO_L31P_A19_M1CKE_1 IO_L31N_A18_M1A12_1 IO_L32P_A17_M1A8_1 IO_L32N_A16_M1A9_1 IO_L33P_A15_M1A10_1 IO_L33N_A14_M1A4_1 IO_L34P_A13_M1WE_1 IO_L34N_A12_M1BA2_1 IO_L35P_A11_M1A7_1 IO_L35N_A10_M1A2_1 IO_L36P_A9_M1BA0_1 IO_L36N_A8_M1BA1_1 IO_L37P_A7_M1A0_1 IO_L37N_A6_M1A1_1 IO_L38P_A5_M1CLK_1 IO_L38N_A4_M1CLKN_1 IO_L39P_M1A3_1 IO_L39N_M1ODT_1 IO_L40P_GCLK11_M1A5_1 IO_L40N_GCLK10_M1A6_1 IO_L41P_GCLK9_IRDY1_M1RASN_1 IO_L41N_GCLK8_M1CASN_1 IO_L42P_GCLK7_M1UDM_1 IO_L42N_GCLK6_TRDY1_M1LDM_1

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Chapter 2: Pinout Tables

Table 2-8:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NA 2 2 2 2 2 2

CSG324 PackageLX25T and LX45T (Contd)


Pin Description Pin Number H17 H18 J16 J18 K17 K18 L17 L18 M16 M18 N17 N18 P17 P18 N15 N16 T17 T18 U17 U18 M14 N14 L14 M13 P15 P16 R16 P13 V17 R15 T15 U16 V16 BUFIO2 Region RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB NA NA NA BR BR BR BR No Connect (NC)

IO_L43P_GCLK5_M1DQ4_1 IO_L43N_GCLK4_M1DQ5_1 IO_L44P_A3_M1DQ6_1 IO_L44N_A2_M1DQ7_1 IO_L45P_A1_M1LDQS_1 IO_L45N_A0_M1LDQSN_1 IO_L46P_FCS_B_M1DQ2_1 IO_L46N_FOE_B_M1DQ3_1 IO_L47P_FWE_B_M1DQ0_1 IO_L47N_LDC_M1DQ1_1 IO_L48P_HDC_M1DQ8_1 IO_L48N_M1DQ9_1 IO_L49P_M1DQ10_1 IO_L49N_M1DQ11_1 IO_L50P_M1UDQS_1 IO_L50N_M1UDQSN_1 IO_L51P_M1DQ12_1 IO_L51N_M1DQ13_1 IO_L52P_M1DQ14_1 IO_L52N_M1DQ15_1 IO_L53P_1 IO_L53N_VREF_1 IO_L61P_1 IO_L61N_1 IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1 SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2 IO_L2N_CMPMOSI_2

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG324 PackageLX25T and LX45T

Table 2-8:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

CSG324 PackageLX25T and LX45T (Contd)


Pin Description Pin Number R13 T13 U15 V15 T14 V14 N12 P12 U13 V13 M11 N11 R11 T11 T12 V12 N10 P11 M10 N9 U11 V11 R10 T10 U10 V10 R8 T8 T9 V9 M8 N8 U8 BUFIO2 Region BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BL BL BL BL BL BL BL No Connect (NC)

IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L5P_2 IO_L5N_2 IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2 IO_L13P_M1_2 IO_L13N_D10_2 IO_L14P_D11_2 IO_L14N_D12_2 IO_L15P_2 IO_L15N_2 IO_L16P_2 IO_L16N_VREF_2 IO_L19P_2 IO_L19N_2 IO_L20P_2 IO_L20N_2 IO_L22P_2 IO_L22N_2 IO_L23P_2 IO_L23N_2 IO_L29P_GCLK3_2 IO_L29N_GCLK2_2 IO_L30P_GCLK1_D13_2 IO_L30N_GCLK0_USERCCLK_2 IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2 IO_L32P_GCLK29_2 IO_L32N_GCLK28_2 IO_L40P_2 IO_L40N_2 IO_L41P_2

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Chapter 2: Pinout Tables

Table 2-8:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3

CSG324 PackageLX25T and LX45T (Contd)


Pin Description Pin Number V8 U7 V7 N7 P8 T6 V6 R7 T7 N6 P7 R5 T5 U5 V5 R3 T3 T4 V4 N5 P6 U3 V3 V2 N4 N3 P4 P3 L6 M5 U2 U1 T2 BUFIO2 Region BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL NA LB LB LB LB LB LB LB LB LB No Connect (NC)

IO_L41N_VREF_2 IO_L43P_2 IO_L43N_2 IO_L44P_2 IO_L44N_2 IO_L45P_2 IO_L45N_2 IO_L46P_2 IO_L46N_2 IO_L47P_2 IO_L47N_2 IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L49N_D4_2 IO_L62P_D5_2 IO_L62N_D6_2 IO_L63P_2 IO_L63N_2 IO_L64P_D8_2 IO_L64N_D9_2 IO_L65P_INIT_B_2 IO_L65N_CSO_B_2 PROGRAM_B_2 IO_L1P_3 IO_L1N_VREF_3 IO_L2P_3 IO_L2N_3 IO_L31P_3 IO_L31N_VREF_3 IO_L32P_M3DQ14_3 IO_L32N_M3DQ15_3 IO_L33P_M3DQ12_3

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CSG324 PackageLX25T and LX45T

Table 2-8:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

CSG324 PackageLX25T and LX45T (Contd)


Pin Description Pin Number T1 P2 P1 N2 N1 M3 M1 L2 L1 K2 K1 L4 L3 J3 J1 H2 H1 K4 K3 L5 K5 H4 H3 L7 K6 G3 G1 J7 J6 F2 F1 H6 H5 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LT (LB in LX25T) LT (LB in LX25T) LT (LB in LX25T) LT (LB in LX25T) LT (LB in LX25T) LT (LB in LX25T) LT LT LT LT LT LT LT LT No Connect (NC)

IO_L33N_M3DQ13_3 IO_L34P_M3UDQS_3 IO_L34N_M3UDQSN_3 IO_L35P_M3DQ10_3 IO_L35N_M3DQ11_3 IO_L36P_M3DQ8_3 IO_L36N_M3DQ9_3 IO_L37P_M3DQ0_3 IO_L37N_M3DQ1_3 IO_L38P_M3DQ2_3 IO_L38N_M3DQ3_3 IO_L39P_M3LDQS_3 IO_L39N_M3LDQSN_3 IO_L40P_M3DQ6_3 IO_L40N_M3DQ7_3 IO_L41P_GCLK27_M3DQ4_3 IO_L41N_GCLK26_M3DQ5_3 IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L42N_GCLK24_M3LDM_3 IO_L43P_GCLK23_M3RASN_3 IO_L43N_GCLK22_IRDY2_M3CASN_3 IO_L44P_GCLK21_M3A5_3 IO_L44N_GCLK20_M3A6_3 IO_L45P_M3A3_3 IO_L45N_M3ODT_3 IO_L46P_M3CLK_3 IO_L46N_M3CLKN_3 IO_L47P_M3A0_3 IO_L47N_M3A1_3 IO_L48P_M3BA0_3 IO_L48N_M3BA1_3 IO_L49P_M3A7_3 IO_L49N_M3A2_3

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Chapter 2: Pinout Tables

Table 2-8:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 123 123 123

CSG324 PackageLX25T and LX45T (Contd)


Pin Description Pin Number E3 E1 F4 F3 D2 D1 H7 G6 E4 D3 F6 F5 C2 C1 A4 B4 B7 A8 B8 C5 D5 E7 C7 E5 D7 D10 C9 D9 A6 B6 A12 B12 B11 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT LT LT LT LT NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA LX25T LX25T LX25T No Connect (NC)

IO_L50P_M3WE_3 IO_L50N_M3BA2_3 IO_L51P_M3A10_3 IO_L51N_M3A4_3 IO_L52P_M3A8_3 IO_L52N_M3A9_3 IO_L53P_M3CKE_3 IO_L53N_M3A12_3 IO_L54P_M3RESET_3 IO_L54N_M3A11_3 IO_L55P_M3A13_3 IO_L55N_M3A14_3 IO_L83P_3 IO_L83N_VREF_3 MGTTXN0_101 MGTTXP0_101 MGTAVCCPLL0_101 MGTREFCLK0N_101 MGTREFCLK0P_101 MGTRXN0_101 MGTRXP0_101 MGTRREF_101 MGTRXN1_101 MGTAVTTRCAL_101 MGTRXP1_101 MGTAVCCPLL1_101 MGTREFCLK1N_101 MGTREFCLK1P_101 MGTTXN1_101 MGTTXP1_101 MGTTXN0_123 MGTTXP0_123 MGTAVCCPLL0_123

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG324 PackageLX25T and LX45T

Table 2-8:
Bank 123 123 123 123 123 123 123 123 123 123 123 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

CSG324 PackageLX25T and LX45T (Contd)


Pin Description Pin Number A10 B10 C11 D11 C13 D13 E11 E10 F10 A14 B14 A1 A11 A18 A7 A9 B13 B5 B9 C10 C12 C14 C16 C4 C6 D8 E13 E15 F11 F9 G17 G2 G5 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC) LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T

MGTREFCLK0N_123 MGTREFCLK0P_123 MGTRXN0_123 MGTRXP0_123 MGTRXN1_123 MGTRXP1_123 MGTAVCCPLL1_123 MGTREFCLK1N_123 MGTREFCLK1P_123 MGTTXN1_123 MGTTXP1_123 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Chapter 2: Pinout Tables

Table 2-8:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

CSG324 PackageLX25T and LX45T (Contd)


Pin Description Pin Number H10 H8 J11 J15 J4 J9 K10 K8 L11 L9 M17 M2 M6 N13 R1 R14 R18 R4 R9 T16 U12 U6 V1 V18 B1 B17 D14 D4 G10 J12 K7 M9 P10 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG324 PackageLX25T and LX45T

Table 2-8:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA 0 0 0 0 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3

CSG324 PackageLX25T and LX45T (Contd)


Pin Description Pin Number P14 P5 G7 H11 H9 J10 J8 K11 K9 L10 L8 M12 M7 B15 C3 F8 G12 E17 G15 J14 J17 M15 R17 P9 R12 R6 U14 U4 U9 E2 G4 J2 J5 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3

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Chapter 2: Pinout Tables

Table 2-8:
Bank 3 3 101 123 101 123 101 123

CSG324 PackageLX25T and LX45T (Contd)


Pin Description Pin Number M4 R2 A5 A13 D6 D12 C8 E9 BUFIO2 Region NA NA NA NA NA NA NA NA LX25T LX25T LX25T No Connect (NC)

VCCO_3 VCCO_3 MGTAVTTTX_101 MGTAVTTTX_123 MGTAVTTRX_101 MGTAVTTRX_123 MGTAVCC_101 MGTAVCC_123

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150


The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/O clock input for the associated pin. For more information see Clock Inputs and BUFIO2 Clocking Regions in Chapter 1.
BUFIO2 Region TL TR RT RB BL BR LT LB Description I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 3 (left). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 3 (left).

Table 2-9:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150


Pin Description Pin Number A3 A4 C5 A5 D6 C6 B6 A6 C7 A7 B8 A8 D9 C8 C9 A9 E8 F8 G8 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL LX25, LX45, LX75 LX25, LX45, LX75 LX25, LX45, LX75 No Connect (NC)

IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L5P_0 IO_L5N_0 IO_L6P_0 IO_L6N_0 IO_L7P_0 IO_L7N_0 IO_L8P_0 IO_L8N_VREF_0 IO_L14P_0 IO_L14N_0 IO_L15P_0

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

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Chapter 2: Pinout Tables

Table 2-9:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number F9 G9 H10 E10 F10 G11 H11 D7 D8 D10 C10 B10 A10 C11 A11 D11 C12 B12 A12 C13 A13 E12 D12 H12 F12 F13 D13 H13 G13 E14 F15 F14 H14 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TR TR TR TR TR TR TR (TL in LX75) TR (TL in LX75) TR TR TR (TL in LX75) TR (TL in LX75) TR TR TR TR TR TR LX45 LX45 LX45, LX75 LX45, LX75 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 No Connect (NC) LX25, LX45, LX75 LX25, LX45, LX75 LX25, LX45, LX75 LX25, LX45, LX75 LX25, LX45, LX75 LX25, LX45, LX75 LX25, LX45, LX75

IO_L15N_0 IO_L16P_0 IO_L16N_0 IO_L17P_0 IO_L17N_0 IO_L18P_0 IO_L18N_0 IO_L32P_0 IO_L32N_0 IO_L33P_0 IO_L33N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L35N_GCLK16_0 IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L38P_0 IO_L38N_VREF_0 IO_L43P_0 IO_L43N_0 IO_L44P_0 IO_L44N_0 IO_L45P_0 IO_L45N_0 IO_L46P_0 IO_L46N_0 IO_L47P_0 IO_L47N_0 IO_L48P_0 IO_L48N_0

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150

Table 2-9:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NA NA NA NA 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number D14 C14 B14 A14 C15 A15 D15 C16 B16 A16 C17 A17 B18 A18 E16 D17 G15 E18 C18 A19 C19 B20 G16 G17 F16 F17 B21 B22 A20 A21 K16 J16 H16 BUFIO2 Region TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR NA NA NA NA RT RT RT RT RT RT RT RT RT RT RT RT RT LX25 LX25 LX25 LX25 LX25 LX25 LX25 No Connect (NC)

IO_L49P_0 IO_L49N_0 IO_L50P_0 IO_L50N_0 IO_L51P_0 IO_L51N_0 IO_L62P_0 IO_L62N_VREF_0 IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 TCK TDI TMS TDO IO_L1P_A25_1 IO_L1N_A24_VREF_1 IO_L9P_1 IO_L9N_1 IO_L10P_1 IO_L10N_1 IO_L19P_1 IO_L19N_1 IO_L20P_1 IO_L20N_1 IO_L21P_1 IO_L21N_1 IO_L28P_1

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Chapter 2: Pinout Tables

Table 2-9:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number H17 D19 D20 F18 F19 D21 D22 C20 C22 G19 F20 H19 H18 E20 E22 J17 K17 F21 F22 H20 J19 G20 G22 K20 K19 H21 H22 M20 L19 J20 J22 K21 K22 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT (RB in LX25) RT (RB in LX25) RT (RB in LX25) RT (RB in LX25) RT (RB in LX25) RT (RB in LX25) RB RB RB RB RB RB No Connect (NC) LX25

IO_L28N_VREF_1 IO_L29P_A23_M1A13_1 IO_L29N_A22_M1A14_1 IO_L30P_A21_M1RESET_1 IO_L30N_A20_M1A11_1 IO_L31P_A19_M1CKE_1 IO_L31N_A18_M1A12_1 IO_L32P_A17_M1A8_1 IO_L32N_A16_M1A9_1 IO_L33P_A15_M1A10_1 IO_L33N_A14_M1A4_1 IO_L34P_A13_M1WE_1 IO_L34N_A12_M1BA2_1 IO_L35P_A11_M1A7_1 IO_L35N_A10_M1A2_1 IO_L36P_A9_M1BA0_1 IO_L36N_A8_M1BA1_1 IO_L37P_A7_M1A0_1 IO_L37N_A6_M1A1_1 IO_L38P_A5_M1CLK_1 IO_L38N_A4_M1CLKN_1 IO_L39P_M1A3_1 IO_L39N_M1ODT_1 IO_L40P_GCLK11_M1A5_1 IO_L40N_GCLK10_M1A6_1 IO_L41P_GCLK9_IRDY1_M1RASN_1 IO_L41N_GCLK8_M1CASN_1 IO_L42P_GCLK7_M1UDM_1 IO_L42N_GCLK6_TRDY1_M1LDM_1 IO_L43P_GCLK5_M1DQ4_1 IO_L43N_GCLK4_M1DQ5_1 IO_L44P_A3_M1DQ6_1 IO_L44N_A2_M1DQ7_1

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150

Table 2-9:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number L20 L22 M21 M22 N20 N22 P21 P22 R20 R22 T21 T22 U20 U22 V21 V22 M19 N19 M16 L15 P19 P20 W20 W22 L17 K18 U19 V20 M17 M18 P17 N16 P18 BUFIO2 Region RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 No Connect (NC)

IO_L45P_A1_M1LDQS_1 IO_L45N_A0_M1LDQSN_1 IO_L46P_FCS_B_M1DQ2_1 IO_L46N_FOE_B_M1DQ3_1 IO_L47P_FWE_B_M1DQ0_1 IO_L47N_LDC_M1DQ1_1 IO_L48P_HDC_M1DQ8_1 IO_L48N_M1DQ9_1 IO_L49P_M1DQ10_1 IO_L49N_M1DQ11_1 IO_L50P_M1UDQS_1 IO_L50N_M1UDQSN_1 IO_L51P_M1DQ12_1 IO_L51N_M1DQ13_1 IO_L52P_M1DQ14_1 IO_L52N_M1DQ15_1 IO_L53P_1 IO_L53N_VREF_1 IO_L58P_1 IO_L58N_1 IO_L59P_1 IO_L59N_1 IO_L60P_1 IO_L60N_1 IO_L61P_1 IO_L61N_1 IO_L70P_1 IO_L70N_1 IO_L71P_1 IO_L71N_1 IO_L72P_1 IO_L72N_1 IO_L73P_1

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Chapter 2: Pinout Tables

Table 2-9:
Bank 1 1 1 NA NA NA NA 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number R19 T19 T20 P16 P15 R17 N15 Y20 Y22 Y21 AA22 AA21 AB21 AA20 AB20 T18 T17 Y19 AB19 W18 Y18 T16 T15 U17 U16 V19 V18 R16 R15 V17 W17 U14 U13 BUFIO2 Region RB RB RB NA NA NA NA NA NA BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR LX75 LX75 LX25, LX75 LX25, LX75 LX25, LX75 LX25, LX75 LX25, LX75 LX25, LX75 LX25, LX75 LX25, LX75 LX25, LX75 LX25, LX75 LX25 LX25 LX25, LX45 LX25, LX45 LX25, LX45 No Connect (NC) LX25

IO_L73N_1 IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1 VFS RFUSE VBATT SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2 IO_L2N_CMPMOSI_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L4P_2 IO_L4N_VREF_2 IO_L5P_2 IO_L5N_2 IO_L6P_2 IO_L6N_2 IO_L7P_2 IO_L7N_2 IO_L8P_2 IO_L8N_2 IO_L9P_2 IO_L9N_2 IO_L10P_2 IO_L10N_2 IO_L11P_2 IO_L11N_2 IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150

Table 2-9:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number U15 V15 AA18 AB18 Y17 AB17 AA14 AB14 Y16 W15 V13 W13 AA16 AB16 W14 Y14 Y15 AB15 T12 U12 T14 R13 W12 Y12 Y13 AB13 AA12 AB12 Y11 AB11 R11 T11 AA10 BUFIO2 Region BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BL BL BL BL BL BL BL LX75 LX75 LX25, LX75, LX100 LX25, LX75, LX100 LX25, LX75 LX25, LX75 LX75 LX75 LX75, LX100 LX75, LX100 LX75 LX75 No Connect (NC)

IO_L13P_M1_2 IO_L13N_D10_2 IO_L14P_D11_2 IO_L14N_D12_2 IO_L15P_2 IO_L15N_2 IO_L16P_2 IO_L16N_VREF_2 IO_L17P_2 IO_L17N_2 IO_L18P_2 IO_L18N_2 IO_L19P_2 IO_L19N_2 IO_L20P_2 IO_L20N_2 IO_L21P_2 IO_L21N_2 IO_L22P_2 IO_L22N_2 IO_L23P_2 IO_L23N_2 IO_L29P_GCLK3_2 IO_L29N_GCLK2_2 IO_L30P_GCLK1_D13_2 IO_L30N_GCLK0_USERCCLK_2 IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2 IO_L32P_GCLK29_2 IO_L32N_GCLK28_2 IO_L40P_2 IO_L40N_2 IO_L41P_2

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Chapter 2: Pinout Tables

Table 2-9:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number AB10 V11 W11 Y9 AB9 W10 Y10 AA8 AB8 W8 V7 W9 Y8 Y7 AB7 AA6 AB6 U9 V9 T8 U8 T10 U10 W6 Y6 Y5 AB5 AA4 AB4 Y3 AB3 R9 R8 BUFIO2 Region BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL LX75 LX75 LX75 LX75 LX25, LX75, LX100 LX25, LX75, LX100 LX25, LX75, LX100 LX25, LX75, LX100 LX75, LX100 LX75, LX100 LX75, LX100 LX75, LX100 LX75 LX75 LX75 LX75 LX75 LX75 No Connect (NC)

IO_L41N_VREF_2 IO_L42P_2 IO_L42N_2 IO_L43P_2 IO_L43N_2 IO_L44P_2 IO_L44N_2 IO_L45P_2 IO_L45N_2 IO_L46P_2 IO_L46N_2 IO_L47P_2 IO_L47N_2 IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L49N_D4_2 IO_L50P_2 IO_L50N_2 IO_L51P_2 IO_L51N_2 IO_L52P_2 IO_L52N_2 IO_L53P_2 IO_L53N_2 IO_L54P_2 IO_L54N_2 IO_L57P_2 IO_L57N_2 IO_L58P_2 IO_L58N_2 IO_L59P_2 IO_L59N_2

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150

Table 2-9:
Bank 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number T7 R7 W4 Y4 U6 V5 AA2 AB2 T6 T5 AA1 Y2 Y1 W3 W1 P8 P7 P6 P5 T4 T3 U4 V3 N6 N7 M7 M8 R4 P4 M6 L6 P3 N4 BUFIO2 Region BL BL BL BL BL BL BL BL BL BL NA LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX75 LX75 No Connect (NC) LX75 LX75

IO_L60P_2 IO_L60N_2 IO_L62P_D5_2 IO_L62N_D6_2 IO_L63P_2 IO_L63N_2 IO_L64P_D8_2 IO_L64N_D9_2 IO_L65P_INIT_B_2 IO_L65N_CSO_B_2 PROGRAM_B_2 IO_L1P_3 IO_L1N_VREF_3 IO_L2P_3 IO_L2N_3 IO_L7P_3 IO_L7N_3 IO_L8P_3 IO_L8N_3 IO_L9P_3 IO_L9N_3 IO_L10P_3 IO_L10N_3 IO_L11P_3 IO_L11N_3 IO_L23P_3 IO_L23N_3 IO_L24P_3 IO_L24N_3 IO_L25P_3 IO_L25N_3 IO_L26P_3 IO_L26N_3

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Chapter 2: Pinout Tables

Table 2-9:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number M5 M4 V2 V1 U3 U1 T2 T1 R3 R1 P2 P1 N3 N1 M2 M1 L3 L1 K2 K1 J3 J1 M3 L4 K5 K4 K3 J4 K6 J6 H4 H3 H2 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LT (LB in LX25) LT (LB in LX25) LT (LB in LX25) LT (LB in LX25) LT (LB in LX25) LT (LB in LX25) LT LT LT No Connect (NC)

IO_L31P_3 IO_L31N_VREF_3 IO_L32P_M3DQ14_3 IO_L32N_M3DQ15_3 IO_L33P_M3DQ12_3 IO_L33N_M3DQ13_3 IO_L34P_M3UDQS_3 IO_L34N_M3UDQSN_3 IO_L35P_M3DQ10_3 IO_L35N_M3DQ11_3 IO_L36P_M3DQ8_3 IO_L36N_M3DQ9_3 IO_L37P_M3DQ0_3 IO_L37N_M3DQ1_3 IO_L38P_M3DQ2_3 IO_L38N_M3DQ3_3 IO_L39P_M3LDQS_3 IO_L39N_M3LDQSN_3 IO_L40P_M3DQ6_3 IO_L40N_M3DQ7_3 IO_L41P_GCLK27_M3DQ4_3 IO_L41N_GCLK26_M3DQ5_3 IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L42N_GCLK24_M3LDM_3 IO_L43P_GCLK23_M3RASN_3 IO_L43N_GCLK22_IRDY2_M3CASN_3 IO_L44P_GCLK21_M3A5_3 IO_L44N_GCLK20_M3A6_3 IO_L45P_M3A3_3 IO_L45N_M3ODT_3 IO_L46P_M3CLK_3 IO_L46N_M3CLKN_3 IO_L47P_M3A0_3

96

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150

Table 2-9:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number H1 G3 G1 H6 H5 F2 F1 G4 F3 E3 E1 D2 D1 C3 C1 G6 F5 K7 K8 D5 E4 J7 H8 B2 B1 G7 F7 D3 C4 E5 E6 A2 B3 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 LX25 No Connect (NC)

IO_L47N_M3A1_3 IO_L48P_M3BA0_3 IO_L48N_M3BA1_3 IO_L49P_M3A7_3 IO_L49N_M3A2_3 IO_L50P_M3WE_3 IO_L50N_M3BA2_3 IO_L51P_M3A10_3 IO_L51N_M3A4_3 IO_L52P_M3A8_3 IO_L52N_M3A9_3 IO_L53P_M3CKE_3 IO_L53N_M3A12_3 IO_L54P_M3RESET_3 IO_L54N_M3A11_3 IO_L55P_M3A13_3 IO_L55N_M3A14_3 IO_L57P_3 IO_L57N_VREF_3 IO_L58P_3 IO_L58N_3 IO_L59P_3 IO_L59N_3 IO_L60P_3 IO_L60N_3 IO_L80P_3 IO_L80N_3 IO_L81P_3 IO_L81N_3 IO_L82P_3 IO_L82N_3 IO_L83P_3 IO_L83N_VREF_3

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Chapter 2: Pinout Tables

Table 2-9:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number A1 A22 AA13 AA17 AA5 AA9 AB1 AB22 B13 B17 B5 B9 D18 D4 E11 E15 E2 E21 E7 G18 G5 H7 J11 J13 J15 J2 J21 J9 K10 K12 K14 L11 L13 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150

Table 2-9:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number L18 L5 L9 M10 M12 M14 N11 N13 N17 N2 N21 N9 P10 P12 P14 R18 R5 U2 U21 U7 V10 V14 V4 W16 W19 W7 D16 F11 G12 H15 H9 K15 L8 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX

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Chapter 2: Pinout Tables

Table 2-9:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 0 0 0 0 0 0

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number M15 N8 R10 R12 R6 U11 V6 J10 J12 J14 J8 K11 K13 K9 L10 L12 L14 M11 M13 M9 N10 N12 N14 P11 P13 P9 R14 B11 B15 B19 B4 B7 E13 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0

100

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150

Table 2-9:
Bank 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number E17 E9 G10 G14 C21 E19 G21 J18 L16 L21 N18 R21 U18 W21 AA11 AA15 AA19 AA3 AA7 T13 T9 V12 V16 V8 W5 C2 F4 F6 G2 J5 L2 L7 N5 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3

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101

Chapter 2: Pinout Tables

Table 2-9:
Bank 3 3 3

FG(G)484 PackageLX25, LX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number R2 U5 W2 BUFIO2 Region NA NA NA No Connect (NC)

VCCO_3 VCCO_3 VCCO_3

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T


The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/O clock input for the associated pin. For more information see Clock Inputs and BUFIO2 Clocking Regions in Chapter 1.
BUFIO2 Region TL TR RT RB BL BR LT LB Description I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 3 (left). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 3 (left).

Table 2-10:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 101 101 101

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T


Pin Description Pin Number C3 D3 D4 D5 B2 A2 E5 E6 B3 A3 C4 A4 F7 F8 C5 A5 A6 B6 B9 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL NA NA NA No Connect (NC)

IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L5P_0 IO_L5N_0 IO_L6P_0 IO_L6N_0 IO_L7P_0 IO_L7N_0 IO_L8P_0 IO_L8N_VREF_0 MGTTXN0_101 MGTTXP0_101 MGTAVCCPLL0_101

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Table 2-10:
Bank 101 101 101 101 101 101 101 101 101 101 101 101 101 0 0 0 0 0 0 0 0 0 0 0 0 0 0 123 123 123 123 123 123

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number B10 A10 C7 D7 E9 C9 E8 D9 D12 D11 C11 A8 B8 G8 F9 H10 H11 G9 F10 H12 G11 F14 F15 E16 F16 H13 G13 A14 B14 B13 B12 A12 C13 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA TL TL TL TL TL TL TL TL TR TR TR TR TR TR NA NA NA NA NA NA LX25T LX25T LX25T LX25T LX25T LX25T No Connect (NC)

MGTREFCLK0N_101 MGTREFCLK0P_101 MGTRXN0_101 MGTRXP0_101 MGTRREF_101 MGTRXN1_101 MGTAVTTRCAL_101 MGTRXP1_101 MGTAVCCPLL1_101 MGTREFCLK1N_101 MGTREFCLK1P_101 MGTTXN1_101 MGTTXP1_101 IO_L32P_0 IO_L32N_0 IO_L33P_0 IO_L33N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L35N_GCLK16_0 IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L38P_0 IO_L38N_VREF_0 MGTTXN0_123 MGTTXP0_123 MGTAVCCPLL0_123 MGTREFCLK0N_123 MGTREFCLK0P_123 MGTRXN0_123

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FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T

Table 2-10:
Bank 123 123 123 123 123 123 123 123 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NA NA NA NA 1 1 1 1 1

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number D13 C15 D15 E13 F12 E12 A16 B16 H14 G15 C17 A17 G16 F17 D18 D19 B18 A18 C19 A19 B20 A20 D17 C18 A21 E18 D20 G17 F18 F19 H16 H17 B21 BUFIO2 Region NA NA NA NA NA NA NA NA TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR NA NA NA NA RT RT RT RT RT LX25T LX25T LX25T No Connect (NC) LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T

MGTRXP0_123 MGTRXN1_123 MGTRXP1_123 MGTAVCCPLL1_123 MGTREFCLK1N_123 MGTREFCLK1P_123 MGTTXN1_123 MGTTXP1_123 IO_L49P_0 IO_L49N_0 IO_L50P_0 IO_L50N_0 IO_L51P_0 IO_L51N_0 IO_L62P_0 IO_L62N_VREF_0 IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 TCK TDI TMS TDO IO_L1P_A25_1 IO_L1N_A24_VREF_1 IO_L9P_1 IO_L9N_1 IO_L10P_1

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Table 2-10:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number B22 J16 J17 C20 C22 L15 K16 D21 D22 G19 F20 H18 H19 F21 F22 E20 E22 J19 H20 K19 K18 G20 G22 K17 L17 H21 H22 K20 L19 J20 J22 M20 M19 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT (RB in LX25T) RT (RB in LX25T) RT (RB in LX25T) RT (RB in LX25T) LX25T LX25T LX25T LX25T No Connect (NC) LX25T

IO_L10N_1 IO_L19P_1 IO_L19N_1 IO_L20P_1 IO_L20N_1 IO_L21P_1 IO_L21N_1 IO_L28P_1 IO_L28N_VREF_1 IO_L29P_A23_M1A13_1 IO_L29N_A22_M1A14_1 IO_L30P_A21_M1RESET_1 IO_L30N_A20_M1A11_1 IO_L31P_A19_M1CKE_1 IO_L31N_A18_M1A12_1 IO_L32P_A17_M1A8_1 IO_L32N_A16_M1A9_1 IO_L33P_A15_M1A10_1 IO_L33N_A14_M1A4_1 IO_L34P_A13_M1WE_1 IO_L34N_A12_M1BA2_1 IO_L35P_A11_M1A7_1 IO_L35N_A10_M1A2_1 IO_L36P_A9_M1BA0_1 IO_L36N_A8_M1BA1_1 IO_L37P_A7_M1A0_1 IO_L37N_A6_M1A1_1 IO_L38P_A5_M1CLK_1 IO_L38N_A4_M1CLKN_1 IO_L39P_M1A3_1 IO_L39N_M1ODT_1 IO_L40P_GCLK11_M1A5_1 IO_L40N_GCLK10_M1A6_1

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T

Table 2-10:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number K21 K22 P20 N19 L20 L22 M21 M22 N20 N22 P21 P22 R20 R22 T21 T22 U20 U22 V21 V22 W20 W22 Y21 Y22 P19 R19 M16 N15 U19 T20 N16 P16 M17 BUFIO2 Region RT (RB in LX25T) RT (RB in LX25T) RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB LX25T LX25T No Connect (NC)

IO_L41P_GCLK9_IRDY1_M1RASN_1 IO_L41N_GCLK8_M1CASN_1 IO_L42P_GCLK7_M1UDM_1 IO_L42N_GCLK6_TRDY1_M1LDM_1 IO_L43P_GCLK5_M1DQ4_1 IO_L43N_GCLK4_M1DQ5_1 IO_L44P_A3_M1DQ6_1 IO_L44N_A2_M1DQ7_1 IO_L45P_A1_M1LDQS_1 IO_L45N_A0_M1LDQSN_1 IO_L46P_FCS_B_M1DQ2_1 IO_L46N_FOE_B_M1DQ3_1 IO_L47P_FWE_B_M1DQ0_1 IO_L47N_LDC_M1DQ1_1 IO_L48P_HDC_M1DQ8_1 IO_L48N_M1DQ9_1 IO_L49P_M1DQ10_1 IO_L49N_M1DQ11_1 IO_L50P_M1UDQS_1 IO_L50N_M1UDQSN_1 IO_L51P_M1DQ12_1 IO_L51N_M1DQ13_1 IO_L52P_M1DQ14_1 IO_L52N_M1DQ15_1 IO_L53P_1 IO_L53N_VREF_1 IO_L58P_1 IO_L58N_1 IO_L59P_1 IO_L59N_1 IO_L60P_1 IO_L60N_1 IO_L61P_1

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Chapter 2: Pinout Tables

Table 2-10:
Bank 1 1 1 1 1 1 1 1 1 1 1 NA NA NA NA 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number M18 R15 R16 P17 P18 R17 T17 T19 T18 V19 V20 U17 P15 T16 AA22 V18 AB21 Y20 AA21 V17 W18 AA20 AB20 U16 V15 W17 Y18 AA14 AB14 R13 T14 Y19 AB19 BUFIO2 Region RB RB RB RB RB RB RB RB RB RB RB NA NA NA NA NA NA BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR LX25T LX25T LX75T LX75T LX25T, LX45T LX25T, LX45T LX25T, LX45T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T No Connect (NC)

IO_L61N_1 IO_L70P_1 IO_L70N_1 IO_L71P_1 IO_L71N_1 IO_L72P_1 IO_L72N_1 IO_L73P_1 IO_L73N_1 IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1 VFS RFUSE VBATT SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2 IO_L2N_CMPMOSI_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L4P_2 IO_L4N_VREF_2 IO_L5P_2 IO_L5N_2 IO_L6P_2 IO_L6N_2 IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2 IO_L13P_M1_2 IO_L13N_D10_2

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T

Table 2-10:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number AA18 AB18 Y17 AB17 U14 U13 Y16 W15 V13 W13 AA16 AB16 W14 Y14 Y15 AB15 R11 T11 T15 U15 T12 U12 Y13 AB13 AA12 AB12 Y11 AB11 W12 Y12 AA10 AB10 V11 BUFIO2 Region BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BL BL BL BL BL BL BL BL BL LX75T LX25T, LX75T LX25T, LX75T LX25T, LX75T LX25T, LX75T LX75T LX75T LX75T LX75T LX75T LX75T No Connect (NC)

IO_L14P_D11_2 IO_L14N_D12_2 IO_L15P_2 IO_L15N_2 IO_L16P_2 IO_L16N_VREF_2 IO_L17P_2 IO_L17N_2 IO_L18P_2 IO_L18N_2 IO_L19P_2 IO_L19N_2 IO_L20P_2 IO_L20N_2 IO_L21P_2 IO_L21N_2 IO_L22P_2 IO_L22N_2 IO_L23P_2 IO_L23N_2 IO_L29P_GCLK3_2 IO_L29N_GCLK2_2 IO_L30P_GCLK1_D13_2 IO_L30N_GCLK0_USERCCLK_2 IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2 IO_L32P_GCLK29_2 IO_L32N_GCLK28_2 IO_L40P_2 IO_L40N_2 IO_L41P_2 IO_L41N_VREF_2 IO_L42P_2

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109

Chapter 2: Pinout Tables

Table 2-10:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number W11 Y9 AB9 W10 Y10 AA8 AB8 T10 U10 Y7 AB7 W9 Y8 AA6 AB6 U9 V9 T8 U8 V7 W8 R9 R8 W6 Y6 Y5 AB5 AA4 AB4 T7 U6 Y4 AA3 BUFIO2 Region BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL LX75T LX75T LX75T LX75T LX75T LX75T LX75T LX75T LX75T LX75T LX75T LX75T LX75T LX75T No Connect (NC) LX75T

IO_L42N_2 IO_L43P_2 IO_L43N_2 IO_L44P_2 IO_L44N_2 IO_L45P_2 IO_L45N_2 IO_L46P_2 IO_L46N_2 IO_L47P_2 IO_L47N_2 IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L49N_D4_2 IO_L50P_2 IO_L50N_2 IO_L57P_2 IO_L57N_2 IO_L58P_2 IO_L58N_2 IO_L59P_2 IO_L59N_2 IO_L60P_2 IO_L60N_2 IO_L62P_D5_2 IO_L62N_D6_2 IO_L63P_2 IO_L63N_2 IO_L64P_D8_2 IO_L64N_D9_2 IO_L65P_INIT_B_2 IO_L65N_CSO_B_2

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T

Table 2-10:
Bank 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number AB2 R7 P8 W4 Y3 T6 T5 V5 V3 P5 P4 AA2 AA1 N6 N7 U4 T4 P6 P7 T3 R4 M7 M8 Y2 Y1 W3 W1 V2 V1 U3 U1 T2 T1 BUFIO2 Region NA LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T No Connect (NC)

PROGRAM_B_2 IO_L1P_3 IO_L1N_VREF_3 IO_L2P_3 IO_L2N_3 IO_L7P_3 IO_L7N_3 IO_L8P_3 IO_L8N_3 IO_L9P_3 IO_L9N_3 IO_L10P_3 IO_L10N_3 IO_L23P_3 IO_L23N_3 IO_L24P_3 IO_L24N_3 IO_L25P_3 IO_L25N_3 IO_L26P_3 IO_L26N_3 IO_L31P_3 IO_L31N_VREF_3 IO_L32P_M3DQ14_3 IO_L32N_M3DQ15_3 IO_L33P_M3DQ12_3 IO_L33N_M3DQ13_3 IO_L34P_M3UDQS_3 IO_L34N_M3UDQSN_3 IO_L35P_M3DQ10_3 IO_L35N_M3DQ11_3 IO_L36P_M3DQ8_3 IO_L36N_M3DQ9_3

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Chapter 2: Pinout Tables

Table 2-10:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number R3 R1 P2 P1 N3 N1 M2 M1 L3 L1 P3 N4 M5 M4 M3 L4 M6 L6 K4 K3 K2 K1 J3 J1 K6 K5 H2 H1 J4 H3 G3 G1 F2 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT No Connect (NC)

IO_L37P_M3DQ0_3 IO_L37N_M3DQ1_3 IO_L38P_M3DQ2_3 IO_L38N_M3DQ3_3 IO_L39P_M3LDQS_3 IO_L39N_M3LDQSN_3 IO_L40P_M3DQ6_3 IO_L40N_M3DQ7_3 IO_L41P_GCLK27_M3DQ4_3 IO_L41N_GCLK26_M3DQ5_3 IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L42N_GCLK24_M3LDM_3 IO_L43P_GCLK23_M3RASN_3 IO_L43N_GCLK22_IRDY2_M3CASN_3 IO_L44P_GCLK21_M3A5_3 IO_L44N_GCLK20_M3A6_3 IO_L45P_M3A3_3 IO_L45N_M3ODT_3 IO_L46P_M3CLK_3 IO_L46N_M3CLKN_3 IO_L47P_M3A0_3 IO_L47N_M3A1_3 IO_L48P_M3BA0_3 IO_L48N_M3BA1_3 IO_L49P_M3A7_3 IO_L49N_M3A2_3 IO_L50P_M3WE_3 IO_L50N_M3BA2_3 IO_L51P_M3A10_3 IO_L51N_M3A4_3 IO_L52P_M3A8_3 IO_L52N_M3A9_3 IO_L53P_M3CKE_3

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T

Table 2-10:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number F1 E3 E1 J6 H5 K7 K8 H4 G4 D2 D1 F3 E4 H6 G7 J7 H8 F5 G6 C1 B1 A1 A11 A13 A22 A9 AA13 AA17 AA5 AA9 AB1 AB22 B11 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT NA NA NA NA NA NA NA NA NA NA NA NA LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T LX25T No Connect (NC)

IO_L53N_M3A12_3 IO_L54P_M3RESET_3 IO_L54N_M3A11_3 IO_L55P_M3A13_3 IO_L55N_M3A14_3 IO_L57P_3 IO_L57N_VREF_3 IO_L58P_3 IO_L58N_3 IO_L59P_3 IO_L59N_3 IO_L60P_3 IO_L60N_3 IO_L80P_3 IO_L80N_3 IO_L81P_3 IO_L81N_3 IO_L82P_3 IO_L82N_3 IO_L83P_3 IO_L83N_VREF_3 GND GND GND GND GND GND GND GND GND GND GND GND

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Chapter 2: Pinout Tables

Table 2-10:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number B15 B17 B5 B7 C12 C14 C16 C6 C8 D10 D16 D6 E11 E14 E15 E2 E21 E7 F13 G18 G5 H7 J11 J13 J15 J2 J21 J9 K10 K12 K14 L11 L13 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T

Table 2-10:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 101 123 101 123 101 123 NA

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number L18 L5 L9 M10 M12 M14 N11 N13 N17 N2 N21 N9 P10 P12 P14 R18 R5 U2 U21 U7 V10 V14 V4 W16 W19 W7 C10 E10 D8 D14 A7 A15 F11 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA LX25T LX25T LX25T No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND MGTAVCC_101 MGTAVCC_123 MGTAVTTRX_101 MGTAVTTRX_123 MGTAVTTTX_101 MGTAVTTTX_123 VCCAUX

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Chapter 2: Pinout Tables

Table 2-10:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 0

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number G12 H15 H9 K15 L8 M15 N8 R10 R12 R6 U11 V6 J10 J12 J14 J8 K11 K13 K9 L10 L12 L14 M11 M13 M9 N10 N12 N14 P11 P13 P9 R14 B19 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCO_0

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T

Table 2-10:
Bank 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number B4 E17 F6 G10 G14 C21 E19 G21 J18 L16 L21 N18 R21 U18 W21 AA11 AA15 AA19 AA7 AB3 T13 T9 V12 V16 V8 W5 C2 F4 G2 J5 L2 L7 N5 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3

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Table 2-10:
Bank 3 3 3

FG(G)484 PackageLX25T, LX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number R2 U5 W2 BUFIO2 Region NA NA NA No Connect (NC)

VCCO_3 VCCO_3 VCCO_3

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CS(G)484 PackageLX45, LX75, LX100, and LX150

CS(G)484 PackageLX45, LX75, LX100, and LX150


The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/O clock input for the associated pin. For more information see Clock Inputs and BUFIO2 Clocking Regions in Chapter 1.
BUFIO2 Region TL TR RT RB BL BR LT LB Description I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 3 (left). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 3 (left).

Table 2-11:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CS(G)484 PackageLX45, LX75, LX100, and LX150


Pin Description Pin Number B3 A4 C5 A5 D6 C6 B6 A6 C7 A7 B8 A8 D7 C8 C9 A9 F9 E8 H10 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL LX45 LX45 LX45 No Connect (NC)

IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L5P_0 IO_L5N_0 IO_L6P_0 IO_L6N_0 IO_L7P_0 IO_L7N_0 IO_L8P_0 IO_L8N_VREF_0 IO_L15P_0 IO_L15N_0 IO_L16P_0

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Table 2-11:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CS(G)484 PackageLX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number G9 D9 D8 D10 C10 B10 A10 C11 A11 B12 A12 D11 C12 F10 E10 D15 C14 D13 D12 C13 A13 F12 E12 B14 A14 H11 G11 C15 A15 B16 A16 C17 A17 BUFIO2 Region TL TL TL TL TL TL TL TL TL TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR LX45 LX45 LX45 LX45 LX45 LX45 No Connect (NC) LX45

IO_L16N_0 IO_L32P_0 IO_L32N_0 IO_L33P_0 IO_L33N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L35N_GCLK16_0 IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L38P_0 IO_L38N_VREF_0 IO_L46P_0 IO_L46N_0 IO_L47P_0 IO_L47N_0 IO_L48P_0 IO_L48N_0 IO_L49P_0 IO_L49N_0 IO_L50P_0 IO_L50N_0 IO_L51P_0 IO_L51N_0 IO_L62P_0 IO_L62N_VREF_0 IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0

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CS(G)484 PackageLX45, LX75, LX100, and LX150

Table 2-11:
Bank 0 0 0 0 NA NA NA NA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CS(G)484 PackageLX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number D17 C16 B18 A18 D14 E18 E16 E14 F15 F16 F13 F14 G15 G16 D19 D20 C18 C19 G17 G19 B20 A21 F17 F18 A19 A20 H17 H18 F19 F20 H12 G13 J16 BUFIO2 Region TR TR TR TR NA NA NA NA RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT No Connect (NC)

IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 TCK TDI TMS TDO IO_L1P_A25_1 IO_L1N_A24_VREF_1 IO_L9P_1 IO_L9N_1 IO_L10P_1 IO_L10N_1 IO_L11P_1 IO_L11N_1 IO_L12P_1 IO_L12N_1 IO_L13P_1 IO_L13N_1 IO_L14P_1 IO_L14N_1 IO_L15P_1 IO_L15N_1 IO_L16P_1 IO_L16N_1 IO_L17P_1 IO_L17N_1 IO_L18P_1 IO_L18N_1 IO_L19P_1 IO_L19N_1 IO_L20P_1

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Table 2-11:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CS(G)484 PackageLX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number H16 H13 H14 L15 K16 F21 F22 H19 H20 E20 E22 G20 G22 D21 D22 H21 H22 C20 C22 K18 K19 B21 B22 J17 J19 J21 J22 L17 K17 M18 M19 L19 K20 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RB RB No Connect (NC)

IO_L20N_1 IO_L21P_1 IO_L21N_1 IO_L28P_1 IO_L28N_VREF_1 IO_L29P_A23_M1A13_1 IO_L29N_A22_M1A14_1 IO_L30P_A21_M1RESET_1 IO_L30N_A20_M1A11_1 IO_L31P_A19_M1CKE_1 IO_L31N_A18_M1A12_1 IO_L32P_A17_M1A8_1 IO_L32N_A16_M1A9_1 IO_L33P_A15_M1A10_1 IO_L33N_A14_M1A4_1 IO_L34P_A13_M1WE_1 IO_L34N_A12_M1BA2_1 IO_L35P_A11_M1A7_1 IO_L35N_A10_M1A2_1 IO_L36P_A9_M1BA0_1 IO_L36N_A8_M1BA1_1 IO_L37P_A7_M1A0_1 IO_L37N_A6_M1A1_1 IO_L38P_A5_M1CLK_1 IO_L38N_A4_M1CLKN_1 IO_L39P_M1A3_1 IO_L39N_M1ODT_1 IO_L40P_GCLK11_M1A5_1 IO_L40N_GCLK10_M1A6_1 IO_L41P_GCLK9_IRDY1_M1RASN_1 IO_L41N_GCLK8_M1CASN_1 IO_L42P_GCLK7_M1UDM_1 IO_L42N_GCLK6_TRDY1_M1LDM_1

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CS(G)484 PackageLX45, LX75, LX100, and LX150

Table 2-11:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CS(G)484 PackageLX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number L20 L22 K21 K22 M21 M22 N19 M20 N20 N22 P21 P22 R20 R22 T21 T22 U20 U22 V21 V22 W20 W22 M16 M17 Y21 Y22 N15 N16 AA20 AB21 P15 P16 AA21 BUFIO2 Region RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB No Connect (NC)

IO_L43P_GCLK5_M1DQ4_1 IO_L43N_GCLK4_M1DQ5_1 IO_L44P_A3_M1DQ6_1 IO_L44N_A2_M1DQ7_1 IO_L45P_A1_M1LDQS_1 IO_L45N_A0_M1LDQSN_1 IO_L46P_FCS_B_M1DQ2_1 IO_L46N_FOE_B_M1DQ3_1 IO_L47P_FWE_B_M1DQ0_1 IO_L47N_LDC_M1DQ1_1 IO_L48P_HDC_M1DQ8_1 IO_L48N_M1DQ9_1 IO_L49P_M1DQ10_1 IO_L49N_M1DQ11_1 IO_L50P_M1UDQS_1 IO_L50N_M1UDQSN_1 IO_L51P_M1DQ12_1 IO_L51N_M1DQ13_1 IO_L52P_M1DQ14_1 IO_L52N_M1DQ15_1 IO_L53P_1 IO_L53N_VREF_1 IO_L58P_1 IO_L58N_1 IO_L59P_1 IO_L59N_1 IO_L60P_1 IO_L60N_1 IO_L61P_1 IO_L61N_1 IO_L62P_1 IO_L62N_1 IO_L63P_1

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Table 2-11:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NA NA NA NA 2 2 2 2 2 2 2 2

CS(G)484 PackageLX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number AA22 P19 P20 AB19 AB20 P17 P18 Y19 Y20 R15 R16 R17 R19 V19 V20 T17 T18 V17 V18 T19 T20 U19 T16 U17 W18 T15 U16 W17 Y18 AA18 AB18 Y17 AB17 BUFIO2 Region RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB NA NA NA NA NA NA BR BR BR BR BR BR LX45 LX45 LX45 No Connect (NC)

IO_L63N_1 IO_L64P_1 IO_L64N_1 IO_L65P_1 IO_L65N_1 IO_L66P_1 IO_L66N_1 IO_L67P_1 IO_L67N_1 IO_L68P_1 IO_L68N_1 IO_L70P_1 IO_L70N_1 IO_L71P_1 IO_L71N_1 IO_L72P_1 IO_L72N_1 IO_L73P_1 IO_L73N_1 IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1 VFS RFUSE VBATT SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2 IO_L2N_CMPMOSI_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CS(G)484 PackageLX45, LX75, LX100, and LX150

Table 2-11:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

CS(G)484 PackageLX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number AA16 AB16 Y15 AB15 V13 W13 U15 V15 W15 Y16 AA14 AB14 W14 Y14 T14 U14 W11 Y10 AA12 AB12 Y11 AB11 AA10 AB10 R13 U13 T12 U12 Y13 AB13 W12 Y12 R11 BUFIO2 Region BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BL BL BL BL BL BL BL BL BL BL BL BL BL LX75 LX45 LX45 LX45 LX45 No Connect (NC)

IO_L4P_2 IO_L4N_VREF_2 IO_L5P_2 IO_L5N_2 IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2 IO_L13P_M1_2 IO_L13N_D10_2 IO_L14P_D11_2 IO_L14N_D12_2 IO_L15P_2 IO_L15N_2 IO_L16P_2 IO_L16N_VREF_2 IO_L20P_2 IO_L20N_2 IO_L29P_GCLK3_2 IO_L29N_GCLK2_2 IO_L30P_GCLK1_D13_2 IO_L30N_GCLK0_USERCCLK_2 IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2 IO_L32P_GCLK29_2 IO_L32N_GCLK28_2 IO_L33P_2 IO_L33N_2 IO_L34P_2 IO_L34N_2 IO_L41P_2 IO_L41N_VREF_2 IO_L42P_2 IO_L42N_2 IO_L43P_2

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Table 2-11:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3

CS(G)484 PackageLX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number T11 V11 W10 T10 U10 U9 V9 W9 Y8 Y9 AB9 AA8 AB8 V7 W8 W6 Y6 Y7 AB7 AA6 AB6 Y5 AB5 AA1 AA2 AB2 Y2 Y1 W4 Y4 Y3 AB3 W3 BUFIO2 Region BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL NA LB LB LB LB LB LB LB LB LB LX75 LX75 No Connect (NC) LX75 LX75 LX75 LX75 LX75 LX75 LX75

IO_L43N_2 IO_L44P_2 IO_L44N_2 IO_L45P_2 IO_L45N_2 IO_L46P_2 IO_L46N_2 IO_L47P_2 IO_L47N_2 IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L49N_D4_2 IO_L50P_2 IO_L50N_2 IO_L62P_D5_2 IO_L62N_D6_2 IO_L63P_2 IO_L63N_2 IO_L64P_D8_2 IO_L64N_D9_2 IO_L65P_INIT_B_2 IO_L65N_CSO_B_2 PROGRAM_B_2 IO_L1P_3 IO_L1N_VREF_3 IO_L2P_3 IO_L2N_3 IO_L7P_3 IO_L7N_3 IO_L8P_3 IO_L8N_3 IO_L9P_3

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CS(G)484 PackageLX45, LX75, LX100, and LX150

Table 2-11:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

CS(G)484 PackageLX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number W1 U8 T7 T8 R7 AA4 AB4 U6 V5 U4 V3 R9 R8 T6 T5 P4 R4 P6 P5 P8 P7 N7 N6 M8 M7 T4 T3 M6 L6 V2 V1 U3 U1 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LX45 LX45 LX45 LX45 No Connect (NC)

IO_L9N_3 IO_L10P_3 IO_L10N_3 IO_L11P_3 IO_L11N_3 IO_L12P_3 IO_L12N_3 IO_L13P_3 IO_L13N_3 IO_L18P_3 IO_L18N_3 IO_L19P_3 IO_L19N_3 IO_L20P_3 IO_L20N_3 IO_L21P_3 IO_L21N_3 IO_L22P_3 IO_L22N_3 IO_L23P_3 IO_L23N_3 IO_L24P_3 IO_L24N_3 IO_L25P_3 IO_L25N_3 IO_L26P_3 IO_L26N_3 IO_L31P_3 IO_L31N_VREF_3 IO_L32P_M3DQ14_3 IO_L32N_M3DQ15_3 IO_L33P_M3DQ12_3 IO_L33N_M3DQ13_3

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Chapter 2: Pinout Tables

Table 2-11:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

CS(G)484 PackageLX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number T2 T1 R3 R1 P2 P1 N3 N1 M2 M1 L3 L1 K2 K1 J3 J1 H2 H1 N4 P3 G3 G1 M4 M3 F2 F1 M5 L4 E3 E1 K4 K3 D2 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT No Connect (NC)

IO_L34P_M3UDQS_3 IO_L34N_M3UDQSN_3 IO_L35P_M3DQ10_3 IO_L35N_M3DQ11_3 IO_L36P_M3DQ8_3 IO_L36N_M3DQ9_3 IO_L37P_M3DQ0_3 IO_L37N_M3DQ1_3 IO_L38P_M3DQ2_3 IO_L38N_M3DQ3_3 IO_L39P_M3LDQS_3 IO_L39N_M3LDQSN_3 IO_L40P_M3DQ6_3 IO_L40N_M3DQ7_3 IO_L41P_GCLK27_M3DQ4_3 IO_L41N_GCLK26_M3DQ5_3 IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L42N_GCLK24_M3LDM_3 IO_L43P_GCLK23_M3RASN_3 IO_L43N_GCLK22_IRDY2_M3CASN_3 IO_L44P_GCLK21_M3A5_3 IO_L44N_GCLK20_M3A6_3 IO_L45P_M3A3_3 IO_L45N_M3ODT_3 IO_L46P_M3CLK_3 IO_L46N_M3CLKN_3 IO_L47P_M3A0_3 IO_L47N_M3A1_3 IO_L48P_M3BA0_3 IO_L48N_M3BA1_3 IO_L49P_M3A7_3 IO_L49N_M3A2_3 IO_L50P_M3WE_3

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CS(G)484 PackageLX45, LX75, LX100, and LX150

Table 2-11:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

CS(G)484 PackageLX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number D1 K6 K5 C3 C1 J6 J4 B2 B1 H4 H3 H6 H5 H8 J7 K8 K7 E4 F3 G8 G7 G6 G4 F5 E5 F8 F7 C4 D3 E6 D5 A3 A2 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT No Connect (NC)

IO_L50N_M3BA2_3 IO_L51P_M3A10_3 IO_L51N_M3A4_3 IO_L52P_M3A8_3 IO_L52N_M3A9_3 IO_L53P_M3CKE_3 IO_L53N_M3A12_3 IO_L54P_M3RESET_3 IO_L54N_M3A11_3 IO_L55P_M3A13_3 IO_L55N_M3A14_3 IO_L57P_3 IO_L57N_VREF_3 IO_L58P_3 IO_L58N_3 IO_L59P_3 IO_L59N_3 IO_L60P_3 IO_L60N_3 IO_L73P_3 IO_L73N_3 IO_L74P_3 IO_L74N_3 IO_L75P_3 IO_L75N_3 IO_L80P_3 IO_L80N_3 IO_L81P_3 IO_L81N_3 IO_L82P_3 IO_L82N_3 IO_L83P_3 IO_L83N_VREF_3

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Table 2-11:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

CS(G)484 PackageLX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number A1 A22 B5 B9 B13 B17 D4 D18 E2 E7 E11 E15 E21 G5 G18 H7 J2 J9 J11 J13 J15 J20 K10 K12 K14 L5 L9 L11 L13 L18 M10 M12 M14 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CS(G)484 PackageLX45, LX75, LX100, and LX150

Table 2-11:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

CS(G)484 PackageLX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number N2 N9 N11 N13 N17 N21 P10 P12 P14 R5 R18 U2 U7 U21 V4 V10 V14 W7 W16 W19 AA5 AA9 AA13 AA17 AB1 AB22 D16 F11 G12 H9 H15 K15 L8 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX

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Table 2-11:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 0 0 0 0 0 0

CS(G)484 PackageLX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number M15 N8 R6 R10 R12 U11 V6 J8 J10 J12 J14 K9 K11 K13 L10 L12 L14 M9 M11 M13 N10 N12 N14 P9 P11 P13 R14 B4 B7 B11 B15 E9 E13 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CS(G)484 PackageLX45, LX75, LX100, and LX150

Table 2-11:
Bank 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3

CS(G)484 PackageLX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number E17 G10 B19 C21 E19 G14 G21 J18 L16 L21 N18 R21 U18 W21 AA19 T9 T13 V8 V12 V16 AA7 AA11 AA15 C2 F4 F6 G2 J5 L2 L7 N5 R2 U5 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3

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Table 2-11:
Bank 3 3 3

CS(G)484 PackageLX45, LX75, LX100, and LX150 (Contd)


Pin Description Pin Number W2 W5 AA3 BUFIO2 Region NA NA NA No Connect (NC)

VCCO_3 VCCO_3 VCCO_3

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CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T


The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/O clock input for the associated pin. For more information see Clock Inputs and BUFIO2 Clocking Regions in Chapter 1.
BUFIO2 Region TL TR RT RB BL BR LT LB Description I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 3 (left). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 3 (left).

Table 2-12:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T


Pin Description Pin Number B3 A4 C5 A5 F7 E6 E5 D5 G7 G8 F9 E8 G9 F8 H10 G10 F10 F11 H11 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TR No Connect (NC)

IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L5P_0 IO_L5N_0 IO_L6P_0 IO_L6N_0 IO_L7P_0 IO_L7N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L35N_GCLK16_0 IO_L36P_GCLK15_0

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Table 2-12:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NA NA NA NA 1 1 1 1 1 1 1 1

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number G11 G12 F12 H12 H13 H14 G15 G16 F16 E16 D17 C17 A17 B18 A18 B20 A19 D18 C18 D19 D20 C19 F17 E18 H16 G17 G19 J16 K17 A20 A21 H17 H18 BUFIO2 Region TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR NA NA NA NA RT RT RT RT RT RT RT RT No Connect (NC)

IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L38P_0 IO_L38N_VREF_0 IO_L49P_0 IO_L49N_0 IO_L50P_0 IO_L50N_0 IO_L51P_0 IO_L51N_0 IO_L62P_0 IO_L62N_VREF_0 IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 TCK TDI TMS TDO IO_L1P_A25_1 IO_L1N_A24_VREF_1 IO_L15P_1 IO_L15N_1 IO_L16P_1 IO_L16N_1 IO_L17P_1 IO_L17N_1

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CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T

Table 2-12:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number F19 F20 N16 M16 L15 K16 N14 N15 F21 F22 H19 H20 E20 E22 G20 G22 D21 D22 H21 H22 C20 C22 K18 K19 B21 B22 J17 J19 J20 J22 M17 L17 M18 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT No Connect (NC)

IO_L18P_1 IO_L18N_1 IO_L19P_1 IO_L19N_1 IO_L20P_1 IO_L20N_1 IO_L28P_1 IO_L28N_VREF_1 IO_L29P_A23_M1A13_1 IO_L29N_A22_M1A14_1 IO_L30P_A21_M1RESET_1 IO_L30N_A20_M1A11_1 IO_L31P_A19_M1CKE_1 IO_L31N_A18_M1A12_1 IO_L32P_A17_M1A8_1 IO_L32N_A16_M1A9_1 IO_L33P_A15_M1A10_1 IO_L33N_A14_M1A4_1 IO_L34P_A13_M1WE_1 IO_L34N_A12_M1BA2_1 IO_L35P_A11_M1A7_1 IO_L35N_A10_M1A2_1 IO_L36P_A9_M1BA0_1 IO_L36N_A8_M1BA1_1 IO_L37P_A7_M1A0_1 IO_L37N_A6_M1A1_1 IO_L38P_A5_M1CLK_1 IO_L38N_A4_M1CLKN_1 IO_L39P_M1A3_1 IO_L39N_M1ODT_1 IO_L40P_GCLK11_M1A5_1 IO_L40N_GCLK10_M1A6_1 IO_L41P_GCLK9_IRDY1_M1RASN_1

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Table 2-12:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number M19 L19 K20 L20 L22 K21 K22 M21 M22 N19 M20 N20 N22 P21 P22 R20 R22 T21 T22 U20 U22 V21 V22 AA21 AA22 R12 R13 W20 W22 T12 T13 AA20 AB21 BUFIO2 Region RT RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB No Connect (NC)

IO_L41N_GCLK8_M1CASN_1 IO_L42P_GCLK7_M1UDM_1 IO_L42N_GCLK6_TRDY1_M1LDM_1 IO_L43P_GCLK5_M1DQ4_1 IO_L43N_GCLK4_M1DQ5_1 IO_L44P_A3_M1DQ6_1 IO_L44N_A2_M1DQ7_1 IO_L45P_A1_M1LDQS_1 IO_L45N_A0_M1LDQSN_1 IO_L46P_FCS_B_M1DQ2_1 IO_L46N_FOE_B_M1DQ3_1 IO_L47P_FWE_B_M1DQ0_1 IO_L47N_LDC_M1DQ1_1 IO_L48P_HDC_M1DQ8_1 IO_L48N_M1DQ9_1 IO_L49P_M1DQ10_1 IO_L49N_M1DQ11_1 IO_L50P_M1UDQS_1 IO_L50N_M1UDQSN_1 IO_L51P_M1DQ12_1 IO_L51N_M1DQ13_1 IO_L52P_M1DQ14_1 IO_L52N_M1DQ15_1 IO_L53P_1 IO_L53N_VREF_1 IO_L58P_1 IO_L58N_1 IO_L59P_1 IO_L59N_1 IO_L60P_1 IO_L60N_1 IO_L61P_1 IO_L61N_1

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CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T

Table 2-12:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NA NA NA NA 2 2 2 2 2

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number P15 P16 Y21 Y22 P19 P20 AB19 AB20 P17 P18 Y19 Y20 T15 R16 R17 R19 V19 V20 T17 T18 V17 V18 T19 T20 U19 T16 R14 W18 U12 U16 W17 Y18 AA18 BUFIO2 Region RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB NA NA NA NA NA NA BR BR BR LX45T LX45T LX45T No Connect (NC)

IO_L62P_1 IO_L62N_1 IO_L63P_1 IO_L63N_1 IO_L64P_1 IO_L64N_1 IO_L65P_1 IO_L65N_1 IO_L66P_1 IO_L66N_1 IO_L67P_1 IO_L67N_1 IO_L68P_1 IO_L68N_1 IO_L70P_1 IO_L70N_1 IO_L71P_1 IO_L71N_1 IO_L72P_1 IO_L72N_1 IO_L73P_1 IO_L73N_1 IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1 VFS RFUSE VBATT SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2

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Chapter 2: Pinout Tables

Table 2-12:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number AB18 Y17 AB17 AA16 AB16 Y15 AB15 V13 W13 U15 V15 W15 Y16 AA14 AB14 W14 Y14 T14 U13 W11 Y10 AA12 AB12 Y11 AB11 AA10 AB10 Y13 AB13 W12 Y12 W9 Y8 BUFIO2 Region BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BL BL BL BL BL BL BL BL BL BL No Connect (NC)

IO_L2N_CMPMOSI_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L4P_2 IO_L4N_VREF_2 IO_L5P_2 IO_L5N_2 IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2 IO_L13P_M1_2 IO_L13N_D10_2 IO_L14P_D11_2 IO_L14N_D12_2 IO_L15P_2 IO_L15N_2 IO_L16P_2 IO_L16N_VREF_2 IO_L20P_2 IO_L20N_2 IO_L29P_GCLK3_2 IO_L29N_GCLK2_2 IO_L30P_GCLK1_D13_2 IO_L30N_GCLK0_USERCCLK_2 IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2 IO_L32P_GCLK29_2 IO_L32N_GCLK28_2 IO_L41P_2 IO_L41N_VREF_2 IO_L42P_2 IO_L42N_2 IO_L43P_2 IO_L43N_2

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CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T

Table 2-12:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number V9 W10 Y9 AB9 AA8 AB8 V7 W8 W6 Y6 Y7 AB7 AA6 AB6 Y5 AB5 AA1 AA2 AB2 Y2 Y1 U4 V3 Y3 AB3 W3 W1 W4 Y4 V11 U10 AA4 AB4 BUFIO2 Region BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL NA LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LX75T LX75T No Connect (NC) LX75T LX75T

IO_L44P_2 IO_L44N_2 IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L49N_D4_2 IO_L50P_2 IO_L50N_2 IO_L62P_D5_2 IO_L62N_D6_2 IO_L63P_2 IO_L63N_2 IO_L64P_D8_2 IO_L64N_D9_2 IO_L65P_INIT_B_2 IO_L65N_CSO_B_2 PROGRAM_B_2 IO_L1P_3 IO_L1N_VREF_3 IO_L2P_3 IO_L2N_3 IO_L7P_3 IO_L7N_3 IO_L8P_3 IO_L8N_3 IO_L9P_3 IO_L9N_3 IO_L10P_3 IO_L10N_3 IO_L11P_3 IO_L11N_3 IO_L12P_3 IO_L12N_3

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Chapter 2: Pinout Tables

Table 2-12:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number U6 V5 T6 T5 P4 R4 T7 R6 P6 P5 U9 U8 R9 T8 T4 T3 T11 T10 V2 V1 U3 U1 T2 T1 R3 R1 P2 P1 N3 N1 M2 M1 L3 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB No Connect (NC)

IO_L13P_3 IO_L13N_3 IO_L20P_3 IO_L20N_3 IO_L21P_3 IO_L21N_3 IO_L22P_3 IO_L22N_3 IO_L23P_3 IO_L23N_3 IO_L24P_3 IO_L24N_3 IO_L25P_3 IO_L25N_3 IO_L26P_3 IO_L26N_3 IO_L31P_3 IO_L31N_VREF_3 IO_L32P_M3DQ14_3 IO_L32N_M3DQ15_3 IO_L33P_M3DQ12_3 IO_L33N_M3DQ13_3 IO_L34P_M3UDQS_3 IO_L34N_M3UDQSN_3 IO_L35P_M3DQ10_3 IO_L35N_M3DQ11_3 IO_L36P_M3DQ8_3 IO_L36N_M3DQ9_3 IO_L37P_M3DQ0_3 IO_L37N_M3DQ1_3 IO_L38P_M3DQ2_3 IO_L38N_M3DQ3_3 IO_L39P_M3LDQS_3

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CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T

Table 2-12:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number L1 K2 K1 J3 J1 H2 H1 N4 P3 G3 G1 M4 M3 F2 F1 M5 L4 E3 E1 K4 K3 D2 D1 N6 M6 C3 C1 K5 J4 B2 B1 L6 K6 BUFIO2 Region LB LB LB LB LB LB LB LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT No Connect (NC)

IO_L39N_M3LDQSN_3 IO_L40P_M3DQ6_3 IO_L40N_M3DQ7_3 IO_L41P_GCLK27_M3DQ4_3 IO_L41N_GCLK26_M3DQ5_3 IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L42N_GCLK24_M3LDM_3 IO_L43P_GCLK23_M3RASN_3 IO_L43N_GCLK22_IRDY2_M3CASN_3 IO_L44P_GCLK21_M3A5_3 IO_L44N_GCLK20_M3A6_3 IO_L45P_M3A3_3 IO_L45N_M3ODT_3 IO_L46P_M3CLK_3 IO_L46N_M3CLKN_3 IO_L47P_M3A0_3 IO_L47N_M3A1_3 IO_L48P_M3BA0_3 IO_L48N_M3BA1_3 IO_L49P_M3A7_3 IO_L49N_M3A2_3 IO_L50P_M3WE_3 IO_L50N_M3BA2_3 IO_L51P_M3A10_3 IO_L51N_M3A4_3 IO_L52P_M3A8_3 IO_L52N_M3A9_3 IO_L53P_M3CKE_3 IO_L53N_M3A12_3 IO_L54P_M3RESET_3 IO_L54N_M3A11_3 IO_L55P_M3A13_3 IO_L55N_M3A14_3

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Chapter 2: Pinout Tables

Table 2-12:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 101 101 101 101 101 101 101 101 101

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number P7 N7 M8 M7 R8 P8 K8 K7 A3 A2 J7 J6 F5 F3 H6 H5 G6 G4 H4 H3 D4 C4 E4 D3 A6 B6 B9 A10 B10 C7 D7 E9 C9 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT NA NA NA NA NA NA NA NA NA No Connect (NC)

IO_L57P_3 IO_L57N_VREF_3 IO_L58P_3 IO_L58N_3 IO_L59P_3 IO_L59N_3 IO_L60P_3 IO_L60N_3 IO_L69P_3 IO_L69N_3 IO_L70P_3 IO_L70N_3 IO_L71P_3 IO_L71N_3 IO_L72P_3 IO_L72N_3 IO_L73P_3 IO_L73N_3 IO_L74P_3 IO_L74N_3 IO_L75P_3 IO_L75N_3 IO_L83P_3 IO_L83N_VREF_3 MGTTXN0_101 MGTTXP0_101 MGTAVCCPLL0_101 MGTREFCLK0N_101 MGTREFCLK0P_101 MGTRXN0_101 MGTRXP0_101 MGTRREF_101 MGTRXN1_101

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CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T

Table 2-12:
Bank 101 101 101 101 101 101 101 123 123 123 123 123 123 123 123 123 123 123 123 123 123 NA NA NA NA NA NA NA NA NA NA NA NA

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number E11 D9 D12 C11 D11 A8 B8 A14 B14 B13 A12 B12 C13 D13 C15 D15 E13 E14 F14 A16 B16 A1 A11 A13 A22 A9 AA13 AA17 AA5 AA9 AB1 AB22 B11 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

MGTAVTTRCAL_101 MGTRXP1_101 MGTAVCCPLL1_101 MGTREFCLK1N_101 MGTREFCLK1P_101 MGTTXN1_101 MGTTXP1_101 MGTTXN0_123 MGTTXP0_123 MGTAVCCPLL0_123 MGTREFCLK0N_123 MGTREFCLK0P_123 MGTRXN0_123 MGTRXP0_123 MGTRXN1_123 MGTRXP1_123 MGTAVCCPLL1_123 MGTREFCLK1N_123 MGTREFCLK1P_123 MGTTXN1_123 MGTTXP1_123 GND GND GND GND GND GND GND GND GND GND GND GND

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Chapter 2: Pinout Tables

Table 2-12:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number B15 B17 B5 B7 C12 C14 C16 C6 C8 D10 E12 E2 E21 E7 F13 F15 G14 G18 G5 H7 J11 J13 J15 J2 J21 J9 K10 K12 K14 L13 L18 L5 L9 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T

Table 2-12:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number M10 M12 M14 N11 N17 N2 N21 N9 P10 P12 P14 R18 R5 U2 U21 U7 V10 V14 V16 V4 W19 W7 J10 J12 J14 J8 K11 K13 K9 L10 L11 L12 L14 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT

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Chapter 2: Pinout Tables

Table 2-12:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 0 0 0 0 0 0 0 1 1 1

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number M11 M13 M9 N10 N12 N13 P11 P13 P9 D16 D6 F18 H15 H9 K15 L8 M15 N8 R10 R11 U11 U17 V6 B19 B4 E10 E17 F6 G13 H8 AA19 C21 E19 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T

Table 2-12:
Bank 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 101 123 101

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number G21 J18 L16 L21 N18 R15 R21 U18 W21 AA11 AA15 AA7 U14 V12 V8 W16 W5 AA3 C2 F4 G2 J5 L2 L7 N5 R2 R7 T9 U5 W2 C10 E15 D8 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 MGTAVCC_101 MGTAVCC_123 MGTAVTTRX_101

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Chapter 2: Pinout Tables

Table 2-12:
Bank 123 101 123

CS(G)484 PackageLX45T, LX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number D14 A7 A15 BUFIO2 Region NA NA NA No Connect (NC)

MGTAVTTRX_123 MGTAVTTTX_101 MGTAVTTTX_123

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FG(G)676 PackageLX45

FG(G)676 PackageLX45
The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/O clock input for the associated pin. For more information see Clock Inputs and BUFIO2 Clocking Regions in Chapter 1.
BUFIO2 Region TL TR RT RB BL BR LT LB Description I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 3 (left). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 3 (left).

Table 2-13:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FG(G)676 PackageLX45
Pin Description Pin Number A3 A2 B4 A4 C5 A5 B6 A6 C7 A7 B8 A8 C9 A9 D6 C6 C11 A11 B12 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL No Connect (NC)

IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L4P_0 IO_L4N_0 IO_L6P_0 IO_L6N_0 IO_L12P_0 IO_L12N_0 IO_L16P_0 IO_L16N_0 IO_L17P_0 IO_L17N_0 IO_L8P_0 IO_L8N_VREF_0 IO_L24P_0 IO_L24N_0 IO_L26P_0

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Table 2-13:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NA NA NA NA 1 1

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number A12 C13 A13 B14 A14 D14 C14 C15 A15 B16 A16 C17 A17 D18 C18 D21 C20 B18 A18 C19 A19 B20 A20 C21 A21 B22 A22 E21 F20 C23 A24 B23 A23 BUFIO2 Region TL TL TL TL TL TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR NA NA NA NA RT RT No Connect (NC)

IO_L26N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L35N_GCLK16_0 IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L38P_0 IO_L38N_VREF_0 IO_L50P_0 IO_L50N_0 IO_L52P_0 IO_L52N_0 IO_L56P_0 IO_L56N_0 IO_L62P_0 IO_L62N_VREF_0 IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 TCK TDI TMS TDO IO_L1P_A25_1 IO_L1N_A24_VREF_1

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FG(G)676 PackageLX45

Table 2-13:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number B24 A25 C25 C26 B25 B26 E25 E26 D24 D26 F24 F26 H24 H26 G25 G26 K24 K26 J25 J26 M24 M26 L25 L26 N25 N26 L19 K19 L23 L24 P20 N21 M23 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT No Connect (NC)

IO_L10P_1 IO_L10N_1 IO_L11P_1 IO_L11N_1 IO_L12P_1 IO_L12N_1 IO_L16P_1 IO_L16N_1 IO_L17P_1 IO_L17N_1 IO_L18P_1 IO_L18N_1 IO_L19P_1 IO_L19N_1 IO_L20P_1 IO_L20N_1 IO_L21P_1 IO_L21N_1 IO_L22P_1 IO_L22N_1 IO_L23P_1 IO_L23N_1 IO_L24P_1 IO_L24N_1 IO_L25P_1 IO_L25N_1 IO_L28P_1 IO_L28N_VREF_1 IO_L29P_A23_M1A13_1 IO_L29N_A22_M1A14_1 IO_L30P_A21_M1RESET_1 IO_L30N_A20_M1A11_1 IO_L31P_A19_M1CKE_1

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Table 2-13:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number N24 L17 K18 P24 P26 M19 L18 R25 R26 M18 N19 N22 N23 N17 N18 R23 R24 N20 M21 P21 P22 V23 W24 U25 U26 W25 W26 V24 V26 T24 T26 Y24 Y26 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RB RB RB RB RB RB RB RB RB RB RB RB No Connect (NC)

IO_L31N_A18_M1A12_1 IO_L32P_A17_M1A8_1 IO_L32N_A16_M1A9_1 IO_L33P_A15_M1A10_1 IO_L33N_A14_M1A4_1 IO_L34P_A13_M1WE_1 IO_L34N_A12_M1BA2_1 IO_L35P_A11_M1A7_1 IO_L35N_A10_M1A2_1 IO_L36P_A9_M1BA0_1 IO_L36N_A8_M1BA1_1 IO_L37P_A7_M1A0_1 IO_L37N_A6_M1A1_1 IO_L38P_A5_M1CLK_1 IO_L38N_A4_M1CLKN_1 IO_L39P_M1A3_1 IO_L39N_M1ODT_1 IO_L40P_GCLK11_M1A5_1 IO_L40N_GCLK10_M1A6_1 IO_L41P_GCLK9_IRDY1_M1RASN_1 IO_L41N_GCLK8_M1CASN_1 IO_L42P_GCLK7_M1UDM_1 IO_L42N_GCLK6_TRDY1_M1LDM_1 IO_L43P_GCLK5_M1DQ4_1 IO_L43N_GCLK4_M1DQ5_1 IO_L44P_A3_M1DQ6_1 IO_L44N_A2_M1DQ7_1 IO_L45P_A1_M1LDQS_1 IO_L45N_A0_M1LDQSN_1 IO_L46P_FCS_B_M1DQ2_1 IO_L46N_FOE_B_M1DQ3_1 IO_L47P_FWE_B_M1DQ0_1 IO_L47N_LDC_M1DQ1_1

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FG(G)676 PackageLX45

Table 2-13:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number AD24 AD26 AB24 AB26 AC25 AC26 AA25 AA26 AE25 AE26 T23 U24 R20 R19 T22 U23 T18 T19 U21 U22 AA23 AA24 T20 U20 AC23 AC24 V18 V19 AE24 AF25 W18 W19 U17 BUFIO2 Region RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB No Connect (NC)

IO_L48P_HDC_M1DQ8_1 IO_L48N_M1DQ9_1 IO_L49P_M1DQ10_1 IO_L49N_M1DQ11_1 IO_L50P_M1UDQS_1 IO_L50N_M1UDQSN_1 IO_L51P_M1DQ12_1 IO_L51N_M1DQ13_1 IO_L52P_M1DQ14_1 IO_L52N_M1DQ15_1 IO_L53P_1 IO_L53N_VREF_1 IO_L57P_1 IO_L57N_1 IO_L59P_1 IO_L59N_1 IO_L60P_1 IO_L60N_1 IO_L61P_1 IO_L61N_1 IO_L63P_1 IO_L63N_1 IO_L64P_1 IO_L64N_1 IO_L65P_1 IO_L65N_1 IO_L66P_1 IO_L66N_1 IO_L67P_1 IO_L67N_1 IO_L68P_1 IO_L68N_1 IO_L62P_1

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Chapter 2: Pinout Tables

Table 2-13:
Bank 1 1 1 1 1 1 1 1 1 1 1 NA 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number V17 U19 V20 V22 W22 Y20 Y21 Y22 AA22 AE23 AF24 AD23 AC22 AF23 AD22 AF22 AE21 AF21 AD20 AF20 AE19 AF19 AC20 AD21 Y18 AA19 AC19 AD19 V16 W17 AD18 AF18 Y16 BUFIO2 Region RB RB RB RB RB RB RB RB RB RB RB NA NA NA BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR No Connect (NC)

IO_L62N_1 IO_L70P_1 IO_L70N_1 IO_L71P_1 IO_L71N_1 IO_L72P_1 IO_L72N_1 IO_L73P_1 IO_L73N_1 IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1 SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2 IO_L2N_CMPMOSI_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L4P_2 IO_L4N_VREF_2 IO_L5P_2 IO_L5N_2 IO_L6P_2 IO_L6N_2 IO_L7P_2 IO_L7N_2 IO_L8P_2 IO_L8N_2 IO_L9P_2 IO_L9N_2 IO_L10P_2

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FG(G)676 PackageLX45

Table 2-13:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number AA17 AA18 AB18 AE17 AF17 AD16 AF16 AE15 AF15 AB17 AC17 AC15 AD15 AC16 AD17 V15 W16 AB15 AC14 Y15 AA15 Y14 AA14 AD14 AF14 AE13 AF13 AC13 AD13 AD12 AF12 AA13 AB13 BUFIO2 Region BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BL BL BL BL BL BL No Connect (NC)

IO_L10N_2 IO_L11P_2 IO_L11N_2 IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2 IO_L13P_M1_2 IO_L13N_D10_2 IO_L14P_D11_2 IO_L14N_D12_2 IO_L15P_2 IO_L15N_2 IO_L16P_2 IO_L16N_VREF_2 IO_L17P_2 IO_L17N_2 IO_L18P_2 IO_L18N_2 IO_L19P_2 IO_L19N_2 IO_L20P_2 IO_L20N_2 IO_L28P_2 IO_L28N_2 IO_L29P_GCLK3_2 IO_L29N_GCLK2_2 IO_L30P_GCLK1_D13_2 IO_L30N_GCLK0_USERCCLK_2 IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2 IO_L32P_GCLK29_2 IO_L32N_GCLK28_2 IO_L34P_2 IO_L34N_2

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Chapter 2: Pinout Tables

Table 2-13:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number AA12 AC12 U15 V14 AA11 AB11 V13 W14 AC11 AD11 V12 W12 AE11 AF11 AE9 AF9 AD10 AF10 U13 U12 Y10 AB10 V11 W11 AC9 AD9 AD8 AF8 AE7 AF7 AD6 AF6 AE5 BUFIO2 Region BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL No Connect (NC)

IO_L41P_2 IO_L41N_VREF_2 IO_L42P_2 IO_L42N_2 IO_L43P_2 IO_L43N_2 IO_L44P_2 IO_L44N_2 IO_L45P_2 IO_L45N_2 IO_L46P_2 IO_L46N_2 IO_L47P_2 IO_L47N_2 IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L49N_D4_2 IO_L50P_2 IO_L50N_2 IO_L51P_2 IO_L51N_2 IO_L52P_2 IO_L52N_2 IO_L58P_2 IO_L58N_2 IO_L53P_2 IO_L53N_2 IO_L62P_D5_2 IO_L62N_D6_2 IO_L63P_2 IO_L63N_2 IO_L64P_D8_2

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FG(G)676 PackageLX45

Table 2-13:
Bank 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number AF5 AE4 AF4 AF3 AC7 AD7 AE3 AF2 AC4 AD4 AA7 Y6 AB7 AB6 AC5 AD5 AA5 AB5 W8 W7 AB4 AC3 AA4 AA3 W5 Y5 U8 U7 U5 V5 U4 U3 T8 BUFIO2 Region BL BL BL NA LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB No Connect (NC)

IO_L64N_D9_2 IO_L65P_INIT_B_2 IO_L65N_CSO_B_2 PROGRAM_B_2 IO_L1P_3 IO_L1N_VREF_3 IO_L2P_3 IO_L2N_3 IO_L3P_3 IO_L3N_3 IO_L7P_3 IO_L7N_3 IO_L8P_3 IO_L8N_3 IO_L10P_3 IO_L10N_3 IO_L16P_3 IO_L16N_3 IO_L15P_3 IO_L15N_3 IO_L18P_3 IO_L18N_3 IO_L20P_3 IO_L20N_3 IO_L22P_3 IO_L22N_3 IO_L23P_3 IO_L23N_3 IO_L24P_3 IO_L24N_3 IO_L28P_3 IO_L28N_3 IO_L29P_3

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Chapter 2: Pinout Tables

Table 2-13:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number T6 R5 T4 R7 R6 AB3 AB1 AD3 AD1 AC2 AC1 AE2 AE1 AA2 AA1 Y3 Y1 W2 W1 V3 V1 U2 U1 T3 T1 V4 W3 N8 P8 R2 R1 P7 P6 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LT LT LT LT LT LT No Connect (NC)

IO_L29N_3 IO_L30P_3 IO_L30N_3 IO_L31P_3 IO_L31N_VREF_3 IO_L32P_M3DQ14_3 IO_L32N_M3DQ15_3 IO_L33P_M3DQ12_3 IO_L33N_M3DQ13_3 IO_L34P_M3UDQS_3 IO_L34N_M3UDQSN_3 IO_L35P_M3DQ10_3 IO_L35N_M3DQ11_3 IO_L36P_M3DQ8_3 IO_L36N_M3DQ9_3 IO_L37P_M3DQ0_3 IO_L37N_M3DQ1_3 IO_L38P_M3DQ2_3 IO_L38N_M3DQ3_3 IO_L39P_M3LDQS_3 IO_L39N_M3LDQSN_3 IO_L40P_M3DQ6_3 IO_L40N_M3DQ7_3 IO_L41P_GCLK27_M3DQ4_3 IO_L41N_GCLK26_M3DQ5_3 IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L42N_GCLK24_M3LDM_3 IO_L43P_GCLK23_M3RASN_3 IO_L43N_GCLK22_IRDY2_M3CASN_3 IO_L44P_GCLK21_M3A5_3 IO_L44N_GCLK20_M3A6_3 IO_L45P_M3A3_3 IO_L45N_M3ODT_3

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FG(G)676 PackageLX45

Table 2-13:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number R4 R3 N7 N6 P3 P1 P10 R9 P5 N5 M10 N9 N4 N3 M9 M8 L4 L3 M6 M4 L7 L6 N2 N1 M3 M1 L2 L1 K3 K1 J2 J1 H3 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT No Connect (NC)

IO_L46P_M3CLK_3 IO_L46N_M3CLKN_3 IO_L47P_M3A0_3 IO_L47N_M3A1_3 IO_L48P_M3BA0_3 IO_L48N_M3BA1_3 IO_L49P_M3A7_3 IO_L49N_M3A2_3 IO_L50P_M3WE_3 IO_L50N_M3BA2_3 IO_L51P_M3A10_3 IO_L51N_M3A4_3 IO_L52P_M3A8_3 IO_L52N_M3A9_3 IO_L53P_M3CKE_3 IO_L53N_M3A12_3 IO_L54P_M3RESET_3 IO_L54N_M3A11_3 IO_L55P_M3A13_3 IO_L55N_M3A14_3 IO_L57P_3 IO_L57N_VREF_3 IO_L59P_3 IO_L59N_3 IO_L60P_3 IO_L60N_3 IO_L61P_3 IO_L61N_3 IO_L62P_3 IO_L62N_3 IO_L63P_3 IO_L63N_3 IO_L64P_3

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Chapter 2: Pinout Tables

Table 2-13:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number H1 G2 G1 F3 F1 E2 E1 D3 D1 E4 E3 C2 C1 B2 B1 C4 C3 A1 A26 AB12 AB16 AB2 AB20 AB25 AC8 AE10 AE14 AE18 AE22 AE6 AF1 AF26 B13 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

IO_L64N_3 IO_L65P_3 IO_L65N_3 IO_L66P_3 IO_L66N_3 IO_L67P_3 IO_L67N_3 IO_L68P_3 IO_L68N_3 IO_L77P_3 IO_L77N_3 IO_L79P_3 IO_L79N_3 IO_L81P_3 IO_L81N_3 IO_L83P_3 IO_L83N_VREF_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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FG(G)676 PackageLX45

Table 2-13:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number B17 B21 B5 B9 D4 E11 E15 E22 E7 F19 F2 F25 H11 H23 H4 J19 J8 K16 K2 K25 L11 L13 L15 M12 M14 M16 M22 M5 N11 N13 N15 P12 P14 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Chapter 2: Pinout Tables

Table 2-13:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number P16 P19 P2 P25 R11 R13 R15 R8 T12 T14 T16 T21 T5 U11 V2 V25 W15 W20 Y11 Y23 Y4 Y7 AA10 AA16 AA21 AA6 F21 F6 G12 G15 J18 J9 K13 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX

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FG(G)676 PackageLX45

Table 2-13:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 0

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number L22 L5 M17 N10 U14 U6 V9 Y19 K11 K17 L10 L12 L14 L16 M11 M13 M15 N12 N14 N16 P11 P13 P15 R12 R14 R16 T11 T13 T15 T17 U10 U16 B11 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCO_0

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Chapter 2: Pinout Tables

Table 2-13:
Bank 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number B15 B19 B3 B7 C22 D17 D9 E13 G10 G18 H14 AB23 AD25 M20 P23 T25 U18 V21 W23 Y25 D25 F23 H25 J21 K23 M25 AB14 AC10 AC18 AC21 AE12 AE16 AE20 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2

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FG(G)676 PackageLX45

Table 2-13:
Bank 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 NC NC NC NC NC NC NC NC NC NC NC NC NC NC

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number AE8 Y12 Y17 AC6 AD2 M7 P4 P9 T2 T7 W4 W6 Y2 D2 F4 H2 J6 K4 M2 A10 AA20 AA8 AB19 AB8 C10 C12 C16 C24 C8 B10 D10 D11 D12 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 No Connect (NC)

VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect

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Chapter 2: Pinout Tables

Table 2-13:
Bank NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number D13 D15 D16 D19 D20 D22 D23 D5 D7 D8 E10 E12 E14 E16 E17 E18 E19 E20 E23 E24 E5 E6 E8 E9 F10 F11 F12 F13 F14 F15 F16 F17 F18 BUFIO2 Region No Connect (NC) LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45

No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect

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FG(G)676 PackageLX45

Table 2-13:
Bank NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number F22 F5 F7 F8 F9 G11 G13 G14 G16 G17 G19 G20 G21 G22 G23 G24 G3 G4 G5 G6 G7 G8 G9 H10 H12 H13 H15 H16 H17 H18 H19 H20 H21 BUFIO2 Region No Connect (NC) LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45

No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect

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Table 2-13:
Bank NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number H22 H5 H6 H7 H8 H9 J10 J11 J12 J13 J14 J15 J16 J17 J20 J22 J23 J24 J5 J7 K10 K12 K14 K15 K20 K21 K22 K5 K6 K7 K8 K9 L20 BUFIO2 Region No Connect (NC) LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45

No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX45

Table 2-13:
Bank NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

FG(G)676 PackageLX45 (Contd)


Pin Description Pin Number L21 J3 J4 L8 L9 P17 P18 R10 R17 R18 R21 R22 T10 T9 AA9 AB9 U9 V10 W10 W13 W21 W9 Y13 Y8 Y9 V6 V7 V8 AB21 AB22 BUFIO2 Region No Connect (NC) LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45 LX45

No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect

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FG(G)676 PackageLX75, LX100, and LX150


The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/O clock input for the associated pin. For more information see Clock Inputs and BUFIO2 Clocking Regions in Chapter 1.
BUFIO2 Region TL TR RT RB BL BR LT LB Description I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 1 and bank 5 (right). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 3 and bank 4 (left). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 3 (left).

Table 2-14:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FG(G)676 PackageLX75, LX100, and LX150


Pin Description Pin Number A3 A2 B4 A4 E6 D5 C5 A5 G8 F7 B6 A6 G9 F8 D6 C6 K12 J11 H10 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL LX75, LX100 LX75, LX100 LX75, LX100 LX75, LX100 LX75, LX100 LX75 LX75 No Connect (NC)

IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L5P_0 IO_L5N_0 IO_L6P_0 IO_L6N_0 IO_L7P_0 IO_L7N_0 IO_L8P_0 IO_L8N_VREF_0 IO_L9P_0 IO_L9N_0 IO_L11P_0

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX75, LX100, and LX150

Table 2-14:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number H9 C7 A7 E8 D7 D8 C8 F9 E9 B8 A8 C9 A9 E10 F10 D10 C10 J12 H13 B10 A10 D11 F11 C11 A11 H12 G11 B12 A12 F12 E12 D12 C12 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL LX75, LX100 LX75, LX100 LX75 LX75 LX75, LX100 LX75, LX100 LX75 LX75 LX75 LX75 LX75 LX75 LX75, LX100 LX75, LX100 LX75 LX75 LX75 LX75 LX75 LX75 No Connect (NC) LX75, LX100

IO_L11N_0 IO_L12P_0 IO_L12N_0 IO_L13P_0 IO_L13N_0 IO_L14P_0 IO_L14N_0 IO_L15P_0 IO_L15N_0 IO_L16P_0 IO_L16N_0 IO_L17P_0 IO_L17N_0 IO_L18P_0 IO_L18N_0 IO_L19P_0 IO_L19N_0 IO_L21P_0 IO_L21N_0 IO_L22P_0 IO_L22N_0 IO_L23P_0 IO_L23N_0 IO_L24P_0 IO_L24N_0 IO_L25P_0 IO_L25N_0 IO_L26P_0 IO_L26N_0 IO_L30P_0 IO_L30N_0 IO_L31P_0 IO_L31N_0

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Table 2-14:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number G13 F14 F13 D13 C13 A13 B14 A14 D14 C14 C15 A15 B16 A16 J14 G14 E14 D15 J13 K14 D16 C16 G16 F15 F17 E17 F16 E16 C17 A17 J15 H15 D18 BUFIO2 Region TL TL TL TL TL TL TL TL TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR LX75 LX75 LX75 LX75 LX75, LX100 LX75, LX100 LX75 LX75 LX75 LX75 No Connect (NC) LX75, LX100 LX75, LX100 LX75 LX75

IO_L32P_0 IO_L32N_0 IO_L33P_0 IO_L33N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L35N_GCLK16_0 IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L38P_0 IO_L38N_VREF_0 IO_L43P_0 IO_L43N_0 IO_L44P_0 IO_L44N_0 IO_L45P_0 IO_L45N_0 IO_L46P_0 IO_L46N_0 IO_L47P_0 IO_L47N_0 IO_L48P_0 IO_L48N_0 IO_L49P_0 IO_L49N_0 IO_L50P_0 IO_L50N_0 IO_L51P_0 IO_L51N_0 IO_L52P_0

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX75, LX100, and LX150

Table 2-14:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NA NA NA NA 5 5 5 5

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number C18 K15 J16 E19 D19 H16 G17 D21 C20 F18 E18 E20 D20 J17 H17 B18 A18 C19 A19 B20 A20 C21 A21 B22 A22 E21 F20 C23 A24 B23 A23 G20 G21 BUFIO2 Region TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR NA NA NA NA RT RT RT RT LX75 LX75 LX75 LX75 LX75 LX75 LX75, LX100 LX75, LX100 LX75 LX75 LX75 LX75 No Connect (NC)

IO_L52N_0 IO_L53P_0 IO_L53N_0 IO_L54P_0 IO_L54N_0 IO_L55P_0 IO_L55N_0 IO_L56P_0 IO_L56N_0 IO_L57P_0 IO_L57N_0 IO_L58P_0 IO_L58N_0 IO_L59P_0 IO_L59N_0 IO_L62P_0 IO_L62N_VREF_0 IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 TCK TDI TMS TDO IO_L1P_A25_5 IO_L1N_A24_VREF_5 IO_L2P_M5A13_5 IO_L2N_M5A14_5

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Chapter 2: Pinout Tables

Table 2-14:
Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number D23 C24 F22 D22 H20 H21 H22 G22 E23 E24 G23 G24 H18 G19 B24 A25 C25 C26 B25 B26 K20 K21 K22 J22 J23 J24 E25 E26 D24 D26 F24 F26 H24 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT No Connect (NC)

IO_L3P_M5RESET_5 IO_L3N_M5A11_5 IO_L4P_M5CKE_5 IO_L4N_M5A12_5 IO_L5P_M5A8_5 IO_L5N_M5A9_5 IO_L6P_M5A10_5 IO_L6N_M5A4_5 IO_L7P_M5WE_5 IO_L7N_M5BA2_5 IO_L8P_M5A7_5 IO_L8N_M5A2_5 IO_L9P_M5BA0_5 IO_L9N_M5BA1_5 IO_L10P_M5A0_5 IO_L10N_M5A1_5 IO_L11P_M5CLK_5 IO_L11N_M5CLKN_5 IO_L12P_M5A3_5 IO_L12N_M5ODT_5 IO_L13P_M5A5_5 IO_L13N_M5A6_5 IO_L14P_M5RASN_5 IO_L14N_M5CASN_5 IO_L15P_M5UDM_5 IO_L15N_M5LDM_5 IO_L16P_M5DQ4_5 IO_L16N_M5DQ5_5 IO_L17P_M5DQ6_5 IO_L17N_M5DQ7_5 IO_L18P_M5LDQS_5 IO_L18N_M5LDQSN_5 IO_L19P_M5DQ2_5

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX75, LX100, and LX150

Table 2-14:
Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number H26 G25 G26 K24 K26 J25 J26 M24 M26 L25 L26 N25 N26 L20 L21 H19 J20 L19 K19 L23 L24 P20 N21 M23 N24 L17 K18 P24 P26 M19 L18 R25 R26 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT No Connect (NC)

IO_L19N_M5DQ3_5 IO_L20P_M5DQ0_5 IO_L20N_M5DQ1_5 IO_L21P_M5DQ8_5 IO_L21N_M5DQ9_5 IO_L22P_M5DQ10_5 IO_L22N_M5DQ11_5 IO_L23P_M5UDQS_5 IO_L23N_M5UDQSN_5 IO_L24P_M5DQ12_5 IO_L24N_M5DQ13_5 IO_L25P_M5DQ14_5 IO_L25N_M5DQ15_5 IO_L26P_5 IO_L26N_VREF_5 IO_L27P_5 IO_L27N_5 IO_L28P_1 IO_L28N_VREF_1 IO_L29P_A23_M1A13_1 IO_L29N_A22_M1A14_1 IO_L30P_A21_M1RESET_1 IO_L30N_A20_M1A11_1 IO_L31P_A19_M1CKE_1 IO_L31N_A18_M1A12_1 IO_L32P_A17_M1A8_1 IO_L32N_A16_M1A9_1 IO_L33P_A15_M1A10_1 IO_L33N_A14_M1A4_1 IO_L34P_A13_M1WE_1 IO_L34N_A12_M1BA2_1 IO_L35P_A11_M1A7_1 IO_L35N_A10_M1A2_1

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Chapter 2: Pinout Tables

Table 2-14:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number M18 N19 N22 N23 N17 N18 R23 R24 N20 M21 P21 P22 V23 W24 U25 U26 W25 W26 V24 V26 T24 T26 Y24 Y26 AD24 AD26 AB24 AB26 AC25 AC26 AA25 AA26 AE25 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB No Connect (NC)

IO_L36P_A9_M1BA0_1 IO_L36N_A8_M1BA1_1 IO_L37P_A7_M1A0_1 IO_L37N_A6_M1A1_1 IO_L38P_A5_M1CLK_1 IO_L38N_A4_M1CLKN_1 IO_L39P_M1A3_1 IO_L39N_M1ODT_1 IO_L40P_GCLK11_M1A5_1 IO_L40N_GCLK10_M1A6_1 IO_L41P_GCLK9_IRDY1_M1RASN_1 IO_L41N_GCLK8_M1CASN_1 IO_L42P_GCLK7_M1UDM_1 IO_L42N_GCLK6_TRDY1_M1LDM_1 IO_L43P_GCLK5_M1DQ4_1 IO_L43N_GCLK4_M1DQ5_1 IO_L44P_A3_M1DQ6_1 IO_L44N_A2_M1DQ7_1 IO_L45P_A1_M1LDQS_1 IO_L45N_A0_M1LDQSN_1 IO_L46P_FCS_B_M1DQ2_1 IO_L46N_FOE_B_M1DQ3_1 IO_L47P_FWE_B_M1DQ0_1 IO_L47N_LDC_M1DQ1_1 IO_L48P_HDC_M1DQ8_1 IO_L48N_M1DQ9_1 IO_L49P_M1DQ10_1 IO_L49N_M1DQ11_1 IO_L50P_M1UDQS_1 IO_L50N_M1UDQSN_1 IO_L51P_M1DQ12_1 IO_L51N_M1DQ13_1 IO_L52P_M1DQ14_1

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX75, LX100, and LX150

Table 2-14:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number AE26 T23 U24 R22 R21 P17 P18 R20 R19 R17 R18 T22 U23 T18 T19 U21 U22 U17 V17 AA23 AA24 T20 U20 AC23 AC24 V18 V19 AE24 AF25 W18 W19 AB21 AB22 BUFIO2 Region RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB No Connect (NC)

IO_L52N_M1DQ15_1 IO_L53P_1 IO_L53N_VREF_1 IO_L55P_1 IO_L55N_1 IO_L56P_1 IO_L56N_1 IO_L57P_1 IO_L57N_1 IO_L58P_1 IO_L58N_1 IO_L59P_1 IO_L59N_1 IO_L60P_1 IO_L60N_1 IO_L61P_1 IO_L61N_1 IO_L62P_1 IO_L62N_1 IO_L63P_1 IO_L63N_1 IO_L64P_1 IO_L64N_1 IO_L65P_1 IO_L65N_1 IO_L66P_1 IO_L66N_1 IO_L67P_1 IO_L67N_1 IO_L68P_1 IO_L68N_1 IO_L69P_1 IO_L69N_VREF_1

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Chapter 2: Pinout Tables

Table 2-14:
Bank 1 1 1 1 1 1 1 1 1 1 NA NA NA NA 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number U19 V20 V22 W22 Y20 Y21 Y22 AA22 AE23 AF24 AB19 AA20 W21 AD23 AC22 AF23 AD22 AF22 AE21 AF21 AD20 AF20 AE19 AF19 AC20 AD21 Y18 AA19 AC19 AD19 V16 W17 AD18 BUFIO2 Region RB RB RB RB RB RB RB RB RB RB NA NA NA NA NA NA BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR LX75 LX75 LX75 LX75 LX75 LX75 LX75 LX75 No Connect (NC)

IO_L70P_1 IO_L70N_1 IO_L71P_1 IO_L71N_1 IO_L72P_1 IO_L72N_1 IO_L73P_1 IO_L73N_1 IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1 VFS RFUSE VBATT SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2 IO_L2N_CMPMOSI_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L4P_2 IO_L4N_VREF_2 IO_L5P_2 IO_L5N_2 IO_L6P_2 IO_L6N_2 IO_L7P_2 IO_L7N_2 IO_L8P_2 IO_L8N_2 IO_L9P_2

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX75, LX100, and LX150

Table 2-14:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number AF18 Y16 AA17 AA18 AB18 AE17 AF17 AD16 AF16 AE15 AF15 AB17 AC17 AC15 AD15 AC16 AD17 V15 W16 AB15 AC14 Y15 AA15 Y14 AA14 AD14 AF14 AE13 AF13 AC13 AD13 AD12 AF12 BUFIO2 Region BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BL BL BL BL LX75 LX75 LX75 LX75 LX75 LX75 LX75 LX75 LX75 LX75 No Connect (NC)

IO_L9N_2 IO_L10P_2 IO_L10N_2 IO_L11P_2 IO_L11N_2 IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2 IO_L13P_M1_2 IO_L13N_D10_2 IO_L14P_D11_2 IO_L14N_D12_2 IO_L15P_2 IO_L15N_2 IO_L16P_2 IO_L16N_VREF_2 IO_L17P_2 IO_L17N_2 IO_L18P_2 IO_L18N_2 IO_L19P_2 IO_L19N_2 IO_L20P_2 IO_L20N_2 IO_L28P_2 IO_L28N_2 IO_L29P_GCLK3_2 IO_L29N_GCLK2_2 IO_L30P_GCLK1_D13_2 IO_L30N_GCLK0_USERCCLK_2 IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2 IO_L32P_GCLK29_2 IO_L32N_GCLK28_2

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Chapter 2: Pinout Tables

Table 2-14:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number W13 Y13 AA13 AB13 AA12 AC12 U15 V14 AA11 AB11 V13 W14 AC11 AD11 V12 W12 AE11 AF11 AE9 AF9 AD10 AF10 U13 U12 Y10 AB10 V11 W11 AD8 AF8 AC9 AD9 AA9 BUFIO2 Region BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL LX75 LX75 LX75 LX75 LX75 LX75 LX75 LX75 LX75 LX75 LX75 LX75 LX75 LX75 LX75 LX75 No Connect (NC) LX75 LX75

IO_L33P_2 IO_L33N_2 IO_L34P_2 IO_L34N_2 IO_L41P_2 IO_L41N_VREF_2 IO_L42P_2 IO_L42N_2 IO_L43P_2 IO_L43N_2 IO_L44P_2 IO_L44N_2 IO_L45P_2 IO_L45N_2 IO_L46P_2 IO_L46N_2 IO_L47P_2 IO_L47N_2 IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L49N_D4_2 IO_L50P_2 IO_L50N_2 IO_L51P_2 IO_L51N_2 IO_L52P_2 IO_L52N_2 IO_L53P_2 IO_L53N_2 IO_L58P_2 IO_L58N_2 IO_L61P_2

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX75, LX100, and LX150

Table 2-14:
Bank 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number AB9 AE7 AF7 AD6 AF6 AE5 AF5 AE4 AF4 AF3 AC7 AD7 AE3 AF2 AC4 AD4 AA8 AB8 AA7 Y6 AB7 AB6 Y9 Y8 AC5 AD5 W8 W7 AA5 AB5 V7 V6 AB4 BUFIO2 Region BL BL BL BL BL BL BL BL BL NA LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB No Connect (NC)

IO_L61N_VREF_2 IO_L62P_D5_2 IO_L62N_D6_2 IO_L63P_2 IO_L63N_2 IO_L64P_D8_2 IO_L64N_D9_2 IO_L65P_INIT_B_2 IO_L65N_CSO_B_2 PROGRAM_B_2 IO_L1P_3 IO_L1N_VREF_3 IO_L2P_3 IO_L2N_3 IO_L3P_3 IO_L3N_3 IO_L4P_3 IO_L4N_3 IO_L7P_3 IO_L7N_3 IO_L8P_3 IO_L8N_3 IO_L9P_3 IO_L9N_3 IO_L10P_3 IO_L10N_3 IO_L15P_3 IO_L15N_3 IO_L16P_3 IO_L16N_3 IO_L17P_3 IO_L17N_VREF_3 IO_L18P_3

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Table 2-14:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number AC3 W9 V8 AA4 AA3 W10 V10 W5 Y5 U8 U7 U5 V5 T10 U9 R10 T9 U4 U3 T8 T6 R5 T4 R7 R6 AB3 AB1 AD3 AD1 AC2 AC1 AE2 AE1 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB No Connect (NC)

IO_L18N_3 IO_L19P_3 IO_L19N_3 IO_L20P_3 IO_L20N_3 IO_L21P_3 IO_L21N_3 IO_L22P_3 IO_L22N_3 IO_L23P_3 IO_L23N_3 IO_L24P_3 IO_L24N_3 IO_L25P_3 IO_L25N_3 IO_L27P_3 IO_L27N_3 IO_L28P_3 IO_L28N_3 IO_L29P_3 IO_L29N_3 IO_L30P_3 IO_L30N_3 IO_L31P_3 IO_L31N_VREF_3 IO_L32P_M3DQ14_3 IO_L32N_M3DQ15_3 IO_L33P_M3DQ12_3 IO_L33N_M3DQ13_3 IO_L34P_M3UDQS_3 IO_L34N_M3UDQSN_3 IO_L35P_M3DQ10_3 IO_L35N_M3DQ11_3

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FG(G)676 PackageLX75, LX100, and LX150

Table 2-14:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number AA2 AA1 Y3 Y1 W2 W1 V3 V1 U2 U1 T3 T1 V4 W3 N8 P8 R2 R1 P7 P6 R4 R3 N7 N6 P3 P1 P10 R9 P5 N5 M10 N9 N4 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LB LB LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT No Connect (NC)

IO_L36P_M3DQ8_3 IO_L36N_M3DQ9_3 IO_L37P_M3DQ0_3 IO_L37N_M3DQ1_3 IO_L38P_M3DQ2_3 IO_L38N_M3DQ3_3 IO_L39P_M3LDQS_3 IO_L39N_M3LDQSN_3 IO_L40P_M3DQ6_3 IO_L40N_M3DQ7_3 IO_L41P_GCLK27_M3DQ4_3 IO_L41N_GCLK26_M3DQ5_3 IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L42N_GCLK24_M3LDM_3 IO_L43P_GCLK23_M3RASN_3 IO_L43N_GCLK22_IRDY2_M3CASN_3 IO_L44P_GCLK21_M3A5_3 IO_L44N_GCLK20_M3A6_3 IO_L45P_M3A3_3 IO_L45N_M3ODT_3 IO_L46P_M3CLK_3 IO_L46N_M3CLKN_3 IO_L47P_M3A0_3 IO_L47N_M3A1_3 IO_L48P_M3BA0_3 IO_L48N_M3BA1_3 IO_L49P_M3A7_3 IO_L49N_M3A2_3 IO_L50P_M3WE_3 IO_L50N_M3BA2_3 IO_L51P_M3A10_3 IO_L51N_M3A4_3 IO_L52P_M3A8_3

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Chapter 2: Pinout Tables

Table 2-14:
Bank 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number N3 M9 M8 L4 L3 M6 M4 L7 L6 K8 L8 N2 N1 M3 M1 L2 L1 K3 K1 J2 J1 H3 H1 G2 G1 F3 F1 E2 E1 D3 D1 J4 J3 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT No Connect (NC)

IO_L52N_M3A9_3 IO_L53P_M3CKE_3 IO_L53N_M3A12_3 IO_L54P_M3RESET_3 IO_L54N_M3A11_3 IO_L55P_M3A13_3 IO_L55N_M3A14_3 IO_L57P_3 IO_L57N_VREF_3 IO_L58P_4 IO_L58N_VREF_4 IO_L59P_M4DQ14_4 IO_L59N_M4DQ15_4 IO_L60P_M4DQ12_4 IO_L60N_M4DQ13_4 IO_L61P_M4UDQS_4 IO_L61N_M4UDQSN_4 IO_L62P_M4DQ10_4 IO_L62N_M4DQ11_4 IO_L63P_M4DQ8_4 IO_L63N_M4DQ9_4 IO_L64P_M4DQ0_4 IO_L64N_M4DQ1_4 IO_L65P_M4DQ2_4 IO_L65N_M4DQ3_4 IO_L66P_M4LDQS_4 IO_L66N_M4LDQSN_4 IO_L67P_M4DQ6_4 IO_L67N_M4DQ7_4 IO_L68P_M4DQ4_4 IO_L68N_M4DQ5_4 IO_L69P_M4UDM_4 IO_L69N_M4LDM_4

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FG(G)676 PackageLX75, LX100, and LX150

Table 2-14:
Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 NA NA NA NA NA

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number K7 K6 K5 J5 J7 H7 G4 G3 K10 L9 H6 H5 J10 K9 E4 E3 G6 G5 C2 C1 F5 E5 B2 B1 H8 G7 C4 C3 A1 A26 AB12 AB16 AB2 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT NA NA NA NA NA No Connect (NC)

IO_L70P_M4RASN_4 IO_L70N_M4CASN_4 IO_L71P_M4A5_4 IO_L71N_M4A6_4 IO_L72P_M4A3_4 IO_L72N_M4ODT_4 IO_L73P_M4CLK_4 IO_L73N_M4CLKN_4 IO_L74P_M4A0_4 IO_L74N_M4A1_4 IO_L75P_M4BA0_4 IO_L75N_M4BA1_4 IO_L76P_M4A7_4 IO_L76N_M4A2_4 IO_L77P_M4WE_4 IO_L77N_M4BA2_4 IO_L78P_M4A10_4 IO_L78N_M4A4_4 IO_L79P_M4A8_4 IO_L79N_M4A9_4 IO_L80P_M4CKE_4 IO_L80N_M4A12_4 IO_L81P_M4RESET_4 IO_L81N_M4A11_4 IO_L82P_M4A13_4 IO_L82N_M4A14_4 IO_L83P_4 IO_L83N_VREF_4 GND GND GND GND GND

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Chapter 2: Pinout Tables

Table 2-14:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number AB20 AB25 AC8 AE10 AE14 AE18 AE22 AE6 AF1 AF26 B13 B17 B21 B5 B9 D4 E11 E15 E22 E7 F19 F2 F25 H11 H23 H4 J19 J8 K16 K2 K25 L11 L13 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX75, LX100, and LX150

Table 2-14:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number L15 M12 M14 M16 M22 M5 N11 N13 N15 P12 P14 P16 P19 P2 P25 R11 R13 R15 R8 T12 T14 T16 T21 T5 U11 V2 V25 W15 W20 Y11 Y23 Y4 Y7 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Chapter 2: Pinout Tables

Table 2-14:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number AA10 AA16 AA21 AA6 F21 F6 G12 G15 J18 J9 K13 L22 L5 M17 N10 U14 U6 V9 Y19 K11 K17 L10 L12 L14 L16 M11 M13 M15 N12 N14 N16 P11 P13 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT

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FG(G)676 PackageLX75, LX100, and LX150

Table 2-14:
Bank NA NA NA NA NA NA NA NA NA NA 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 2 2

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number P15 R12 R14 R16 T11 T13 T15 T17 U10 U16 B11 B15 B19 B3 B7 C22 D17 D9 E13 G10 G18 H14 AB23 AD25 M20 P23 T25 U18 V21 W23 Y25 AB14 AC10 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2

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Chapter 2: Pinout Tables

Table 2-14:
Bank 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 5 5 5 5 5 5

FG(G)676 PackageLX75, LX100, and LX150 (Contd)


Pin Description Pin Number AC18 AC21 AE12 AE16 AE20 AE8 Y12 Y17 AC6 AD2 M7 P4 P9 T2 T7 W4 W6 Y2 D2 F4 H2 J6 K4 M2 D25 F23 H25 J21 K23 M25 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5

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FG(G)676 PackageLX75T, LX100T, and LX150T

FG(G)676 PackageLX75T, LX100T, and LX150T


The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/O clock input for the associated pin. For more information see Clock Inputs and BUFIO2 Clocking Regions in Chapter 1.
BUFIO2 Region TL TR RT RB BL BR LT LB Description I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 1 and bank 5 (right). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 3 and bank 4 (left). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 3 (left).

Table 2-15:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FG(G)676 PackageLX75T, LX100T, and LX150T


Pin Description Pin Number H7 G7 H8 G8 F7 F6 C3 B3 G6 F5 E6 E5 H9 G9 A3 A2 F9 E8 D5 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL LX75T LX75T LX75T No Connect (NC)

IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L5P_0 IO_L5N_0 IO_L8P_0 IO_L8N_VREF_0 IO_L13P_0 IO_L13N_0 IO_L14P_0 IO_L14N_0 IO_L15P_0 IO_L15N_0 IO_L16P_0

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Chapter 2: Pinout Tables

Table 2-15:
Bank 0 0 0 0 0 0 0 0 0 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 0 0 0 0 0 0 0 0

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number C5 H10 G10 B4 A4 F10 E10 B5 A5 A6 B6 B11 A10 B10 C7 D7 E9 C9 E11 D9 C12 C11 D11 A8 B8 G12 F11 F12 E12 J11 G11 H12 G13 BUFIO2 Region TL TL TL TL TL TL TL TL TL NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA TL TL TL TL TL TL TL TL LX75T, LX100T LX75T, LX100T LX75T, LX100T LX75T, LX100T LX75T LX75T No Connect (NC) LX75T LX75T LX75T

IO_L16N_0 IO_L21P_0 IO_L21N_0 IO_L22P_0 IO_L22N_0 IO_L23P_0 IO_L23N_0 IO_L24P_0 IO_L24N_0 MGTTXN0_101 MGTTXP0_101 MGTAVCCPLL0_101 MGTREFCLK0N_101 MGTREFCLK0P_101 MGTRXN0_101 MGTRXP0_101 MGTRREF_101 MGTRXN1_101 MGTAVTTRCAL_101 MGTRXP1_101 MGTAVCCPLL1_101 MGTREFCLK1N_101 MGTREFCLK1P_101 MGTTXN1_101 MGTTXP1_101 IO_L30P_0 IO_L30N_0 IO_L31P_0 IO_L31N_0 IO_L32P_0 IO_L32N_0 IO_L33P_0 IO_L33N_0

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FG(G)676 PackageLX75T, LX100T, and LX150T

Table 2-15:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 123 123 123 123 123 123 123 123 123 123 123 123 123 123 0 0 0

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number E13 D13 C13 A13 B12 A12 B14 A14 K12 J12 J13 H13 F14 E14 K14 H14 A18 B18 C14 C15 D15 C17 D17 C19 D19 B15 A16 B16 A20 B20 J15 H15 J16 BUFIO2 Region TL TL TL TL TR TR TR TR TR TR TR TR TR TR TR TR NA NA NA NA NA NA NA NA NA NA NA NA NA NA TR TR TR LX75T, LX100T LX75T, LX100T LX75T, LX100T LX75T, LX100T LX75T, LX100T LX75T, LX100T No Connect (NC)

IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L35N_GCLK16_0 IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L38P_0 IO_L38N_VREF_0 IO_L39P_0 IO_L39N_0 IO_L40P_0 IO_L40N_0 IO_L41P_0 IO_L41N_0 MGTTXN0_123 MGTTXP0_123 MGTAVCCPLL0_123 MGTREFCLK0N_123 MGTREFCLK0P_123 MGTRXN0_123 MGTRXP0_123 MGTRXN1_123 MGTRXP1_123 MGTAVCCPLL1_123 MGTREFCLK1N_123 MGTREFCLK1P_123 MGTTXN1_123 MGTTXP1_123 IO_L43P_0 IO_L43N_0 IO_L48P_0

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Chapter 2: Pinout Tables

Table 2-15:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NA NA NA NA 5 5 5 5

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number J17 F16 E16 G15 F15 F18 E18 G16 F17 F20 E20 H17 G17 C21 B21 H18 H19 B22 A22 G19 F19 B23 A23 D21 D22 A24 C23 F21 G21 H20 G20 B24 A25 BUFIO2 Region TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR NA NA NA NA RT RT RT RT LX75T LX75T LX75T LX75T LX75T LX75T No Connect (NC)

IO_L48N_0 IO_L49P_0 IO_L49N_0 IO_L50P_0 IO_L50N_0 IO_L51P_0 IO_L51N_0 IO_L56P_0 IO_L56N_0 IO_L57P_0 IO_L57N_0 IO_L58P_0 IO_L58N_0 IO_L59P_0 IO_L59N_0 IO_L62P_0 IO_L62N_VREF_0 IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 TCK TDI TMS TDO IO_L1P_A25_5 IO_L1N_A24_VREF_5 IO_L2P_M5A13_5 IO_L2N_M5A14_5

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FG(G)676 PackageLX75T, LX100T, and LX150T

Table 2-15:
Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number K18 K19 D23 C24 H21 H22 F22 G23 J20 J22 E23 E24 L19 K20 C25 C26 B25 B26 K21 K22 M18 M19 F23 G24 J23 J24 E25 E26 D24 D26 F24 F26 H24 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT No Connect (NC)

IO_L3P_M5RESET_5 IO_L3N_M5A11_5 IO_L4P_M5CKE_5 IO_L4N_M5A12_5 IO_L5P_M5A8_5 IO_L5N_M5A9_5 IO_L6P_M5A10_5 IO_L6N_M5A4_5 IO_L7P_M5WE_5 IO_L7N_M5BA2_5 IO_L8P_M5A7_5 IO_L8N_M5A2_5 IO_L9P_M5BA0_5 IO_L9N_M5BA1_5 IO_L10P_M5A0_5 IO_L10N_M5A1_5 IO_L11P_M5CLK_5 IO_L11N_M5CLKN_5 IO_L12P_M5A3_5 IO_L12N_M5ODT_5 IO_L13P_M5A5_5 IO_L13N_M5A6_5 IO_L14P_M5RASN_5 IO_L14N_M5CASN_5 IO_L15P_M5UDM_5 IO_L15N_M5LDM_5 IO_L16P_M5DQ4_5 IO_L16N_M5DQ5_5 IO_L17P_M5DQ6_5 IO_L17N_M5DQ7_5 IO_L18P_M5LDQS_5 IO_L18N_M5LDQSN_5 IO_L19P_M5DQ2_5

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Chapter 2: Pinout Tables

Table 2-15:
Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number H26 G25 G26 K24 K26 J25 J26 M24 M26 L25 L26 N25 N26 M21 M23 L20 L21 N17 N18 L23 L24 N19 N20 N21 N22 P17 P19 N23 N24 R18 R19 P21 P22 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT No Connect (NC)

IO_L19N_M5DQ3_5 IO_L20P_M5DQ0_5 IO_L20N_M5DQ1_5 IO_L21P_M5DQ8_5 IO_L21N_M5DQ9_5 IO_L22P_M5DQ10_5 IO_L22N_M5DQ11_5 IO_L23P_M5UDQS_5 IO_L23N_M5UDQSN_5 IO_L24P_M5DQ12_5 IO_L24N_M5DQ13_5 IO_L25P_M5DQ14_5 IO_L25N_M5DQ15_5 IO_L26P_5 IO_L26N_VREF_5 IO_L27P_5 IO_L27N_5 IO_L28P_1 IO_L28N_VREF_1 IO_L29P_A23_M1A13_1 IO_L29N_A22_M1A14_1 IO_L30P_A21_M1RESET_1 IO_L30N_A20_M1A11_1 IO_L31P_A19_M1CKE_1 IO_L31N_A18_M1A12_1 IO_L32P_A17_M1A8_1 IO_L32N_A16_M1A9_1 IO_L33P_A15_M1A10_1 IO_L33N_A14_M1A4_1 IO_L34P_A13_M1WE_1 IO_L34N_A12_M1BA2_1 IO_L35P_A11_M1A7_1 IO_L35N_A10_M1A2_1

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FG(G)676 PackageLX75T, LX100T, and LX150T

Table 2-15:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number R20 R21 P24 P26 R23 R24 T22 T23 U23 U24 R25 R26 V23 W24 U25 U26 T24 T26 V24 V26 W25 W26 AA25 AA26 AD24 AD26 AB24 AB26 AC25 AC26 Y24 Y26 AE25 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB No Connect (NC)

IO_L36P_A9_M1BA0_1 IO_L36N_A8_M1BA1_1 IO_L37P_A7_M1A0_1 IO_L37N_A6_M1A1_1 IO_L38P_A5_M1CLK_1 IO_L38N_A4_M1CLKN_1 IO_L39P_M1A3_1 IO_L39N_M1ODT_1 IO_L40P_GCLK11_M1A5_1 IO_L40N_GCLK10_M1A6_1 IO_L41P_GCLK9_IRDY1_M1RASN_1 IO_L41N_GCLK8_M1CASN_1 IO_L42P_GCLK7_M1UDM_1 IO_L42N_GCLK6_TRDY1_M1LDM_1 IO_L43P_GCLK5_M1DQ4_1 IO_L43N_GCLK4_M1DQ5_1 IO_L44P_A3_M1DQ6_1 IO_L44N_A2_M1DQ7_1 IO_L45P_A1_M1LDQS_1 IO_L45N_A0_M1LDQSN_1 IO_L46P_FCS_B_M1DQ2_1 IO_L46N_FOE_B_M1DQ3_1 IO_L47P_FWE_B_M1DQ0_1 IO_L47N_LDC_M1DQ1_1 IO_L48P_HDC_M1DQ8_1 IO_L48N_M1DQ9_1 IO_L49P_M1DQ10_1 IO_L49N_M1DQ11_1 IO_L50P_M1UDQS_1 IO_L50N_M1UDQSN_1 IO_L51P_M1DQ12_1 IO_L51N_M1DQ13_1 IO_L52P_M1DQ14_1

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Table 2-15:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 NA NA NA NA 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number AE26 U21 U22 T19 T20 AA23 AA24 U19 U20 V20 V21 AC23 AC24 W22 V19 V22 Y22 Y19 AF25 AE24 AF24 Y21 AA22 AD23 AF23 W20 Y20 AB22 AC22 V18 W19 AD22 AF22 BUFIO2 Region RB RB RB RB RB RB RB RB RB RB RB RB RB NA NA NA NA NA NA BR BR BR BR BR BR BR BR BR BR BR BR BR BR No Connect (NC)

IO_L52N_M1DQ15_1 IO_L53P_1 IO_L53N_VREF_1 IO_L66P_1 IO_L66N_1 IO_L67P_1 IO_L67N_1 IO_L68P_1 IO_L68N_1 IO_L69P_1 IO_L69N_VREF_1 IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1 VFS RFUSE VBATT SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2 IO_L2N_CMPMOSI_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L4P_2 IO_L4N_VREF_2 IO_L5P_2 IO_L5N_2 IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2 IO_L13P_M1_2 IO_L13N_D10_2

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX75T, LX100T, and LX150T

Table 2-15:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 267 267 267 267 267 267 267 267 267 267 267 267 267 267 2 2 2 2 2

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number W17 W18 AA21 AB21 Y17 AA17 U15 V16 AA19 AB19 W16 Y16 AA18 AB17 AE21 AF21 AE16 AE17 AF17 AC20 AD20 AC18 AD18 AD15 AC16 AD16 AE19 AF19 Y15 AA16 V14 V15 U13 BUFIO2 Region BR BR BR BR BR BR BR BR BR BR BR BR BR BR NA NA NA NA NA NA NA NA NA NA NA NA NA NA BR BR BR BR BR LX75T, LX100T LX75T, LX100T LX75T, LX100T LX75T, LX100T LX75T, LX100T LX75T LX75T LX75T LX75T LX75T LX75T No Connect (NC)

IO_L14P_D11_2 IO_L14N_D12_2 IO_L15P_2 IO_L15N_2 IO_L16P_2 IO_L16N_VREF_2 IO_L17P_2 IO_L17N_2 IO_L18P_2 IO_L18N_2 IO_L19P_2 IO_L19N_2 IO_L20P_2 IO_L20N_2 MGTTXP1_267 MGTTXN1_267 MGTAVCCPLL1_267 MGTREFCLK1P_267 MGTREFCLK1N_267 MGTRXP1_267 MGTRXN1_267 MGTRXP0_267 MGTRXN0_267 MGTAVCCPLL0_267 MGTREFCLK0P_267 MGTREFCLK0N_267 MGTTXP0_267 MGTTXN0_267 IO_L24P_2 IO_L24N_VREF_2 IO_L26P_2 IO_L26N_2 IO_L27P_2

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Table 2-15:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 245 245 245 245 245 245 245 245 245 245 245 245 245 245

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number V13 AA15 AB15 AE15 AF15 AB14 AC14 AE13 AF13 AD14 AF14 Y12 AA12 W14 Y13 V12 W12 AB13 AA13 AE9 AF9 AD13 AC12 AD12 AC10 AB12 AD10 AB10 AC8 AD8 AE12 AE11 AF11 BUFIO2 Region BR BR BR BR BR BR BR BL BL BL BL BL BL BL BL BL BL BL BL NA NA NA NA NA NA NA NA NA NA NA NA NA NA LX75T, LX100T LX75T, LX100T LX75T, LX100T LX75T, LX100T No Connect (NC) LX75T, LX100T

IO_L27N_2 IO_L28P_2 IO_L28N_2 IO_L29P_GCLK3_2 IO_L29N_GCLK2_2 IO_L30P_GCLK1_D13_2 IO_L30N_GCLK0_USERCCLK_2 IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2 IO_L32P_GCLK29_2 IO_L32N_GCLK28_2 IO_L33P_2 IO_L33N_2 IO_L34P_2 IO_L34N_2 IO_L35P_2 IO_L35N_2 IO_L36P_2 IO_L36N_2 MGTTXP1_245 MGTTXN1_245 MGTAVCCPLL1_245 MGTREFCLK1P_245 MGTREFCLK1N_245 MGTRXP1_245 MGTAVTTRCAL_245 MGTRXN1_245 MGTRREF_245 MGTRXP0_245 MGTRXN0_245 MGTAVCCPLL0_245 MGTREFCLK0P_245 MGTREFCLK0N_245

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX75T, LX100T, and LX150T

Table 2-15:
Bank 245 245 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number AE7 AF7 Y11 AA11 V11 V10 AA9 AB9 AA10 AB11 AD6 AF6 W10 W9 AE5 AF5 Y9 AA8 AB7 AC6 AC5 AD5 W8 W7 AD4 AF4 AA7 AA6 AE3 AF3 AF2 AB5 AC4 BUFIO2 Region NA NA BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL NA LB LB LX75T LX75T LX75T LX75T LX75T LX75T LX75T LX75T No Connect (NC)

MGTTXP0_245 MGTTXN0_245 IO_L41P_2 IO_L41N_VREF_2 IO_L46P_2 IO_L46N_2 IO_L47P_2 IO_L47N_2 IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L49N_D4_2 IO_L50P_2 IO_L50N_2 IO_L51P_2 IO_L51N_2 IO_L52P_2 IO_L52N_2 IO_L53P_2 IO_L53N_2 IO_L61P_2 IO_L61N_VREF_2 IO_L62P_D5_2 IO_L62N_D6_2 IO_L63P_2 IO_L63N_2 IO_L64P_D8_2 IO_L64N_D9_2 IO_L65P_INIT_B_2 IO_L65N_CSO_B_2 PROGRAM_B_2 IO_L1P_3 IO_L1N_VREF_3

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Chapter 2: Pinout Tables

Table 2-15:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number AA4 AA3 Y6 Y5 AB4 AC3 V7 V6 U4 U3 V5 W5 U9 U8 U7 T6 AB3 AB1 AD3 AD1 AC2 AC1 AE2 AE1 AA2 AA1 Y3 Y1 W2 W1 V3 V1 U2 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB No Connect (NC)

IO_L2P_3 IO_L2N_3 IO_L7P_3 IO_L7N_3 IO_L8P_3 IO_L8N_3 IO_L9P_3 IO_L9N_3 IO_L10P_3 IO_L10N_3 IO_L17P_3 IO_L17N_VREF_3 IO_L18P_3 IO_L18N_3 IO_L31P_3 IO_L31N_VREF_3 IO_L32P_M3DQ14_3 IO_L32N_M3DQ15_3 IO_L33P_M3DQ12_3 IO_L33N_M3DQ13_3 IO_L34P_M3UDQS_3 IO_L34N_M3UDQSN_3 IO_L35P_M3DQ10_3 IO_L35N_M3DQ11_3 IO_L36P_M3DQ8_3 IO_L36N_M3DQ9_3 IO_L37P_M3DQ0_3 IO_L37N_M3DQ1_3 IO_L38P_M3DQ2_3 IO_L38N_M3DQ3_3 IO_L39P_M3LDQS_3 IO_L39N_M3LDQSN_3 IO_L40P_M3DQ6_3

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX75T, LX100T, and LX150T

Table 2-15:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number U1 T3 T1 V4 W3 R7 R6 R2 R1 R8 T8 U5 T4 R10 T9 P3 P1 N6 P6 P5 R5 N8 N7 R4 R3 R9 P8 N5 N4 P10 N9 M10 M9 BUFIO2 Region LB LB LB LB LB LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT No Connect (NC)

IO_L40N_M3DQ7_3 IO_L41P_GCLK27_M3DQ4_3 IO_L41N_GCLK26_M3DQ5_3 IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L42N_GCLK24_M3LDM_3 IO_L43P_GCLK23_M3RASN_3 IO_L43N_GCLK22_IRDY2_M3CASN_3 IO_L44P_GCLK21_M3A5_3 IO_L44N_GCLK20_M3A6_3 IO_L45P_M3A3_3 IO_L45N_M3ODT_3 IO_L46P_M3CLK_3 IO_L46N_M3CLKN_3 IO_L47P_M3A0_3 IO_L47N_M3A1_3 IO_L48P_M3BA0_3 IO_L48N_M3BA1_3 IO_L49P_M3A7_3 IO_L49N_M3A2_3 IO_L50P_M3WE_3 IO_L50N_M3BA2_3 IO_L51P_M3A10_3 IO_L51N_M3A4_3 IO_L52P_M3A8_3 IO_L52N_M3A9_3 IO_L53P_M3CKE_3 IO_L53N_M3A12_3 IO_L54P_M3RESET_3 IO_L54N_M3A11_3 IO_L55P_M3A13_3 IO_L55N_M3A14_3 IO_L57P_3 IO_L57N_VREF_3

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Chapter 2: Pinout Tables

Table 2-15:
Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number M4 N3 N2 N1 M3 M1 L2 L1 K3 K1 J2 J1 H3 H1 G2 G1 F3 F1 E2 E1 D3 D1 J4 J3 L9 L8 L4 L3 M8 M6 K5 J5 L7 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT No Connect (NC)

IO_L58P_4 IO_L58N_VREF_4 IO_L59P_M4DQ14_4 IO_L59N_M4DQ15_4 IO_L60P_M4DQ12_4 IO_L60N_M4DQ13_4 IO_L61P_M4UDQS_4 IO_L61N_M4UDQSN_4 IO_L62P_M4DQ10_4 IO_L62N_M4DQ11_4 IO_L63P_M4DQ8_4 IO_L63N_M4DQ9_4 IO_L64P_M4DQ0_4 IO_L64N_M4DQ1_4 IO_L65P_M4DQ2_4 IO_L65N_M4DQ3_4 IO_L66P_M4LDQS_4 IO_L66N_M4LDQSN_4 IO_L67P_M4DQ6_4 IO_L67N_M4DQ7_4 IO_L68P_M4DQ4_4 IO_L68N_M4DQ5_4 IO_L69P_M4UDM_4 IO_L69N_M4LDM_4 IO_L70P_M4RASN_4 IO_L70N_M4CASN_4 IO_L71P_M4A5_4 IO_L71N_M4A6_4 IO_L72P_M4A3_4 IO_L72N_M4ODT_4 IO_L73P_M4CLK_4 IO_L73N_M4CLKN_4 IO_L74P_M4A0_4

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX75T, LX100T, and LX150T

Table 2-15:
Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number L6 B2 B1 L10 K10 G4 G3 J9 J7 C2 C1 K9 K8 E4 E3 K7 K6 H6 H5 A1 A11 A15 A17 A21 A26 A9 AB16 AB2 AB20 AB25 AC11 AC13 AC15 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

IO_L74N_M4A1_4 IO_L75P_M4BA0_4 IO_L75N_M4BA1_4 IO_L76P_M4A7_4 IO_L76N_M4A2_4 IO_L77P_M4WE_4 IO_L77N_M4BA2_4 IO_L78P_M4A10_4 IO_L78N_M4A4_4 IO_L79P_M4A8_4 IO_L79N_M4A9_4 IO_L80P_M4CKE_4 IO_L80N_M4A12_4 IO_L81P_M4RESET_4 IO_L81N_M4A11_4 IO_L82P_M4A13_4 IO_L82N_M4A14_4 IO_L83P_4 IO_L83N_VREF_4 GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Chapter 2: Pinout Tables

Table 2-15:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number AC17 AD19 AD21 AD7 AD9 AE10 AE18 AE20 AE22 AE6 AE8 AF1 AF10 AF12 AF16 AF18 AF26 B17 B19 B7 B9 C18 C20 C6 C8 D10 D12 D14 D16 D4 E15 E19 E22 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX75T, LX100T, and LX150T

Table 2-15:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number E7 F2 F25 G14 H23 H4 J19 J8 K16 K2 K25 L11 L13 L15 L17 M22 M5 N11 N14 P13 P16 P2 P20 P25 P7 T10 T12 T14 T16 T18 T21 T5 U11 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Chapter 2: Pinout Tables

Table 2-15:
Bank NA NA NA NA NA NA NA NA NA 101 123 245 267 101 123 245 267 101 123 245 267 NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number U17 V2 V25 V8 Y10 Y14 Y23 Y4 Y7 C10 C16 AD11 AD17 D8 D18 AC9 AC19 A7 A19 AF8 AF20 AA5 AB18 AB8 AC21 AC7 D20 D6 E17 G5 J10 J18 K13 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND MGTAVCC_101 MGTAVCC_123 MGTAVCC_245 MGTAVCC_267 MGTAVTTRX_101 MGTAVTTRX_123 MGTAVTTRX_245 MGTAVTTRX_267 MGTAVTTTX_101 MGTAVTTTX_123 MGTAVTTTX_245 MGTAVTTTX_267 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX75T, LX100T, and LX150T

Table 2-15:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number K15 L18 L22 L5 M17 N10 R22 U12 U14 U18 U6 V17 V9 W13 K11 K17 L12 L14 L16 M11 M12 M13 M14 M15 M16 N12 N13 N15 N16 P11 P12 P14 P15 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT

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Chapter 2: Pinout Tables

Table 2-15:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 2

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number R11 R12 R13 R14 R15 R16 R17 T11 T13 T15 T17 U10 U16 B13 C22 C4 E21 F13 F8 G18 H11 H16 J14 AB23 AD25 P18 P23 T25 W21 W23 Y25 AA14 AA20 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2

212

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX75T, LX100T, and LX150T

Table 2-15:
Bank 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 5 5 5 5 5 5 5

FG(G)676 PackageLX75T, LX100T, and LX150T (Contd)


Pin Description Pin Number AB6 AE14 AE23 AE4 W11 W15 Y18 Y8 AD2 P4 P9 T2 T7 W4 W6 Y2 D2 F4 H2 J6 K4 M2 M7 D25 G22 H25 J21 K23 M20 M25 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5

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FG(G)900 PackageLX150
The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/O clock input for the associated pin. For more information see Clock Inputs and BUFIO2 Clocking Regions in Chapter 1.
BUFIO2 Region TL TR RT RB BL BR LT LB Description I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 1 and bank 5 (right). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 3 and bank 4 (left). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 3 (left).

Table 2-16:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FG(G)900 PackageLX150
Pin Description Pin Number G9 F9 G7 F7 G6 F6 G8 F8 E6 D6 E8 D8 J10 G10 C6 A6 B7 A7 D7 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL No Connect (NC)

IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L5P_0 IO_L5N_0 IO_L6P_0 IO_L6N_0 IO_L7P_0 IO_L7N_0 IO_L8P_0 IO_L8N_VREF_0 IO_L9P_0 IO_L9N_0 IO_L10P_0

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX150

Table 2-16:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number C7 J11 H11 E10 D10 C8 A8 D9 C9 K12 J12 G11 F11 B9 A9 C10 A10 D11 C11 G12 F12 E12 D12 B11 A11 C12 A12 D13 C13 J13 H13 G13 F13 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL No Connect (NC)

IO_L10N_0 IO_L11P_0 IO_L11N_0 IO_L12P_0 IO_L12N_0 IO_L13P_0 IO_L13N_0 IO_L14P_0 IO_L14N_0 IO_L15P_0 IO_L15N_0 IO_L16P_0 IO_L16N_0 IO_L17P_0 IO_L17N_0 IO_L18P_0 IO_L18N_0 IO_L19P_0 IO_L19N_0 IO_L20P_0 IO_L20N_0 IO_L21P_0 IO_L21N_0 IO_L22P_0 IO_L22N_0 IO_L23P_0 IO_L23N_0 IO_L24P_0 IO_L24N_0 IO_L25P_0 IO_L25N_0 IO_L26P_0 IO_L26N_0

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Chapter 2: Pinout Tables

Table 2-16:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number K14 J14 G14 F14 E14 D14 B13 A13 C14 A14 J15 H15 G15 F15 D15 C15 B15 A15 C16 A16 C18 A18 B17 A17 E16 D16 G16 F16 D17 C17 G17 F17 J17 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR No Connect (NC)

IO_L27P_0 IO_L27N_0 IO_L28P_0 IO_L28N_0 IO_L29P_0 IO_L29N_0 IO_L30P_0 IO_L30N_0 IO_L31P_0 IO_L31N_0 IO_L32P_0 IO_L32N_0 IO_L33P_0 IO_L33N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L35N_GCLK16_0 IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L38P_0 IO_L38N_VREF_0 IO_L39P_0 IO_L39N_0 IO_L40P_0 IO_L40N_0 IO_L41P_0 IO_L41N_0 IO_L42P_0 IO_L42N_0 IO_L43P_0

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX150

Table 2-16:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number H17 B19 A19 E18 D18 G18 F18 C20 A20 D19 C19 G19 F19 B21 A21 J19 H19 E20 D20 C22 A22 D21 C21 E22 D22 B23 A23 J20 G20 G21 F21 D23 C23 BUFIO2 Region TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR No Connect (NC)

IO_L43N_0 IO_L44P_0 IO_L44N_0 IO_L45P_0 IO_L45N_0 IO_L46P_0 IO_L46N_0 IO_L47P_0 IO_L47N_0 IO_L48P_0 IO_L48N_0 IO_L49P_0 IO_L49N_0 IO_L50P_0 IO_L50N_0 IO_L51P_0 IO_L51N_0 IO_L52P_0 IO_L52N_0 IO_L53P_0 IO_L53N_0 IO_L54P_0 IO_L54N_0 IO_L55P_0 IO_L55N_0 IO_L56P_0 IO_L56N_0 IO_L57P_0 IO_L57N_0 IO_L58P_0 IO_L58N_0 IO_L59P_0 IO_L59N_0

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Chapter 2: Pinout Tables

Table 2-16:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NA NA NA NA 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number G22 F22 E24 D24 G23 F23 B25 A25 C24 A24 J21 H21 D25 C25 F24 H25 K25 G24 G25 F25 A28 A29 C26 A26 B29 B30 B27 A27 F26 F27 E26 D26 C29 BUFIO2 Region TR TR TR TR TR TR TR TR TR TR TR TR TR TR NA NA NA NA RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT No Connect (NC)

IO_L60P_0 IO_L60N_0 IO_L61P_0 IO_L61N_0 IO_L62P_0 IO_L62N_VREF_0 IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 TCK TDI TMS TDO IO_L1P_A25_5 IO_L1N_A24_VREF_5 IO_L2P_M5A13_5 IO_L2N_M5A14_5 IO_L3P_M5RESET_5 IO_L3N_M5A11_5 IO_L4P_M5CKE_5 IO_L4N_M5A12_5 IO_L5P_M5A8_5 IO_L5N_M5A9_5 IO_L6P_M5A10_5 IO_L6N_M5A4_5 IO_L7P_M5WE_5 IO_L7N_M5BA2_5 IO_L8P_M5A7_5

218

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX150

Table 2-16:
Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number C30 D27 C27 D28 D30 E27 E28 E29 E30 H26 H27 K26 K27 J27 J28 G27 G28 F28 F30 J29 J30 G29 G30 H28 H30 L27 L28 L29 L30 K28 K30 M26 M27 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT No Connect (NC)

IO_L8N_M5A2_5 IO_L9P_M5BA0_5 IO_L9N_M5BA1_5 IO_L10P_M5A0_5 IO_L10N_M5A1_5 IO_L11P_M5CLK_5 IO_L11N_M5CLKN_5 IO_L12P_M5A3_5 IO_L12N_M5ODT_5 IO_L13P_M5A5_5 IO_L13N_M5A6_5 IO_L14P_M5RASN_5 IO_L14N_M5CASN_5 IO_L15P_M5UDM_5 IO_L15N_M5LDM_5 IO_L16P_M5DQ4_5 IO_L16N_M5DQ5_5 IO_L17P_M5DQ6_5 IO_L17N_M5DQ7_5 IO_L18P_M5LDQS_5 IO_L18N_M5LDQSN_5 IO_L19P_M5DQ2_5 IO_L19N_M5DQ3_5 IO_L20P_M5DQ0_5 IO_L20N_M5DQ1_5 IO_L21P_M5DQ8_5 IO_L21N_M5DQ9_5 IO_L22P_M5DQ10_5 IO_L22N_M5DQ11_5 IO_L23P_M5UDQS_5 IO_L23N_M5UDQSN_5 IO_L24P_M5DQ12_5 IO_L24N_M5DQ13_5

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Chapter 2: Pinout Tables

Table 2-16:
Bank 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number M28 M30 N24 N25 L24 L25 M23 M24 N29 N30 N27 N28 P28 P30 P26 P27 R29 R30 R27 R28 T26 T27 T28 T30 U29 U30 U27 U28 V28 V30 V26 V27 W27 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT No Connect (NC)

IO_L25P_M5DQ14_5 IO_L25N_M5DQ15_5 IO_L26P_5 IO_L26N_VREF_5 IO_L27P_5 IO_L27N_5 IO_L28P_1 IO_L28N_VREF_1 IO_L29P_A23_M1A13_1 IO_L29N_A22_M1A14_1 IO_L30P_A21_M1RESET_1 IO_L30N_A20_M1A11_1 IO_L31P_A19_M1CKE_1 IO_L31N_A18_M1A12_1 IO_L32P_A17_M1A8_1 IO_L32N_A16_M1A9_1 IO_L33P_A15_M1A10_1 IO_L33N_A14_M1A4_1 IO_L34P_A13_M1WE_1 IO_L34N_A12_M1BA2_1 IO_L35P_A11_M1A7_1 IO_L35N_A10_M1A2_1 IO_L36P_A9_M1BA0_1 IO_L36N_A8_M1BA1_1 IO_L37P_A7_M1A0_1 IO_L37N_A6_M1A1_1 IO_L38P_A5_M1CLK_1 IO_L38N_A4_M1CLKN_1 IO_L39P_M1A3_1 IO_L39N_M1ODT_1 IO_L40P_GCLK11_M1A5_1 IO_L40N_GCLK10_M1A6_1 IO_L41P_GCLK9_IRDY1_M1RASN_1

220

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX150

Table 2-16:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number W28 AB28 AB30 W29 W30 Y28 Y30 AA29 AA30 AA27 AA28 Y26 Y27 AD28 AD30 AC27 AC28 AC29 AC30 AE29 AE30 AE27 AE28 W24 W25 R21 R22 AF28 AF30 P22 P23 AG29 AG30 BUFIO2 Region RT RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB No Connect (NC)

IO_L41N_GCLK8_M1CASN_1 IO_L42P_GCLK7_M1UDM_1 IO_L42N_GCLK6_TRDY1_M1LDM_1 IO_L43P_GCLK5_M1DQ4_1 IO_L43N_GCLK4_M1DQ5_1 IO_L44P_A3_M1DQ6_1 IO_L44N_A2_M1DQ7_1 IO_L45P_A1_M1LDQS_1 IO_L45N_A0_M1LDQSN_1 IO_L46P_FCS_B_M1DQ2_1 IO_L46N_FOE_B_M1DQ3_1 IO_L47P_FWE_B_M1DQ0_1 IO_L47N_LDC_M1DQ1_1 IO_L48P_HDC_M1DQ8_1 IO_L48N_M1DQ9_1 IO_L49P_M1DQ10_1 IO_L49N_M1DQ11_1 IO_L50P_M1UDQS_1 IO_L50N_M1UDQSN_1 IO_L51P_M1DQ12_1 IO_L51N_M1DQ13_1 IO_L52P_M1DQ14_1 IO_L52N_M1DQ15_1 IO_L53P_1 IO_L53N_VREF_1 IO_L54P_1 IO_L54N_1 IO_L55P_1 IO_L55N_1 IO_L56P_1 IO_L56N_1 IO_L57P_1 IO_L57N_1

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221

Chapter 2: Pinout Tables

Table 2-16:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number P24 P25 AH30 AJ30 R24 R25 AJ29 AK29 T24 T25 AJ28 AK28 U24 U25 AG27 AG28 V23 V24 AD26 AD27 W21 W22 AH27 AK27 Y22 Y23 AE25 AE26 Y24 Y25 AG26 AH26 AA24 BUFIO2 Region RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB No Connect (NC)

IO_L58P_1 IO_L58N_1 IO_L59P_1 IO_L59N_1 IO_L60P_1 IO_L60N_1 IO_L61P_1 IO_L61N_1 IO_L62P_1 IO_L62N_1 IO_L63P_1 IO_L63N_1 IO_L64P_1 IO_L64N_1 IO_L65P_1 IO_L65N_1 IO_L66P_1 IO_L66N_1 IO_L67P_1 IO_L67N_1 IO_L68P_1 IO_L68N_1 IO_L69P_1 IO_L69N_VREF_1 IO_L70P_1 IO_L70N_1 IO_L71P_1 IO_L71N_1 IO_L72P_1 IO_L72N_1 IO_L73P_1 IO_L73N_1 IO_L74P_AWAKE_1

222

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX150

Table 2-16:
Bank 1 NA NA NA NA 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number AA25 AF27 AB27 AB26 AB25 AC25 AD25 AJ26 AK26 AD24 AE24 AH25 AK25 AF25 AG25 AG24 AH24 AD23 AE23 AD22 AE22 AC21 AD21 AF23 AG23 AD20 AE20 AJ24 AK24 AH23 AK23 AJ22 AK22 BUFIO2 Region RB NA NA NA NA NA NA BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR No Connect (NC)

IO_L74N_DOUT_BUSY_1 VFS RFUSE VBATT SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2 IO_L2N_CMPMOSI_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L4P_2 IO_L4N_VREF_2 IO_L5P_2 IO_L5N_2 IO_L6P_2 IO_L6N_2 IO_L7P_2 IO_L7N_2 IO_L8P_2 IO_L8N_2 IO_L9P_2 IO_L9N_2 IO_L10P_2 IO_L10N_2 IO_L11P_2 IO_L11N_2 IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2 IO_L13P_M1_2 IO_L13N_D10_2

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223

Chapter 2: Pinout Tables

Table 2-16:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number AH21 AK21 AG22 AH22 AJ20 AK20 AF21 AG21 AB20 AC20 AD19 AE19 AG20 AH20 AD18 AE18 AA19 AB19 AF19 AG19 AG18 AH18 AB18 AC18 AF17 AG17 AD17 AE17 AD16 AE16 AH19 AK19 AJ18 BUFIO2 Region BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR No Connect (NC)

IO_L14P_D11_2 IO_L14N_D12_2 IO_L15P_2 IO_L15N_2 IO_L16P_2 IO_L16N_VREF_2 IO_L17P_2 IO_L17N_2 IO_L18P_2 IO_L18N_2 IO_L19P_2 IO_L19N_2 IO_L20P_2 IO_L20N_2 IO_L21P_2 IO_L21N_2 IO_L22P_2 IO_L22N_2 IO_L23P_2 IO_L23N_2 IO_L24P_2 IO_L24N_VREF_2 IO_L25P_2 IO_L25N_2 IO_L26P_2 IO_L26N_2 IO_L27P_2 IO_L27N_2 IO_L28P_2 IO_L28N_2 IO_L29P_GCLK3_2 IO_L29N_GCLK2_2 IO_L30P_GCLK1_D13_2

224

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX150

Table 2-16:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number AK18 AJ16 AK16 AH17 AK17 AB16 AC16 AF15 AG15 AG16 AH16 AD15 AE15 AA15 AB15 AH15 AK15 AJ14 AK14 AB14 AC14 AH13 AK13 AD14 AE14 AF13 AG13 AG14 AH14 AG12 AH12 AD13 AE13 BUFIO2 Region BR BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL No Connect (NC)

IO_L30N_GCLK0_USERCCLK_2 IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2 IO_L32P_GCLK29_2 IO_L32N_GCLK28_2 IO_L33P_2 IO_L33N_2 IO_L34P_2 IO_L34N_2 IO_L35P_2 IO_L35N_2 IO_L36P_2 IO_L36N_2 IO_L37P_2 IO_L37N_2 IO_L38P_2 IO_L38N_2 IO_L39P_2 IO_L39N_2 IO_L40P_2 IO_L40N_2 IO_L41P_2 IO_L41N_VREF_2 IO_L42P_2 IO_L42N_2 IO_L43P_2 IO_L43N_2 IO_L44P_2 IO_L44N_2 IO_L45P_2 IO_L45N_2 IO_L46P_2 IO_L46N_2

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225

Chapter 2: Pinout Tables

Table 2-16:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number AD12 AE12 AH11 AK11 AJ12 AK12 AB12 AC12 AF11 AG11 AB11 AD11 AJ10 AK10 AH9 AK9 AG10 AH10 AD10 AE10 AF9 AG9 AG8 AH8 AF7 AG7 AD9 AE9 AD8 AE8 AJ8 AK8 AG6 BUFIO2 Region BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL No Connect (NC)

IO_L47P_2 IO_L47N_2 IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L49N_D4_2 IO_L50P_2 IO_L50N_2 IO_L51P_2 IO_L51N_2 IO_L52P_2 IO_L52N_2 IO_L53P_2 IO_L53N_2 IO_L54P_2 IO_L54N_2 IO_L55P_2 IO_L55N_2 IO_L56P_2 IO_L56N_2 IO_L57P_2 IO_L57N_2 IO_L58P_2 IO_L58N_2 IO_L59P_2 IO_L59N_2 IO_L60P_2 IO_L60N_2 IO_L61P_2 IO_L61N_VREF_2 IO_L62P_D5_2 IO_L62N_D6_2 IO_L63P_2

226

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX150

Table 2-16:
Bank 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number AH6 AH7 AK7 AJ6 AK6 AB8 AA10 AA9 AD7 AE7 Y9 Y8 AE6 AF6 AA12 AA11 AE5 AG5 T7 T6 AA7 AA6 AC6 AD6 AH5 AK5 W10 W9 AB7 AB6 W7 W6 AJ4 BUFIO2 Region BL BL BL BL BL NA LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB No Connect (NC)

IO_L63N_2 IO_L64P_D8_2 IO_L64N_D9_2 IO_L65P_INIT_B_2 IO_L65N_CSO_B_2 PROGRAM_B_2 IO_L1P_3 IO_L1N_VREF_3 IO_L2P_3 IO_L2N_3 IO_L3P_3 IO_L3N_3 IO_L4P_3 IO_L4N_3 IO_L5P_3 IO_L5N_3 IO_L6P_3 IO_L6N_3 IO_L7P_3 IO_L7N_3 IO_L8P_3 IO_L8N_3 IO_L9P_3 IO_L9N_3 IO_L10P_3 IO_L10N_3 IO_L11P_3 IO_L11N_3 IO_L12P_3 IO_L12N_3 IO_L13P_3 IO_L13N_3 IO_L14P_3

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

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227

Chapter 2: Pinout Tables

Table 2-16:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number AK4 T9 T8 AH3 AK3 Y7 Y6 AJ2 AK2 AE4 AF4 AF3 AG3 V8 V7 AH1 AJ1 V10 V9 AG4 AH4 N10 N9 AF2 AH2 R7 R6 AF1 AG1 U7 U6 AE3 AE1 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB No Connect (NC)

IO_L14N_3 IO_L15P_3 IO_L15N_3 IO_L16P_3 IO_L16N_3 IO_L17P_3 IO_L17N_VREF_3 IO_L18P_3 IO_L18N_3 IO_L19P_3 IO_L19N_3 IO_L20P_3 IO_L20N_3 IO_L21P_3 IO_L21N_3 IO_L22P_3 IO_L22N_3 IO_L23P_3 IO_L23N_3 IO_L24P_3 IO_L24N_3 IO_L25P_3 IO_L25N_3 IO_L26P_3 IO_L26N_3 IO_L27P_3 IO_L27N_3 IO_L28P_3 IO_L28N_3 IO_L29P_3 IO_L29N_3 IO_L30P_3 IO_L30N_3

228

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX150

Table 2-16:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number N8 N7 AC5 AC4 AD4 AD3 AB4 AB3 AD2 AD1 AC3 AC1 Y4 Y3 Y2 Y1 AA5 AA4 W3 W1 AA3 AA1 AB2 AB1 W5 W4 V4 V3 V2 V1 U5 U4 U3 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LT LT LT LT LT LT LT LT LT No Connect (NC)

IO_L31P_3 IO_L31N_VREF_3 IO_L32P_M3DQ14_3 IO_L32N_M3DQ15_3 IO_L33P_M3DQ12_3 IO_L33N_M3DQ13_3 IO_L34P_M3UDQS_3 IO_L34N_M3UDQSN_3 IO_L35P_M3DQ10_3 IO_L35N_M3DQ11_3 IO_L36P_M3DQ8_3 IO_L36N_M3DQ9_3 IO_L37P_M3DQ0_3 IO_L37N_M3DQ1_3 IO_L38P_M3DQ2_3 IO_L38N_M3DQ3_3 IO_L39P_M3LDQS_3 IO_L39N_M3LDQSN_3 IO_L40P_M3DQ6_3 IO_L40N_M3DQ7_3 IO_L41P_GCLK27_M3DQ4_3 IO_L41N_GCLK26_M3DQ5_3 IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L42N_GCLK24_M3LDM_3 IO_L43P_GCLK23_M3RASN_3 IO_L43N_GCLK22_IRDY2_M3CASN_3 IO_L44P_GCLK21_M3A5_3 IO_L44N_GCLK20_M3A6_3 IO_L45P_M3A3_3 IO_L45N_M3ODT_3 IO_L46P_M3CLK_3 IO_L46N_M3CLKN_3 IO_L47P_M3A0_3

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229

Chapter 2: Pinout Tables

Table 2-16:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number U1 T4 T3 T2 T1 R5 R4 R3 R1 P4 P3 N5 N4 P2 P1 N3 N1 P7 P6 M7 M6 L7 L6 M2 M1 L3 L1 K2 K1 L5 L4 M4 M3 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT No Connect (NC)

IO_L47N_M3A1_3 IO_L48P_M3BA0_3 IO_L48N_M3BA1_3 IO_L49P_M3A7_3 IO_L49N_M3A2_3 IO_L50P_M3WE_3 IO_L50N_M3BA2_3 IO_L51P_M3A10_3 IO_L51N_M3A4_3 IO_L52P_M3A8_3 IO_L52N_M3A9_3 IO_L53P_M3CKE_3 IO_L53N_M3A12_3 IO_L54P_M3RESET_3 IO_L54N_M3A11_3 IO_L55P_M3A13_3 IO_L55N_M3A14_3 IO_L56P_3 IO_L56N_3 IO_L57P_3 IO_L57N_VREF_3 IO_L58P_4 IO_L58N_VREF_4 IO_L59P_M4DQ14_4 IO_L59N_M4DQ15_4 IO_L60P_M4DQ12_4 IO_L60N_M4DQ13_4 IO_L61P_M4UDQS_4 IO_L61N_M4UDQSN_4 IO_L62P_M4DQ10_4 IO_L62N_M4DQ11_4 IO_L63P_M4DQ8_4 IO_L63N_M4DQ9_4

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FG(G)900 PackageLX150

Table 2-16:
Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number H4 H3 J3 J1 J5 J4 H2 H1 G3 G1 K4 K3 C1 B1 F2 F1 E5 E4 E3 E1 D4 D3 D2 D1 B3 A3 F4 F3 D5 C5 B2 A2 C4 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT No Connect (NC)

IO_L64P_M4DQ0_4 IO_L64N_M4DQ1_4 IO_L65P_M4DQ2_4 IO_L65N_M4DQ3_4 IO_L66P_M4LDQS_4 IO_L66N_M4LDQSN_4 IO_L67P_M4DQ6_4 IO_L67N_M4DQ7_4 IO_L68P_M4DQ4_4 IO_L68N_M4DQ5_4 IO_L69P_M4UDM_4 IO_L69N_M4LDM_4 IO_L70P_M4RASN_4 IO_L70N_M4CASN_4 IO_L71P_M4A5_4 IO_L71N_M4A6_4 IO_L72P_M4A3_4 IO_L72N_M4ODT_4 IO_L73P_M4CLK_4 IO_L73N_M4CLKN_4 IO_L74P_M4A0_4 IO_L74N_M4A1_4 IO_L75P_M4BA0_4 IO_L75N_M4BA1_4 IO_L76P_M4A7_4 IO_L76N_M4A2_4 IO_L77P_M4WE_4 IO_L77N_M4BA2_4 IO_L78P_M4A10_4 IO_L78N_M4A4_4 IO_L79P_M4A8_4 IO_L79N_M4A9_4 IO_L80P_M4CKE_4

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Table 2-16:
Bank 4 4 4 4 4 4 4 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number A4 G5 G4 B5 A5 J6 H6 A1 A30 AA13 AA17 AA2 AA20 AA22 AA26 AB10 AB21 AB22 AB23 AB24 AB29 AB5 AC10 AC13 AC17 AC23 AC8 AE2 AF10 AF14 AF18 AF22 AF26 BUFIO2 Region LT LT LT LT LT LT LT NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

IO_L80N_M4A12_4 IO_L81P_M4RESET_4 IO_L81N_M4A11_4 IO_L82P_M4A13_4 IO_L82N_M4A14_4 IO_L83P_4 IO_L83N_VREF_4 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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FG(G)900 PackageLX150

Table 2-16:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number AF29 AF5 AH28 AJ13 AJ17 AJ21 AJ25 AJ5 AJ9 AK1 AK30 B10 B14 B18 B22 B26 B6 C28 C3 E13 E17 E2 E21 E25 E9 F29 F5 H12 H16 H20 H23 H8 H9 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Table 2-16:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number J18 J2 J22 J24 J26 J7 J9 K10 K16 K18 K21 K22 K23 K29 K5 K7 K8 L10 L11 L13 L14 L17 L18 L21 L23 L9 M10 M13 M14 M17 M18 M21 M22 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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FG(G)900 PackageLX150

Table 2-16:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number M8 N11 N12 N15 N16 N19 N2 N20 N22 N26 P11 P12 P15 P16 P19 P20 P29 P5 P9 R10 R13 R14 R17 R18 R8 T13 T14 T17 T18 T22 T23 U11 U12 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Chapter 2: Pinout Tables

Table 2-16:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number U15 U16 U19 U2 U20 U21 U22 U26 U9 V11 V12 V15 V16 V19 V20 V22 V29 V5 W13 W14 W17 W18 W23 W8 Y11 Y13 Y14 Y17 Y18 Y21 AA16 K15 K19 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCINT VCCINT VCCINT

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FG(G)900 PackageLX150

Table 2-16:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number K20 L12 L15 L16 L19 L20 M11 M12 M15 M16 M19 M20 N13 N14 N17 N18 P13 P14 P17 P18 R11 R12 R15 R16 R19 R20 T10 T11 T12 T15 T16 T19 T20 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT

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Table 2-16:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number U13 U14 U17 U18 V13 V14 V17 V18 W11 W12 W15 W16 W19 W20 Y12 Y15 Y16 Y19 Y20 K17 K9 L22 M25 N21 N6 P10 R9 T21 U10 V25 V6 AA21 AB13 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX

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FG(G)900 PackageLX150

Table 2-16:
Bank NA NA NA NA NA NA NA NA NA NA NA NA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number AB17 AB9 AC24 AC7 AE11 AE21 F10 F20 H24 J23 J8 K13 B12 B16 B20 B24 B8 E11 E15 E19 E23 E7 H10 H14 H18 H22 H7 J16 K11 N23 P21 R23 R26 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1

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Chapter 2: Pinout Tables

Table 2-16:
Bank 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number T29 U23 V21 W26 Y29 AA23 AC26 AD29 AH29 AJ27 AA14 AA18 AC11 AC15 AC19 AC22 AC9 AF12 AF16 AF20 AF24 AF8 AJ11 AJ15 AJ19 AJ23 AJ7 AA8 AC2 AD5 AG2 AJ3 L8 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3

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FG(G)900 PackageLX150

Table 2-16:
Bank 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5

FG(G)900 PackageLX150 (Contd)


Pin Description Pin Number M9 P8 R2 T5 U8 W2 Y10 Y5 K6 L2 M5 B4 C2 G2 H5 K24 L26 M29 B28 D29 G26 H29 J25 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5

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FG(G)900 PackageLX100T and LX150T


The BUFIO2 clocking region column lists the BUFIO2 clock sources that connect to the I/O clock input for the associated pin. For more information see Clock Inputs and BUFIO2 Clocking Regions in Chapter 1.
BUFIO2 Region TL TR RT RB BL BR LT LB Description I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 0 (top). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 1 and bank 5 (right). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 1 (right). I/O clock is driven by any one of the four BUFIO2s located in the left side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the right side of bank 2 (bottom). I/O clock is driven by any one of the four BUFIO2s located in the top side of bank 3 and bank 4 (left). I/O clock is driven by any one of the four BUFIO2s located in the bottom side of bank 3 (left).

Table 2-17:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FG(G)900 PackageLX100T and LX150T


Pin Description Pin Number H9 G9 F6 E6 J8 H8 D6 C6 H7 G7 E7 D7 M10 L10 B6 A6 K10 J10 F8 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL No Connect (NC)

IO_L1P_HSWAPEN_0 IO_L1N_VREF_0 IO_L2P_0 IO_L2N_0 IO_L3P_0 IO_L3N_0 IO_L4P_0 IO_L4N_0 IO_L5P_0 IO_L5N_0 IO_L6P_0 IO_L6N_0 IO_L7P_0 IO_L7N_0 IO_L8P_0 IO_L8N_VREF_0 IO_L9P_0 IO_L9N_0 IO_L10P_0

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FG(G)900 PackageLX100T and LX150T

Table 2-17:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number E8 L11 K11 D8 C8 B7 A7 G10 F10 L12 K12 F9 E9 J12 H12 F11 E11 J13 H13 H11 G11 M13 L13 G12 F12 L14 K14 F13 E13 M15 K15 G14 F14 BUFIO2 Region TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL TL LX100T LX100T LX100T LX100T LX100T LX100T LX100T LX100T LX100T LX100T LX100T LX100T LX100T LX100T No Connect (NC)

IO_L10N_0 IO_L11P_0 IO_L11N_0 IO_L12P_0 IO_L12N_0 IO_L13P_0 IO_L13N_0 IO_L14P_0 IO_L14N_0 IO_L15P_0 IO_L15N_0 IO_L16P_0 IO_L16N_0 IO_L17P_0 IO_L17N_0 IO_L18P_0 IO_L18N_0 IO_L19P_0 IO_L19N_0 IO_L20P_0 IO_L20N_0 IO_L21P_0 IO_L21N_0 IO_L22P_0 IO_L22N_0 IO_L23P_0 IO_L23N_0 IO_L24P_0 IO_L24N_0 IO_L25P_0 IO_L25N_0 IO_L26P_0 IO_L26N_0

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Table 2-17:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number J14 H14 F15 E15 H15 G15 B15 A15 C16 A16 E16 D16 B17 A17 L17 K17 H17 G17 H16 G16 G18 F18 M18 L18 F17 E17 K19 J19 F19 E19 M19 L19 H19 BUFIO2 Region TL TL TL TL TL TL TL TL TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR LX100T LX100T No Connect (NC)

IO_L32P_0 IO_L32N_0 IO_L33P_0 IO_L33N_0 IO_L34P_GCLK19_0 IO_L34N_GCLK18_0 IO_L35P_GCLK17_0 IO_L35N_GCLK16_0 IO_L36P_GCLK15_0 IO_L36N_GCLK14_0 IO_L37P_GCLK13_0 IO_L37N_GCLK12_0 IO_L38P_0 IO_L38N_VREF_0 IO_L43P_0 IO_L43N_0 IO_L44P_0 IO_L44N_0 IO_L45P_0 IO_L45N_0 IO_L46P_0 IO_L46N_0 IO_L47P_0 IO_L47N_0 IO_L48P_0 IO_L48N_0 IO_L49P_0 IO_L49N_0 IO_L50P_0 IO_L50N_0 IO_L51P_0 IO_L51N_0 IO_L52P_0

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FG(G)900 PackageLX100T and LX150T

Table 2-17:
Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NA NA 101 101

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number G19 J18 H18 G20 F20 K20 J20 F21 E21 M20 L20 G22 F22 L21 K21 F23 E23 H21 G21 F24 E24 B25 A25 D24 C24 J22 H22 E25 D25 H23 J24 A9 B9 BUFIO2 Region TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR TR NA NA NA NA LX100T LX100T LX100T LX100T LX100T LX100T No Connect (NC)

IO_L52N_0 IO_L53P_0 IO_L53N_0 IO_L54P_0 IO_L54N_0 IO_L55P_0 IO_L55N_0 IO_L56P_0 IO_L56N_0 IO_L57P_0 IO_L57N_0 IO_L58P_0 IO_L58N_0 IO_L59P_0 IO_L59N_0 IO_L60P_0 IO_L60N_0 IO_L61P_0 IO_L61N_0 IO_L62P_0 IO_L62N_VREF_0 IO_L63P_SCP7_0 IO_L63N_SCP6_0 IO_L64P_SCP5_0 IO_L64N_SCP4_0 IO_L65P_SCP3_0 IO_L65N_SCP2_0 IO_L66P_SCP1_0 IO_L66N_SCP0_0 TCK TDI MGTTXN0_101 MGTTXP0_101

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Table 2-17:
Bank 101 101 101 101 101 101 101 101 101 101 101 101 101 101 123 123 123 123 123 123 123 123 123 123 123 123 123 123 NA NA 5 5 5

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number B14 A13 B13 C10 D10 E12 C12 E14 D12 C15 C14 D14 A11 B11 A21 B21 C17 C18 D18 C20 D20 C22 D22 B18 A19 B19 A23 B23 K25 H25 G25 F25 A28 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA RT RT RT No Connect (NC)

MGTAVCCPLL0_101 MGTREFCLK0N_101 MGTREFCLK0P_101 MGTRXN0_101 MGTRXP0_101 MGTRREF_101 MGTRXN1_101 MGTAVTTRCAL_101 MGTRXP1_101 MGTAVCCPLL1_101 MGTREFCLK1N_101 MGTREFCLK1P_101 MGTTXN1_101 MGTTXP1_101 MGTTXN0_123 MGTTXP0_123 MGTAVCCPLL0_123 MGTREFCLK0N_123 MGTREFCLK0P_123 MGTRXN0_123 MGTRXP0_123 MGTRXN1_123 MGTRXP1_123 MGTAVCCPLL1_123 MGTREFCLK1N_123 MGTREFCLK1P_123 MGTTXN1_123 MGTTXP1_123 TMS TDO IO_L1P_A25_5 IO_L1N_A24_VREF_5 IO_L2P_M5A13_5

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FG(G)900 PackageLX100T and LX150T

Table 2-17:
Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number A29 C26 A26 B29 B30 B27 A27 F26 F27 E26 D26 C29 C30 D27 C27 D28 D30 E27 E28 E29 E30 H26 H27 K26 K27 J27 J28 G27 G28 F28 F30 J29 J30 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT No Connect (NC)

IO_L2N_M5A14_5 IO_L3P_M5RESET_5 IO_L3N_M5A11_5 IO_L4P_M5CKE_5 IO_L4N_M5A12_5 IO_L5P_M5A8_5 IO_L5N_M5A9_5 IO_L6P_M5A10_5 IO_L6N_M5A4_5 IO_L7P_M5WE_5 IO_L7N_M5BA2_5 IO_L8P_M5A7_5 IO_L8N_M5A2_5 IO_L9P_M5BA0_5 IO_L9N_M5BA1_5 IO_L10P_M5A0_5 IO_L10N_M5A1_5 IO_L11P_M5CLK_5 IO_L11N_M5CLKN_5 IO_L12P_M5A3_5 IO_L12N_M5ODT_5 IO_L13P_M5A5_5 IO_L13N_M5A6_5 IO_L14P_M5RASN_5 IO_L14N_M5CASN_5 IO_L15P_M5UDM_5 IO_L15N_M5LDM_5 IO_L16P_M5DQ4_5 IO_L16N_M5DQ5_5 IO_L17P_M5DQ6_5 IO_L17N_M5DQ7_5 IO_L18P_M5LDQS_5 IO_L18N_M5LDQSN_5

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Table 2-17:
Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number G29 G30 H28 H30 L27 L28 L29 L30 K28 K30 M26 M27 M28 M30 N24 N25 L24 L25 M23 M24 N29 N30 N27 N28 P28 P30 P26 P27 R29 R30 R27 R28 T26 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT RT No Connect (NC)

IO_L19P_M5DQ2_5 IO_L19N_M5DQ3_5 IO_L20P_M5DQ0_5 IO_L20N_M5DQ1_5 IO_L21P_M5DQ8_5 IO_L21N_M5DQ9_5 IO_L22P_M5DQ10_5 IO_L22N_M5DQ11_5 IO_L23P_M5UDQS_5 IO_L23N_M5UDQSN_5 IO_L24P_M5DQ12_5 IO_L24N_M5DQ13_5 IO_L25P_M5DQ14_5 IO_L25N_M5DQ15_5 IO_L26P_5 IO_L26N_VREF_5 IO_L27P_5 IO_L27N_5 IO_L28P_1 IO_L28N_VREF_1 IO_L29P_A23_M1A13_1 IO_L29N_A22_M1A14_1 IO_L30P_A21_M1RESET_1 IO_L30N_A20_M1A11_1 IO_L31P_A19_M1CKE_1 IO_L31N_A18_M1A12_1 IO_L32P_A17_M1A8_1 IO_L32N_A16_M1A9_1 IO_L33P_A15_M1A10_1 IO_L33N_A14_M1A4_1 IO_L34P_A13_M1WE_1 IO_L34N_A12_M1BA2_1 IO_L35P_A11_M1A7_1

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX100T and LX150T

Table 2-17:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number T27 T28 T30 U29 U30 U27 U28 V28 V30 V26 V27 W27 W28 AB28 AB30 W29 W30 Y28 Y30 AA29 AA30 AA27 AA28 Y26 Y27 AD28 AD30 AC27 AC28 AC29 AC30 AE29 AE30 BUFIO2 Region RT RT RT RT RT RT RT RT RT RT RT RT RT RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB No Connect (NC)

IO_L35N_A10_M1A2_1 IO_L36P_A9_M1BA0_1 IO_L36N_A8_M1BA1_1 IO_L37P_A7_M1A0_1 IO_L37N_A6_M1A1_1 IO_L38P_A5_M1CLK_1 IO_L38N_A4_M1CLKN_1 IO_L39P_M1A3_1 IO_L39N_M1ODT_1 IO_L40P_GCLK11_M1A5_1 IO_L40N_GCLK10_M1A6_1 IO_L41P_GCLK9_IRDY1_M1RASN_1 IO_L41N_GCLK8_M1CASN_1 IO_L42P_GCLK7_M1UDM_1 IO_L42N_GCLK6_TRDY1_M1LDM_1 IO_L43P_GCLK5_M1DQ4_1 IO_L43N_GCLK4_M1DQ5_1 IO_L44P_A3_M1DQ6_1 IO_L44N_A2_M1DQ7_1 IO_L45P_A1_M1LDQS_1 IO_L45N_A0_M1LDQSN_1 IO_L46P_FCS_B_M1DQ2_1 IO_L46N_FOE_B_M1DQ3_1 IO_L47P_FWE_B_M1DQ0_1 IO_L47N_LDC_M1DQ1_1 IO_L48P_HDC_M1DQ8_1 IO_L48N_M1DQ9_1 IO_L49P_M1DQ10_1 IO_L49N_M1DQ11_1 IO_L50P_M1UDQS_1 IO_L50N_M1UDQSN_1 IO_L51P_M1DQ12_1 IO_L51N_M1DQ13_1

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249

Chapter 2: Pinout Tables

Table 2-17:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number AE27 AE28 W24 W25 R21 R22 AF28 AF30 P22 P23 AG29 AG30 P24 P25 AH30 AJ30 R24 R25 AJ29 AK29 T24 T25 AJ28 AK28 U24 U25 AG27 AG28 V23 V24 AD26 AD27 W21 BUFIO2 Region RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB RB No Connect (NC)

IO_L52P_M1DQ14_1 IO_L52N_M1DQ15_1 IO_L53P_1 IO_L53N_VREF_1 IO_L54P_1 IO_L54N_1 IO_L55P_1 IO_L55N_1 IO_L56P_1 IO_L56N_1 IO_L57P_1 IO_L57N_1 IO_L58P_1 IO_L58N_1 IO_L59P_1 IO_L59N_1 IO_L60P_1 IO_L60N_1 IO_L61P_1 IO_L61N_1 IO_L62P_1 IO_L62N_1 IO_L63P_1 IO_L63N_1 IO_L64P_1 IO_L64N_1 IO_L65P_1 IO_L65N_1 IO_L66P_1 IO_L66N_1 IO_L67P_1 IO_L67N_1 IO_L68P_1

250

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX100T and LX150T

Table 2-17:
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 NA NA NA NA 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number W22 AH27 AK27 Y22 Y23 AE25 AE26 Y24 Y25 AG26 AH26 AA24 AA25 AF27 AB27 AB26 AB25 AC25 AD25 AJ26 AK26 AC24 AD24 AJ25 AK25 AB23 AC23 AE24 AF24 AA22 AC22 AE23 AF23 BUFIO2 Region RB RB RB RB RB RB RB RB RB RB RB RB RB NA NA NA NA NA NA BR BR BR BR BR BR BR BR BR BR BR BR BR BR No Connect (NC)

IO_L68N_1 IO_L69P_1 IO_L69N_VREF_1 IO_L70P_1 IO_L70N_1 IO_L71P_1 IO_L71N_1 IO_L72P_1 IO_L72N_1 IO_L73P_1 IO_L73N_1 IO_L74P_AWAKE_1 IO_L74N_DOUT_BUSY_1 VFS RFUSE VBATT SUSPEND CMPCS_B_2 DONE_2 IO_L1P_CCLK_2 IO_L1N_M0_CMPMISO_2 IO_L2P_CMPCLK_2 IO_L2N_CMPMOSI_2 IO_L3P_D0_DIN_MISO_MISO1_2 IO_L3N_MOSI_CSI_B_MISO0_2 IO_L4P_2 IO_L4N_VREF_2 IO_L5P_2 IO_L5N_2 IO_L6P_2 IO_L6N_2 IO_L7P_2 IO_L7N_2

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251

Chapter 2: Pinout Tables

Table 2-17:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number AB21 AC21 AD22 AE22 Y21 AA21 AF25 AG25 AB20 AC20 AG24 AH24 AC19 AD19 AE21 AF21 AA18 AB18 AD20 AE20 W20 Y20 AE19 AF19 AA19 AB19 AD18 AE18 W19 Y19 AB17 AD17 AE17 BUFIO2 Region BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR BR LX100T LX100T LX100T LX100T LX100T LX100T No Connect (NC)

IO_L8P_2 IO_L8N_2 IO_L9P_2 IO_L9N_2 IO_L10P_2 IO_L10N_2 IO_L11P_2 IO_L11N_2 IO_L12P_D1_MISO2_2 IO_L12N_D2_MISO3_2 IO_L13P_M1_2 IO_L13N_D10_2 IO_L14P_D11_2 IO_L14N_D12_2 IO_L15P_2 IO_L15N_2 IO_L16P_2 IO_L16N_VREF_2 IO_L17P_2 IO_L17N_2 IO_L18P_2 IO_L18N_2 IO_L19P_2 IO_L19N_2 IO_L20P_2 IO_L20N_2 IO_L21P_2 IO_L21N_2 IO_L22P_2 IO_L22N_2 IO_L23P_2 IO_L23N_2 IO_L28P_2

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX100T and LX150T

Table 2-17:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number AF17 AC16 AD16 AF16 AG16 AH16 AK16 AJ17 AK17 Y17 AA17 AJ15 AK15 AB14 AC14 AD14 AE14 Y14 AA14 AE15 AF15 AC15 AD15 AD12 AE12 Y15 AA15 AE13 AF13 AB13 AC13 AE11 AF11 BUFIO2 Region BR BR BR BR BR BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL LX100T LX100T No Connect (NC)

IO_L28N_2 IO_L29P_GCLK3_2 IO_L29N_GCLK2_2 IO_L30P_GCLK1_D13_2 IO_L30N_GCLK0_USERCCLK_2 IO_L31P_GCLK31_D14_2 IO_L31N_GCLK30_D15_2 IO_L32P_GCLK29_2 IO_L32N_GCLK28_2 IO_L33P_2 IO_L33N_2 IO_L34P_2 IO_L34N_2 IO_L40P_2 IO_L40N_2 IO_L41P_2 IO_L41N_VREF_2 IO_L42P_2 IO_L42N_2 IO_L43P_2 IO_L43N_2 IO_L44P_2 IO_L44N_2 IO_L45P_2 IO_L45N_2 IO_L46P_2 IO_L46N_2 IO_L47P_2 IO_L47N_2 IO_L48P_D7_2 IO_L48N_RDWR_B_VREF_2 IO_L49P_D3_2 IO_L49N_D4_2

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253

Chapter 2: Pinout Tables

Table 2-17:
Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number Y16 AB16 AC11 AD11 W14 Y13 AD10 AE10 AB12 AC12 AG8 AH8 W12 Y12 AE9 AF9 AA11 AB11 AF7 AG7 AB10 AB9 AC9 AD9 AH7 AK7 AD8 AE8 AG6 AH6 AJ6 AK6 AB8 BUFIO2 Region BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL NA LX100T LX100T LX100T LX100T LX100T LX100T LX100T LX100T LX100T LX100T LX100T LX100T No Connect (NC)

IO_L50P_2 IO_L50N_2 IO_L51P_2 IO_L51N_2 IO_L52P_2 IO_L52N_2 IO_L53P_2 IO_L53N_2 IO_L54P_2 IO_L54N_2 IO_L55P_2 IO_L55N_2 IO_L56P_2 IO_L56N_2 IO_L57P_2 IO_L57N_2 IO_L58P_2 IO_L58N_2 IO_L59P_2 IO_L59N_2 IO_L60P_2 IO_L60N_2 IO_L61P_2 IO_L61N_VREF_2 IO_L62P_D5_2 IO_L62N_D6_2 IO_L63P_2 IO_L63N_2 IO_L64P_D8_2 IO_L64N_D9_2 IO_L65P_INIT_B_2 IO_L65N_CSO_B_2 PROGRAM_B_2

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX100T and LX150T

Table 2-17:
Bank 267 267 267 267 267 267 267 267 267 267 267 267 267 267 245 245 245 245 245 245 245 245 245 245 245 245 245 245 245 245 3 3 3

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number AJ23 AK23 AJ18 AJ19 AK19 AG22 AH22 AG20 AH20 AH17 AG18 AH18 AJ21 AK21 AJ11 AK11 AH15 AG14 AH14 AG12 AF14 AH12 AF12 AG10 AH10 AJ14 AJ13 AK13 AJ9 AK9 AA10 AA9 AD7 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA LB LB LB No Connect (NC)

MGTTXP1_267 MGTTXN1_267 MGTAVCCPLL1_267 MGTREFCLK1P_267 MGTREFCLK1N_267 MGTRXP1_267 MGTRXN1_267 MGTRXP0_267 MGTRXN0_267 MGTAVCCPLL0_267 MGTREFCLK0P_267 MGTREFCLK0N_267 MGTTXP0_267 MGTTXN0_267 MGTTXP1_245 MGTTXN1_245 MGTAVCCPLL1_245 MGTREFCLK1P_245 MGTREFCLK1N_245 MGTRXP1_245 MGTAVTTRCAL_245 MGTRXN1_245 MGTRREF_245 MGTRXP0_245 MGTRXN0_245 MGTAVCCPLL0_245 MGTREFCLK0P_245 MGTREFCLK0N_245 MGTTXP0_245 MGTTXN0_245 IO_L1P_3 IO_L1N_VREF_3 IO_L2P_3

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255

Chapter 2: Pinout Tables

Table 2-17:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number AE7 Y9 Y8 AE6 AF6 W11 Y11 AE5 AG5 T7 T6 AA7 AA6 AC6 AD6 AH5 AK5 W10 W9 AB7 AB6 W7 W6 AJ4 AK4 T9 T8 AH3 AK3 Y7 Y6 AJ2 AK2 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB No Connect (NC)

IO_L2N_3 IO_L3P_3 IO_L3N_3 IO_L4P_3 IO_L4N_3 IO_L5P_3 IO_L5N_3 IO_L6P_3 IO_L6N_3 IO_L7P_3 IO_L7N_3 IO_L8P_3 IO_L8N_3 IO_L9P_3 IO_L9N_3 IO_L10P_3 IO_L10N_3 IO_L11P_3 IO_L11N_3 IO_L12P_3 IO_L12N_3 IO_L13P_3 IO_L13N_3 IO_L14P_3 IO_L14N_3 IO_L15P_3 IO_L15N_3 IO_L16P_3 IO_L16N_3 IO_L17P_3 IO_L17N_VREF_3 IO_L18P_3 IO_L18N_3

256

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX100T and LX150T

Table 2-17:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number AE4 AF4 AF3 AG3 V8 V7 AH1 AJ1 V10 V9 AG4 AH4 N10 N9 AF2 AH2 R7 R6 AF1 AG1 U7 U6 AE3 AE1 N8 N7 AC5 AC4 AD4 AD3 AB4 AB3 AD2 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB No Connect (NC)

IO_L19P_3 IO_L19N_3 IO_L20P_3 IO_L20N_3 IO_L21P_3 IO_L21N_3 IO_L22P_3 IO_L22N_3 IO_L23P_3 IO_L23N_3 IO_L24P_3 IO_L24N_3 IO_L25P_3 IO_L25N_3 IO_L26P_3 IO_L26N_3 IO_L27P_3 IO_L27N_3 IO_L28P_3 IO_L28N_3 IO_L29P_3 IO_L29N_3 IO_L30P_3 IO_L30N_3 IO_L31P_3 IO_L31N_VREF_3 IO_L32P_M3DQ14_3 IO_L32N_M3DQ15_3 IO_L33P_M3DQ12_3 IO_L33N_M3DQ13_3 IO_L34P_M3UDQS_3 IO_L34N_M3UDQSN_3 IO_L35P_M3DQ10_3

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257

Chapter 2: Pinout Tables

Table 2-17:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number AD1 AC3 AC1 Y4 Y3 Y2 Y1 AA5 AA4 W3 W1 AA3 AA1 AB2 AB1 W5 W4 V4 V3 V2 V1 U5 U4 U3 U1 T4 T3 T2 T1 R5 R4 R3 R1 BUFIO2 Region LB LB LB LB LB LB LB LB LB LB LB LB LB LB LB LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT No Connect (NC)

IO_L35N_M3DQ11_3 IO_L36P_M3DQ8_3 IO_L36N_M3DQ9_3 IO_L37P_M3DQ0_3 IO_L37N_M3DQ1_3 IO_L38P_M3DQ2_3 IO_L38N_M3DQ3_3 IO_L39P_M3LDQS_3 IO_L39N_M3LDQSN_3 IO_L40P_M3DQ6_3 IO_L40N_M3DQ7_3 IO_L41P_GCLK27_M3DQ4_3 IO_L41N_GCLK26_M3DQ5_3 IO_L42P_GCLK25_TRDY2_M3UDM_3 IO_L42N_GCLK24_M3LDM_3 IO_L43P_GCLK23_M3RASN_3 IO_L43N_GCLK22_IRDY2_M3CASN_3 IO_L44P_GCLK21_M3A5_3 IO_L44N_GCLK20_M3A6_3 IO_L45P_M3A3_3 IO_L45N_M3ODT_3 IO_L46P_M3CLK_3 IO_L46N_M3CLKN_3 IO_L47P_M3A0_3 IO_L47N_M3A1_3 IO_L48P_M3BA0_3 IO_L48N_M3BA1_3 IO_L49P_M3A7_3 IO_L49N_M3A2_3 IO_L50P_M3WE_3 IO_L50N_M3BA2_3 IO_L51P_M3A10_3 IO_L51N_M3A4_3

258

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX100T and LX150T

Table 2-17:
Bank 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number P4 P3 N5 N4 P2 P1 N3 N1 P7 P6 M7 M6 L7 L6 M2 M1 L3 L1 K2 K1 L5 L4 M4 M3 H4 H3 J3 J1 J5 J4 H2 H1 G3 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT No Connect (NC)

IO_L52P_M3A8_3 IO_L52N_M3A9_3 IO_L53P_M3CKE_3 IO_L53N_M3A12_3 IO_L54P_M3RESET_3 IO_L54N_M3A11_3 IO_L55P_M3A13_3 IO_L55N_M3A14_3 IO_L56P_3 IO_L56N_3 IO_L57P_3 IO_L57N_VREF_3 IO_L58P_4 IO_L58N_VREF_4 IO_L59P_M4DQ14_4 IO_L59N_M4DQ15_4 IO_L60P_M4DQ12_4 IO_L60N_M4DQ13_4 IO_L61P_M4UDQS_4 IO_L61N_M4UDQSN_4 IO_L62P_M4DQ10_4 IO_L62N_M4DQ11_4 IO_L63P_M4DQ8_4 IO_L63N_M4DQ9_4 IO_L64P_M4DQ0_4 IO_L64N_M4DQ1_4 IO_L65P_M4DQ2_4 IO_L65N_M4DQ3_4 IO_L66P_M4LDQS_4 IO_L66N_M4LDQSN_4 IO_L67P_M4DQ6_4 IO_L67N_M4DQ7_4 IO_L68P_M4DQ4_4

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259

Chapter 2: Pinout Tables

Table 2-17:
Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 NA NA

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number G1 K4 K3 C1 B1 F2 F1 E5 E4 E3 E1 D4 D3 D2 D1 B3 A3 F4 F3 D5 C5 B2 A2 C4 A4 G5 G4 B5 A5 J6 H6 A1 A12 BUFIO2 Region LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT LT NA NA No Connect (NC)

IO_L68N_M4DQ5_4 IO_L69P_M4UDM_4 IO_L69N_M4LDM_4 IO_L70P_M4RASN_4 IO_L70N_M4CASN_4 IO_L71P_M4A5_4 IO_L71N_M4A6_4 IO_L72P_M4A3_4 IO_L72N_M4ODT_4 IO_L73P_M4CLK_4 IO_L73N_M4CLKN_4 IO_L74P_M4A0_4 IO_L74N_M4A1_4 IO_L75P_M4BA0_4 IO_L75N_M4BA1_4 IO_L76P_M4A7_4 IO_L76N_M4A2_4 IO_L77P_M4WE_4 IO_L77N_M4BA2_4 IO_L78P_M4A10_4 IO_L78N_M4A4_4 IO_L79P_M4A8_4 IO_L79N_M4A9_4 IO_L80P_M4CKE_4 IO_L80N_M4A12_4 IO_L81P_M4RESET_4 IO_L81N_M4A11_4 IO_L82P_M4A13_4 IO_L82N_M4A14_4 IO_L83P_4 IO_L83N_VREF_4 GND GND

260

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX100T and LX150T

Table 2-17:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number A14 A18 A20 A24 A30 A8 AA13 AA2 AA26 AB15 AB22 AB29 AB5 AC17 AC8 AE2 AF10 AF18 AF20 AF22 AF26 AF29 AF5 AG13 AG15 AG17 AG19 AH11 AH21 AH23 AH28 AH9 AJ10 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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261

Chapter 2: Pinout Tables

Table 2-17:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number AJ12 AJ20 AJ22 AJ24 AJ5 AJ8 AK1 AK12 AK14 AK18 AK20 AK24 AK30 AK8 B10 B12 B20 B22 B24 B26 B8 C11 C21 C23 C28 C3 C9 D13 D15 D17 D19 E10 E18 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

262

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX100T and LX150T

Table 2-17:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number E2 E20 E22 F29 F5 F7 G24 J11 J16 J2 J21 J26 K16 K18 K22 K23 K29 K5 K7 K8 K9 L16 L23 L8 M12 M16 M22 M9 N13 N14 N17 N18 N2 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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263

Chapter 2: Pinout Tables

Table 2-17:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number N21 N22 N26 P10 P13 P14 P17 P18 P20 P29 P5 P8 R11 R12 R15 R16 R19 R20 R9 T10 T11 T12 T15 T16 T19 T20 T22 T23 U13 U14 U17 U18 U2 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX100T and LX150T

Table 2-17:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number U21 U22 U26 U9 V13 V14 V17 V18 V22 V29 V5 W16 W18 W8 AB24 AC7 AG23 AG9 D23 D9 G6 H24 J15 J23 J7 J9 L22 M11 M14 M25 N6 R10 T21 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX

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Table 2-17:
Bank NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number U10 V21 V25 V6 W13 W15 W17 Y18 N11 N12 N15 N16 N19 N20 P11 P12 P15 P16 P19 R13 R14 R17 R18 T13 T14 T17 T18 U11 U12 U15 U16 U19 U20 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX100T and LX150T

Table 2-17:
Bank NA NA NA NA NA NA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number V11 V12 V15 V16 V19 V20 B16 C25 C7 F16 G13 G23 G8 H10 H20 J17 K13 L15 L9 M17 M21 AA23 AC26 AD29 AH29 AJ27 N23 P21 R23 R26 T29 U23 W23 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1

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Chapter 2: Pinout Tables

Table 2-17:
Bank 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number W26 Y29 AA12 AA16 AA20 AC10 AC18 AD13 AD21 AD23 AE16 AF8 AH25 AJ16 AJ7 AA8 AC2 AD5 AG2 AJ3 M8 P9 R2 R8 T5 U8 W2 Y10 Y5 B4 C2 G2 H5 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCO_1 VCCO_1 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_2 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 VCCO_4 VCCO_4 VCCO_4 VCCO_4

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX100T and LX150T

Table 2-17:
Bank 4 4 4 5 5 5 5 5 5 5 5 101 123 245 267 101 123 245 267 101 123 245 267

FG(G)900 PackageLX100T and LX150T (Contd)


Pin Description Pin Number K6 L2 M5 B28 D29 G26 H29 J25 K24 L26 M29 C13 C19 AH13 AH19 D11 D21 AG11 AG21 A10 A22 AK10 AK22 BUFIO2 Region NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA No Connect (NC)

VCCO_4 VCCO_4 VCCO_4 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 MGTAVCC_101 MGTAVCC_123 MGTAVCC_245 MGTAVCC_267 MGTAVTTRX_101 MGTAVTTRX_123 MGTAVTTRX_245 MGTAVTTRX_267 MGTAVTTTX_101 MGTAVTTTX_123 MGTAVTTTX_245 MGTAVTTTX_267

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Chapter 3

Pinout and I/O Bank Diagrams


Summary
This chapter provides pinout diagrams for each Spartan-6 FPGA package/device combination. The multi-function I/O pins in these diagrams are represented by symbols based on functionality, using the following precedence: VREF GCLK D0D15 A0A25

For example, a pin description such as IO_L37N_GCLK12_0 is represented with an N_GCLK symbol, a pin description such as IO_L1N_VREF_0 is represented with a VREF symbol, and a pin description such as IO_L13N_D10_2 is represented with a D0D15 symbol. Table 3-1:
Device/ Package LX4 LX9 LX16 LX25 LX25T LX45 LX45T LX75 LX75T LX100 LX100T LX150 LX150T

Cross-Reference for Pinout and I/O Bank Diagrams


TQG144 Page 272 Page 272 CPG196 Page 274 Page 274 Page 274 CSG225 Page 275 Page 276 Page 276 Page 277 Page 277 Page 277 Page 278 Page 279 Page 280 Page 281 Page 282 Page 283 Page 284 Page 286 Page 288 Page 298 Page 290 Page 292 Page 294 Page 298 Page 296 Page 298 Page 300 Page 308 Page 302 Page 306 Page 304 Page 308 Page 304 Page 308 Page 312 Page 314 Page 316 Page 318 Page 320 Page 322 Page 324 Page 326 Page 328 Page 310 FT(G)256 CSG324 FG(G)484 CS(G)484 FG(G)676 FG(G)900

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Chapter 3: Pinout and I/O Bank Diagrams

TQG144 PackageLX4 and LX9


X-Ref Target - Figure 3-1

P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36
P b Y U 1 B N 0 C D g

P144 P143 P142 P141 P140 P139 P138 P137 P136 P135 P134 P133 P132 P131 P130 P129 P128 P127 P126 P125 P124 P123 P122 P121 P120 P119 P118 P117 P116 P115 P114 P113 P112 P111 P110 P109
H I K M O W A Z

P108 P107 P106 P105 P104 P103 P102 P101 P100 P99 P98 P97 P96 P95 P94 P93 P92 P91 P90 P89 P88 P87 P86 P85 P84 P83 P82 P81 P80 P79 P78 P77 P76 P75 P74 P73

272

P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72
User I/O Pins IO_LXXY_# Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25
a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND VCCAUX VCCINT VCCO n NC

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2

UG385_c3_01_111909

Figure 3-1:

TQG144 PackageLX4 and LX9 Pinout Diagram

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

TQG144 PackageLX4 and LX9

X-Ref Target - Figure 3-2

P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36

P144 P143 P142 P141 P140 P139 P138 P137 P136 P135 P134 P133 P132 P131 P130 P129 P128 P127 P126 P125 P124 P123 P122 P121 P120 P119 P118 P117 P116 P115 P114 P113 P112 P111 P110 P109
0 3 3 1 3 3 3 3 3 3 3 3 3 3 3 3 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1

P108 P107 P106 P105 P104 P103 P102 P101 P100 P99 P98 P97 P96 P95 P94 P93 P92 P91 P90 P89 P88 P87 P86 P85 P84 P83 P82 P81 P80 P79 P78 P77 P76 P75 P74 P73

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72
UG385_c3_01_110209

Figure 3-2:

TQG144 PackageLX4 and LX9 I/O Bank Diagram

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Chapter 3: Pinout and I/O Bank Diagrams

CPG196 PackageLX4, LX9, and LX16


X-Ref Target - Figure 3-3

1 A B C D E F G H J K L M N P

2
H

10

11

12

13
I

14 A B C D E F G H J K L M N P

K M O

Z g W A P Y b U 1 N B C 0 D

1
User I/O Pins IO_LXXY_#

10

11

12

13

14

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND VCCAUX VCCINT VCCO n NC

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2

UG385_c3_03_111909

Figure 3-3:
X-Ref Target - Figure 3-4

CPG196 PackageLX4, LX9, and LX16 Pinout Diagram


2
0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 1 1 1 1 3 3 1 1 3 3 0

1 A B C D E F G H J K L M N P

3
0 0

4
0 0

5
0 0

6
0 0

7
0 0

8
0 0 0 0

9
0 0

10
0 0

11
0 0 0 0

12
0 0 1

13

14 A B C D E F G H J K L M N P

1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1

10

11

12

13

14

UG385_c3_04_110209

Figure 3-4:

CPG196 PackageLX4, LX9, and LX16 I/O Bank Diagram

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG225 PackageLX4

CSG225 PackageLX4
X-Ref Target - Figure 3-5

1 A B C D E F G H J K L M N P R 1
User I/O Pins IO_LXXY_#

2
H

10

11

12

13

14
K

15 A B C D E F G H J K L M N P R

n n n n n n n n n n n n n Y P b U n n 1 N B 0 C W A D g Z n n n n n n I n n n n n n n O M

10

11

12

13

14

15
Other Pins GND VCCAUX VCCINT VCCO n NC

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2

UG385_c3_05_111909

Figure 3-5:
X-Ref Target - Figure 3-6

CSG225 PackageLX4 Pinout Diagram


2
0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 3 3 3 3 3 3 3 3 3 2 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3

1 A B C D E F G H J K L M N P R

3
0 0

4
0 0 3

5
0 0 0 0

6
0 0

7
0 0

8
0 0 0

9
0 0 0 0

10
0 0 0 0

11
0 0 0 0

12
0 0

13
0 0 1

14

15
1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1

1 1

A B C D E F G H J K L M N P R

10

11

12

13

14

15

UG385_c3_06_110209

Figure 3-6:

CSG225 PackageLX4 I/O Bank Diagram

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CSG225 PackageLX9 and LX16


X-Ref Target - Figure 3-7

1 A B C D E F G H J K L M N P R 1

2
H

10

11

12

13

14
K

15 A B C D E F G H J K L M N P R

O I M

g 1 Y P b U N B 0 C

Z a a D a a W A

10

11

12

13

14

15

User I/O Pins IO_LXXY_#

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND VCCAUX VCCINT VCCO n NC

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2

UG385_c3_07_111909

Figure 3-7:
X-Ref Target - Figure 3-8

CSG225 PackageLX9 and LX16 Pinout Diagram


2
0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 3 3 3

1 A B C D E F G H J K L M N P R

3
0 0

4
0 0 3 3 3

5
0 0 0 0 3 3 3 3 3 3 2 2 2 2 2

6
0 0 0 0

7
0 0 0 0 0

8
0 0 0 0 0

9
0 0 0 0

10
0 0 0 0 1

11
0 0 0 0 1 1 1 1 1 2 2 2 2

12
0 0

13
0 0 1

14
1 1 1

15
1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1

1 1 1 1 1 1 1 1 2 1 2 1 1

3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1 2 2 2

2 2

A B C D E F G H J K L M N P R

10

11

12

13

14

15

UG385_c3_08_110209

Figure 3-8: CSG225 PackageLX9 and LX16 I/O Bank Diagram

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FT(G)256 PackageLX9, LX16, and LX25

FT(G)256 PackageLX9, LX16, and LX25


X-Ref Target - Figure 3-9

1 A B C D E F G H J K L M N P R T 1
User I/O Pins IO_LXXY_#

10

11

12

13

14

15
M

16 A B C D E F G H J K L M N P R T

K O

g 1 N Y P b U B C 0 D

a W A Z a a

a a

10

11

12

13

14

15

16
Other Pins GND VCCAUX VCCINT VCCO n NC

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2

UG385_c3_09_111909

Figure 3-9:
X-Ref Target - Figure 3-10

FT(G)256 PackageLX9, LX16, and LX25 Pinout Diagram


2
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 3 3 3 3 3 3 3

1 A B C D E F G H J K L M N P R T

3
3 3 3 3 3 3 3 3 3 3 3 3 3

4
0 0 3 3 3 3

5
0 0 0 0 3 3 3

6
0 0 0 0 0 3 3 3

7
0 0 0 0

8
0 0 0 0 0

9
0 0 0

10
0 0 0 0

11
0 0 0 0 1 1 1 1

12
0 0

13
0 0

14
0 0 1

15
1 1 1

16
1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 1 1 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1

1 1 1 1 1 1 1 1

1 1 1 1 1

3 3 3 3 2 3 3 2 2 2 2

3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

2 2 2 2 2

1 1

1 1

A B C D E F G H J K L M N P R T

10

11

12

13

14

15

16

UG385_c3_10_110209

Figure 3-10:

FT(G)256 PackageLX9, LX16, and LX25 I/O Bank Diagram

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CSG324 PackageLX9
X-Ref Target - Figure 3-11

1 A B C D E F G H J K L M N P R T U V 1

10

11

12

13
n

14

15

16

17
K

18
M

n H n n n n n n n n n n n n n

n I O

a n n n n U Y P b n n n n n n n n n n 1 g N B W A C 0 n n D Z a a

a a

A B C D E F G H J K L M N P R T U V

10

11

12

13

14

15

16

17

18

User I/O Pins IO_LXXY_#

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND VCCAUX VCCINT VCCO n NC

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2

UG385_c3_11_111909

Figure 3-11:
X-Ref Target - Figure 3-12

CSG324 PackageLX9 Pinout Diagram


2
0 0

1 A B C D E F G H J K L M N P R T U V

3
0 0 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2

4
0 0 0 0 3 3 3 3 3 3 3

5
0 0

6
0 0 0 0

7
0 0

8
0 0 0 0

9
0 0 0 0 0 0

10
0 0

11
0 0 0 0

12
0 0

13

14
0 0 0 0

15
0 0

16
0 0

17

18 A B C D E F G H J K L M N P R T U V

3 3 3 3 3 3 3 3 3 3 3 3 3 3

3 3 3 3 3 3 3 3 3 3

1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1

2 2

2 2

10

11

12

13

14

15

16

17

18

UG385_c3_12_110209

Figure 3-12:

CSG324 PackageLX9 I/O Bank Diagram

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG324 PackageLX16

CSG324 PackageLX16
X-Ref Target - Figure 3-13

1 A B C D E F G H J K L M N P R T U V 1
User I/O Pins IO_LXXY_#

10

11

12

13

14

15

16

17
K

18
M

a a 1 g N U Y P b D B W A C 0 Z a

a a

A B C D E F G H J K L M N P R T U V

10

11

12

13

14

15

16

17

18
Other Pins GND VCCAUX VCCINT VCCO n NC

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2

UG385_c3_13_111909

Figure 3-13:
X-Ref Target - Figure 3-14

CSG324 PackageLX16 Pinout Diagram


2
0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 3 3 2 2 2 2 2 2 3 3 3 3 3 2 2 2 2 2 2 2 2 2 3 3

1 A B C D E F G H J K L M N P R T U V

3
0 0

4
0 0 0 0 3 3

5
0 0

6
0 0 0 0 0

7
0 0 0 0 3 3

8
0 0 0 0 0 0 0

9
0 0 0 0 0 0

10
0 0

11
0 0 0 0 0

12
0 0 0 0 0 0 1 1

13
0 0 0 0 1 1 1 1 1 1

14
0 0 0 0

15
0 0

16
0 0

17

18 A B C D E F G H J K L M N P R T U V

1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1

3 3 3 3 3 3

0 0

1 1 1 1 1 1 1

1 1 1 1 1 1 2

1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1

3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1 2 2

2 2 2 2 2 2 2 2

2 2 2 2 2

10

11

12

13

14

15

16

17

18

UG385_c3_14_110209

Figure 3-14:

CSG324 PackageLX16 I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

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Chapter 3: Pinout and I/O Bank Diagrams

CSG324 PackageLX25
X-Ref Target - Figure 3-15

1 A B C D E F G H J K L M N P R T U V 1

10

11

12

13

14

15

16

17
K

18
M

H n n n n n n

a a 1 g N U Y P b D B W A C 0 Z a

a a

A B C D E F G H J K L M N P R T U V

10

11

12

13

14

15

16

17

18

User I/O Pins IO_LXXY_#

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND VCCAUX VCCINT VCCO n NC

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2

UG385_c3_15_111909

Figure 3-15:
X-Ref Target - Figure 3-16

CSG324 PackageLX25 Pinout Diagram


2
0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 3 3 2 2 2 2 2 2 3 3 3 3 3 2 2 2 2 2 2 2 2 2 3 3

1 A B C D E F G H J K L M N P R T U V

3
0 0

4
0 0 0 0 3 3

5
0 0

6
0 0 0 0

7
0 0

8
0 0 0 0

9
0 0 0 0 0 0

10
0 0

11
0 0 0 0 0

12
0 0 0 0 0 0 1 1

13
0 0 0 0 1 1 1 1 1 1

14
0 0 0 0

15
0 0

16
0 0

17

18 A B C D E F G H J K L M N P R T U V

1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1

3 3 3 3 3 3 3 2 2 2 2 2 2 2 3 3

0 0

1 1 1 1 1 1 1

1 1 1 1 1 1 2

1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1

1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

2 2 2 2 2 2

2 2 2 2 2

10

11

12

13

14

15

16

17

18

UG385_c3_16_110209

Figure 3-16:

CSG324 PackageLX25 I/O Bank Diagram

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG324 PackageLX25T

CSG324 PackageLX25T
X-Ref Target - Figure 3-17

1 A B C D E F G H J K L M N P R T U V 1
User I/O Pins IO_LXXY_# Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25
a FCS / FWE / FOE / HDC / LDC

2
H

5
V

7
E

10
n n

11
n n n n

12
n n

13
n n

14
n n

15

16

17
K

18
M

E V G n
V E

n I

n n

a a 1 g N U Y P b D B W A C 0 Z a

a a

A B C D E F G H J K L M N P R T U V

10

11

12

13

14

15

16

17

18

Transceiver Pins

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND VCCAUX VCCINT VCCO n NC

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT E MGTAVCC E V V MGTAVCCPLL MGTRXP MGTRXN MGTTXN MGTTXP

V MGTAVTTRX MGTAVTTRCAL MGTAVTTTX MGTREFCLK (P) MGTREFCLK (N) G MGTRREF

O TDO M TMS D DONE_2


Z SUSPEND g

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2

UG385_c3_17_111909

Figure 3-17:
X-Ref Target - Figure 3-18

CSG324 PackageLX25T Pinout Diagram


2
0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 3 3 2 2 2 2 2 2 3 3 3 3 3 2 2 2 2 2 2 2 2 2 3 3 3 3 3

1 A B C D E F G H J K L M N P R T U V

6
101 101

8
101 101

10

11

12

13

14

15
0

16
0 0

17

18 A B C D E F G H J K L M N P R T U V

0 101 0 101
101 101

101 101

101 101

0 0 0 0 0 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 3 3 3 3 3 3 3 3 3 0

0 0 0 0

2 2 2 2 2 2 2 2 2 2

2 2 2 2 2 2

2 2 2 2 2 2 2

10

11

12

13

14

15

16

17

18

UG385_c3_18_110209

Figure 3-18:

CSG324 PackageLX25T I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

281

Chapter 3: Pinout and I/O Bank Diagrams

CSG324 PackageLX45
X-Ref Target - Figure 3-19

1 A B C D E F G H J K L M N P R T U V 1
User I/O Pins IO_LXXY_#

10

11

12

13

14

15

16

17
K

18 A B C D E F G H J K L M N P R T U V

M n H n n n n n n n n n n n n n I O

a a 1 g N U Y P b D B W A C 0 Z a

a a

10

11

12

13

14

15

16

17

18
Other Pins GND VCCAUX VCCINT VCCO n NC

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2

UG385_c3_19_111909

Figure 3-19:
X-Ref Target - Figure 3-20

CSG324 PackageLX45 Pinout Diagram


2
0 0

1 A B C D E F G H J K L M N P R T U V

3
0 0 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2

4
0 0 0 0 3 3 3 3 3 3 3

5
0 0

6
0 0 0 0

7
0 0

8
0 0 0 0

9
0 0 0 0 0 0

10
0 0

11
0 0 0 0

12
0 0

13
0 0 0

14
0 0 0 0

15
0 0

16
0 0

17

18 A B C D E F G H J K L M N P R T U V

3 3 3 3 3 3 3 3 3 3 3 3 3 3

3 3 3 3 3 3 3 3 3 3

1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1

3 3 3 3 3 2 2

3 3 3 3 3 3 2 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3

0 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1

1 1 1 1 1 1 1

1 1 1 1 1 1 2

1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1

2 2

2 2 2

2 2

2 2 2

2 2

2 2 2 2 2

10

11

12

13

14

15

16

17

18

UG385_c3_20_110209

Figure 3-20:

CSG324 PackageLX45 I/O Bank Diagram

282

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG324 PackageLX45T

CSG324 PackageLX45T
X-Ref Target - Figure 3-21

1 A B C D E F G H J K L M N P R T U V 1

2
H

5
V

7
E

10

11
E

12

13
V

14

15

16

17
K

18
M

E V G E
V

V
E

O I

a a 1 g N U Y P b D B W A C 0 Z a

a a

A B C D E F G H J K L M N P R T U V

10

11

12

13

14

15

16

17

18

User I/O Pins IO_LXXY_# VREF

Multi-Function Pins C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

Transceiver Pins

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND VCCAUX VCCINT VCCO n NC

P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

E MGTAVCC E V V MGTAVCCPLL

MGTRXP MGTRXN MGTTXN MGTTXP

V MGTAVTTRX MGTAVTTRCAL MGTAVTTTX MGTREFCLK (P) MGTREFCLK (N) G MGTRREF

O TDO M TMS D DONE_2


Z SUSPEND g

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2

UG385_c3_21_111909

Figure 3-21:
X-Ref Target - Figure 3-22

CSG324 PackageLX45T Pinout Diagram


2
0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 3 3 2 2 2 2 2 2 3 3 3 3 3 2 2 2 2 2 2 2 2 2 3 3 3 3 3

1 A B C D E F G H J K L M N P R T U V

6
101 101

8
101 101

10

11

12

13

14

15

16
0 0

17

18 A B C D E F G H J K L M N P R T U V

0 101 0 101
101 101

123 123 101 101 123 123 123 123

123 123 123 123

123 0 123

101 101

0 0 0 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 3 3 3 3 3 3 3 3 3 0

0 0 0

0 0 0 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2

1 1

2 2 2 2 2 2 2 2 2 2

2 2 2 2 2 2

2 2 2 2 2 2 2

10

11

12

13

14

15

16

17

18

UG385_c3_22_110209

Figure 3-22:

CSG324 PackageLX45T I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

283

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)484 PackageLX25
X-Ref Target - Figure 3-23

1 A B C D E F G H J K L M N P R T U V W Y AA AB

3
H

10

11

12

13

14

15

16

17

18

19
O

20

21

22 A B C D E F G H J K L M N P R T U V W Y AA AB

n n n n n n n n n n n n n n n n n n n n n b Y n n n n n n n n n n n n n n n n Z n n n 1 n n n n n n n n n n n n n n n n n n n K n n n n n n n n

M I

n a n n n W A n n n n g

a a

a a

D 0

P U

N B

1
User I/O Pins IO_LXXY_#

10

11

12

13

14

15

16

17

18

19

20

21

22
Other Pins GND VCCAUX VCCINT VCCO n NC

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2

UG385_c3_23_111909

Figure 3-23:

FG(G)484 PackageLX25 Pinout Diagram

284

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25

X-Ref Target - Figure 3-24

1 A B C D E F G H J K L M N P R T U V W Y AA AB
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
3 3 3

3
0 3 3 3

4
0

5
0 0

6
0 0 0 0

7
0 0 0

8
0 0 0 0

9
0 0 0

10
0 0 0 0

11
0 0 0

12
0 0 0 0 0 0

13
0 0 0 0 0 0

14
0 0 0 0 0 0 0

15
0 0 0

16
0 0 0 0

17
0 0 0

18
0 0

19

20
1 1

21
1 1 1 1 1 1 1 1 1 1

22
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

3 3 3 3 3

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

3 3 3 3 3 3 3 3 3 3

1 1 1

2 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

2 2 2

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1

3 3 3 2 2

3 3 3 3 2 2

2 2 2 2

2 2 2

1 2 2 2 2 2

A B C D E F G H J K L M N P R T U V W Y AA AB

10

11

12

13

14

15

16

17

18

19

20

21

22

UG385_c3_24_110209

Figure 3-24: FG(G)484 PackageLX25 I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

285

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)484 PackageLX25T
X-Ref Target - Figure 3-25

1 A B C D E F G H J K L M N P R T U V W Y AA AB 1

7
V

9
E

10

11

12
n n

13
n n n n

14
n n

15
n n

16
n n

17

18

19

20

21
K n

22
n n

H V G

E
E

n I O

n n

n n n n n n n n n n

n n n n

n n n n n Y b P n n n n n

n n n n

n n n n n n U n n n n n n n g W A 1 C N B 0 D Z n n n a a a a a

A B C D E F G H J K L M N P R T U V W Y AA AB

10

11

12

13

14

15

16

17

18

19

20

21

22

User I/O Pins IO_LXXY_# VREF

Multi-Function Pins C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

Transceiver Pins

Dedicated Pins MGTRXP MGTRXN MGTTXN MGTTXP P PROGRAM_B_2 K TCK I TDI

Other Pins GND VCCAUX VCCINT VCCO n NC

P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

E MGTAVCC

E V

MGTAVCCPLL

V MGTAVTTRX MGTAVTTRCAL MGTAVTTTX MGTREFCLK (P) MGTREFCLK (N) G MGTRREF

O TDO M TMS D DONE_2


Z SUSPEND g

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2

UG385_c3_25_111909

Figure 3-25:

FG(G)484 PackageLX25T Pinout Diagram

286

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX25T

X-Ref Target - Figure 3-26

1 A B C D E F G H J K L M N P R T U V W Y AA AB
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
0 0 3 3 3 3 3 3 3

3
0 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3

4
0 0 0 3

6
101

8
101 101

10
101 101

11

12

13

14

15

16

17
0

18
0 0 0 0 1 1

19
0 0 0

20
0 0 1 1

21

22 A B C D E F G H J K L M N P R T U V W Y AA AB

0 101 0 0 0 0 0 3
101 101

101 101

101 101

0 0 0 0 0 0 0 1 1 1 1 0 0 0

1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0

0 0

0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2

3 3 3 3 3 3 3 3 3

3 3 3 3 3 3

1 1

1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

3 3 2 2 2 2 2 2 2 2 2 2 2 2

1 1 2 2 2 2 2 2

3 3 3 3 3 2 3 2 2 2 2 2 2 2 2 2

10

11

12

13

14

15

16

17

18

19

20

21

22

UG385_c3_26_110209

Figure 3-26:

FG(G)484 PackageLX25T I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

287

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)484 PackageLX45
X-Ref Target - Figure 3-27

1 A B C D E F G H J K L M N P R T U V W Y AA AB

3
H

10

11

12

13

14

15

16

17

18

19
O

20

21

22 A B C D E F G H J K L M N P R T U V W Y AA AB

M n n n n n n n n n n n n n n n n n n n n n n K I

a Z n b Y 1 n n W A a a

a a

g P U N B

D 0

1
User I/O Pins IO_LXXY_#

10

11

12

13

14

15

16

17

18

19

20

21

22
Other Pins GND VCCAUX VCCINT VCCO n NC

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2

UG385_c3_27_111909

Figure 3-27:

FG(G)484 PackageLX45 Pinout Diagram

288

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX45

X-Ref Target - Figure 3-28

1 A B C D E F G H J K L M N P R T U V W Y AA AB
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
3 3 3 3 3 3 3 3 3 3 3 2 2

3
0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2

4
0 3 3 3 3 3 3 3 3 3 3 3 3 3

5
0 0 3 3 3

6
0 0 0 0 3

7
0 0 0 3

8
0 0 0 0

9
0 0 0

10
0 0 0 0

11
0 0 0

12
0 0 0

13
0 0

14
0 0 0 0

15
0 0 0

16
0 0 0 0 1 1

17
0 0 0 1 1 1 1 1 1 1 1

18
0 0

19

20
1 1

21
1 1 1 1 1 1 1 1 1 1 2

22
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 2

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2

3 3 3 3 3 2 2 3 3 3 3 3 3 3 2 2

3 3 3 3 3 3 3 2 2 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 1 3

1 1 1 1 1 2 2 2

2 2 2 2

2 2 2 2 2 2

2 2 2 2

2 2 2

2 2

A B C D E F G H J K L M N P R T U V W Y AA AB

10

11

12

13

14

15

16

17

18

19

20

21

22

UG385_c3_28_110209

Figure 3-28: FG(G)484 PackageLX45 I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

289

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)484 PackageLX75
X-Ref Target - Figure 3-29

1 A B C D E F G H J K L M N P R T U V W Y AA AB

3
H

10

11

12

13

14

15

16

17

18

19
O

20

21

22 A B C D E F G H J K L M N P R T U V W Y AA AB

M n n n n n n n n n n n n K I

a Z e n b n n n P n U n Y n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n 1 f n n n n n n n n n g N B C n W A a a

a a

D 0

1
User I/O Pins IO_LXXY_#

10

11

12

13

14

15

16

17

18

19

20

21

22
Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g e

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_29_111909

Figure 3-29:

FG(G)484 PackageLX75 Pinout Diagram

290

www.xilinx.com

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX75

X-Ref Target - Figure 3-30

1 A B C D E F G H J K L M N P R T U V W Y AA AB
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
3 3 3 3 3 3 3 3 3 3 3 2 2

3
0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2

4
0 3 3 3 3 3 3 3 3 3 3 3 3 3

5
0 0 3 3 3

6
0 0 0 0 3

7
0 0 0 3

8
0 0 0 0

9
0 0 0

10
0 0 0 0

11
0 0 0

12
0 0 0 0 0

13
0 0 0 0 0

14
0 0 0 0 0 0 0

15
0 0 0

16
0 0 0 0

17
0 0 0

18
0 0

19

20
1 1

21
1 1 1 1 1 1 1 1 1 1 2

22
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1

1 1 1 1 1 1 1 1 2

3 3 3 3 3 2 3 3 3 3 3 3 3 2

3 3 3 3 3 3 3 3 3

1 3 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

2 2 2 2 2 2 2 2 2 2

2 2 2 2

2 2 2 2

2 2

2 2

A B C D E F G H J K L M N P R T U V W Y AA AB

10

11

12

13

14

15

16

17

18

19

20

21

22

UG385_c3_30_110209

Figure 3-30: FG(G)484 PackageLX75 I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

291

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)484 PackageLX75T
X-Ref Target - Figure 3-31

1 A B C D E F G H J K L M N P R T U V W Y AA AB 1
User I/O Pins IO_LXXY_# VREF P_GCLK N_GCLK D0 - D15 A0 - A25

7
V

9
E

10

11

12

13
E

14

15
V

16

17

18

19

20

21
K

22 A B C D E F G H J K L M N P R T U V W Y AA AB

H V G

E V I O
E

e n n n n n Y b P n n U n n n n n n n n n n n n n n n n n 1 C N B n n n n f g W A a

a a

a a

0 D

10

11

12

13

14

15

16

17

18

19

20

21

22

Multi-Function Pins C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

Transceiver Pins

Dedicated Pins MGTRXP MGTRXN MGTTXN MGTTXP P PROGRAM_B_2 K TCK I TDI

Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

E MGTAVCC E V V MGTAVCCPLL

V MGTAVTTRX MGTAVTTRCAL MGTAVTTTX MGTREFCLK (P) MGTREFCLK (N) G MGTRREF

O TDO M TMS D DONE_2


Z SUSPEND g e

a FCS / FWE / FOE / HDC / LDC

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_31_111909

Figure 3-31:

FG(G)484 PackageLX75T Pinout Diagram

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FG(G)484 PackageLX75T

X-Ref Target - Figure 3-32

1 A B C D E F G H J K L M N P R T U V W Y AA AB
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
0 0 3 3 3 3 3 3 3 3 3 3

3
0 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2

4
0 0 0 3 3 3 3 3 3 3 3 3 3 3 3

6
101

8
101 101

10
101 101

11

12
123 123

13

14
123 123

15

16
123

17

18
0 0 0 0 1 1 1 1 1 1

19
0 0 0

20
0 0 1

21
1 1

22
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 101 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 3 3 3 3 2 3 3 0 0 3
101 101

123 0

101 101

101 101 123

123 123

123 123

0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 0

1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 2 1 1 1 1 1 1 1

0 0 3 3

0 0

0 0 0 0

123

0 0 0 0

0 0

1 3 1 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1

3 2 2 2 2 2 2 2

A B C D E F G H J K L M N P R T U V W Y AA AB

10

11

12

13

14

15

16

17

18

19

20

21

22

UG385_c3_32_110209

Figure 3-32:

FG(G)484 PackageLX75T I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

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Chapter 3: Pinout and I/O Bank Diagrams

FG(G)484 PackageLX100
X-Ref Target - Figure 3-33

1 A B C D E F G H J K L M N P R T U V W Y AA AB

3
H

10

11

12

13

14

15

16

17

18

19
O

20

21

22 A B C D E F G H J K L M N P R T U V W Y AA AB

M I K

a Z e b Y n n n n P n U n n n n n 1 n n g N B C f W A a a

a a

D 0

1
User I/O Pins IO_LXXY_#

10

11

12

13

14

15

16

17

18

19

20

21

22
Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g e

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_33_111909

Figure 3-33:

FG(G)484 PackageLX100 Pinout Diagram

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FG(G)484 PackageLX100

X-Ref Target - Figure 3-34

1 A B C D E F G H J K L M N P R T U V W Y AA AB
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
3 3 3 3 3 3 3 3 3 3 3 2 2

3
0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2

4
0 3 3 3 3 3 3 3 3 3 3 3 3 3

5
0 0 3 3 3

6
0 0 0 0 3

7
0 0 0 3

8
0 0 0 0 0 0 0 3

9
0 0 0 0 0

10
0 0 0 0 0 0

11
0 0 0

12
0 0 0 0 0 0

13
0 0 0 0 0 0

14
0 0 0 0 0 0 0

15
0 0 0

16
0 0 0 0

17
0 0 0

18
0 0

19

20
1 1

21
1 1 1 1 1 1 1 1 1 1 2

22
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 2

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2

1 1 1 1 1

1 1 1 1 1 1 1 1

3 3 3 3 3 2 2 3 3 3 3 3 3 3 2 2

3 3 3 3 3 3 2 2

0 0 0 0

3 1 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1 1 2 2 2

2 2 2 2 2

2 2 2 2 2

2 2 2 2

2 2 2

A B C D E F G H J K L M N P R T U V W Y AA AB

10

11

12

13

14

15

16

17

18

19

20

21

22

UG385_c3_34_110209

Figure 3-34: FG(G)484 PackageLX100 I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

295

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)484 PackageLX150
X-Ref Target - Figure 3-35

1 A B C D E F G H J K L M N P R T U V W Y AA AB

3
H

10

11

12

13

14

15

16

17

18

19
O

20

21

22 A B C D E F G H J K L M N P R T U V W Y AA AB

M I K

a Z e b Y 1 f W A a a

a a

g P U N B

D 0

1
User I/O Pins IO_LXXY_#

10

11

12

13

14

15

16

17

18

19

20

21

22
Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g e

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_35_111909

Figure 3-35:

FG(G)484 PackageLX150 Pinout Diagram

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX150

X-Ref Target - Figure 3-36

1 A B C D E F G H J K L M N P R T U V W Y AA AB
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
3 3 3 3 3 3 3 3 3 3 3 2 2

3
0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2

4
0 3 3 3 3 3 3 3 3 3 3 3 3 3

5
0 0 3 3 3

6
0 0 0 0 3

7
0 0 0 3

8
0 0 0 0 0 0 0 3

9
0 0 0 0 0

10
0 0 0 0 0 0

11
0 0 0

12
0 0 0 0 0 0

13
0 0 0 0 0 0

14
0 0 0 0 0 0 0

15
0 0 0

16
0 0 0 0

17
0 0 0

18
0 0

19

20
1 1

21
1 1 1 1 1 1 1 1 1 1 2

22
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 2

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2

1 1 1 1 1

1 1 1 1 1 1 1 1

3 3 3 3 3 2 2 3 3 3 3 3 3 3 2 2

3 3 3 3 3 3 2 2 2

0 0 0 0

3 1 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1 1 2 2 2

2 2 2 2

2 2 2 2 2 2

2 2 2 2 2 2

2 2 2

2 2

A B C D E F G H J K L M N P R T U V W Y AA AB

10

11

12

13

14

15

16

17

18

19

20

21

22

UG385_c3_36_110209

Figure 3-36: FG(G)484 PackageLX150 I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

297

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)484 PackageLX45T, LX100T, and LX150T


X-Ref Target - Figure 3-37

1 A B C D E F G H J K L M N P R T U V W Y AA AB 1

7
V

9
E

10

11

12

13
E

14

15
V

16

17

18

19

20

21
K

22 A B C D E F G H J K L M N P R T U V W Y AA AB

H V G

E V I O
E

e a

a a f g W A

a a

Y b P

C N B 0 D Z

10

11

12

13

14

15

16

17

18

19

20

21

22

User I/O Pins IO_LXXY_# VREF

Multi-Function Pins C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

Transceiver Pins

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

E MGTAVCC E V V MGTAVCCPLL

MGTRXP MGTRXN MGTTXN MGTTXP

V MGTAVTTRX MGTAVTTRCAL MGTAVTTTX MGTREFCLK (P) MGTREFCLK (N) G MGTRREF

O TDO M TMS D DONE_2


Z SUSPEND g e

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_37_111909

Figure 3-37:

FG(G)484 PackageLX45T, LX100T, and LX150T Pinout Diagram

Note: The RFUSE, VBATT, and VFS pins are no connects in the LX45T in the FG(G)484 package.

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)484 PackageLX45T, LX100T, and LX150T

X-Ref Target - Figure 3-38

1 A B C D E F G H J K L M N P R T U V W Y AA AB
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
0 0 3 3 3 3 3 3 3 3 3 3

3
0 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2

4
0 0 0 3 3 3 3 3 3 3 3 3 3 3 3

8
101 101

10
101 101

11

12
123 123

13

14
123 123

15

16

17

18
0 0 0 0 1 1 1 1 1 1

19
0 0 0

20
0 0 1

21
1 1

22 A B C D E F G H J K L M N P R T U V W Y AA AB

0 101
101

123 0 123 123 123

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 0

101 101

101 101

101 101 123

123 123

0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 2 1 1 1 1 1 1 1

0 3 3 3 3 3 3 3 2 2 2

0 0 3 3

0 0

0 0 0 0

123

0 0 0 0

0 0

1 3 1 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 2 2 2

3 2 2 2 2 2

2 2 2

10

11

12

13

14

15

16

17

18

19

20

21

22

UG385_c3_38_110209

Figure 3-38: FG(G)484 PackageLX45T, LX100T, and LX150T I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

299

Chapter 3: Pinout and I/O Bank Diagrams

CSG484 PackageLX45
X-Ref Target - Figure 3-39

1 A B C D E F G H J K L M N P R T U V W Y AA AB

3
H

10

11

12

13

14

15

16

17

18

19

20

21

22 A B C D E F G H J K L M N P R T U V W Y AA AB

n n n n n n n n n

K O M I

a a n n n n n n n n g 1 n D n C Y P b U B N Z 0 W A n a a a

10

11

12

13

14

15

16

17

18

19

20

21

22

User I/O Pins IO_LXXY_#

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND VCCAUX VCCINT VCCO n NC

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2

UG385_c3_39_111909

Figure 3-39:

CSG484 PackageLX45 Pinout Diagram

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CSG484 PackageLX45

X-Ref Target - Figure 3-40

1 A B C D E F G H J K L M N P R T U V W Y AA AB
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
3 3 3 3 3 3 3 3 3 3 3 3 3

3
3 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4
0 3 3 3 3 3 3 3 3 3 3 3 3 3

5
0 0 3 3 3

6
0 0 0 0 3

7
0 0 0 3

8
0 0 0 0 3 3 3

9
0 0 0

10
0 0 0 0 0 0

11
0 0 0

12
0 0 0

13
0 0

14
0 0 0

15
0 0 0

16
0 0 0

17
0 0 0

18
0 0 1

19
1 1 1

20
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

21
1 1 1 1 1 1 1 1 1 1 1 1 1 1

22
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1

1 1

1 1

1 1 1 1 1

1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 2 2 2

1 1 1 1 1 1 1 1 1 1 1 1 1 1

3 3 3 3 3 3 3 3 3 3 3 3

3 3 3 3 3 3 3 3

3 1 3 1 3 2 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1

1 1 1 1

3 3 2 2 2 2 2 2 2 2 2

1 2 2 2 2 2 2

3 3 3 3

A B C D E F G H J K L M N P R T U V W Y AA AB

10

11

12

13

14

15

16

17

18

19

20

21

22

UG385_c3_40_110209

Figure 3-40:

CSG484 PackageLX45 I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

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Chapter 3: Pinout and I/O Bank Diagrams

CS(G)484 PackageLX75
X-Ref Target - Figure 3-41

1 A B C D E F G H J K L M N P R T U V W Y AA AB

3
H

10

11

12

13

14

15

16

17

18

19

20

21

22 A B C D E F G H J K L M N P R T U V W Y AA AB

K O M I

a a n n n n n Y P b U B n n n n C N Z 0 n g 1 e D W A f a a a

1
User I/O Pins IO_LXXY_#

10

11

12

13

14

15

16

17

18

19

20

21

22
Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g e

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_41_111909

Figure 3-41:

CS(G)484 PackageLX75 Pinout Diagram

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CS(G)484 PackageLX75

X-Ref Target - Figure 3-42

1 A B C D E F G H J K L M N P R T U V W Y AA AB
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
3 3 3 3 3 3 3 3 3 3 3 3 3

3
3 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4
0 3 3 3 3 3 3 3 3 3 3 3 3 3

5
0 0 3 3 3

6
0 0 0 0 3

7
0 0 0 3

8
0 0 0 0 0 3 3 3

9
0 0 0 0 0

10
0 0 0 0 0 0

11
0 0 0

12
0 0 0 0 0 0

13
0 0 0 1 1 1

14
0 0 0

15
0 0 0

16
0 0 0

17
0 0 0

18
0 0 1

19
1 1 1

20
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

21
1 1 1 1 1 1 1 1 1 1 1 1 1 1

22
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1

1 1

1 1 1 1 1

1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 2 2 2

1 1 1 1 1 1 1 1 1 1 1 1 1 1

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2

3 3 3 3 3 3 3 3

0 0 0 1

3 1 3 1 3 3 3 3 2 2 2 2 2 2 2 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1

1 1 1 1

1 2 2 2 2 2 2

3 3 3 3

2 2

2 2 2

A B C D E F G H J K L M N P R T U V W Y AA AB

10

11

12

13

14

15

16

17

18

19

20

21

22

UG385_c3_42_110209

Figure 3-42: CS(G)484 PackageLX75 I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

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Chapter 3: Pinout and I/O Bank Diagrams

CS(G)484 PackageLX100 and LX150


X-Ref Target - Figure 3-43

1 A B C D E F G H J K L M N P R T U V W Y AA AB

3
H

10

11

12

13

14

15

16

17

18

19

20

21

22 A B C D E F G H J K L M N P R T U V W Y AA AB

K O M I

a a a a g 1 e D C Y P b U B N Z 0 W A f a

1
User I/O Pins IO_LXXY_#

10

11

12

13

14

15

16

17

18

19

20

21

22
Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g e

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_43_111909

Figure 3-43: CS(G)484 PackageLX100 and LX150 Pinout Diagram

304

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CS(G)484 PackageLX100 and LX150

X-Ref Target - Figure 3-44

1 A B C D E F G H J K L M N P R T U V W Y AA AB
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
3 3 3 3 3 3 3 3 3 3 3 3 3

3
3 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4
0 3 3 3 3 3 3 3 3 3 3 3 3 3

5
0 0 3 3 3

6
0 0 0 0 3

7
0 0 0 3

8
0 0 0 0 0 3 3 3

9
0 0 0 0 0

10
0 0 0 0 0 0

11
0 0 0

12
0 0 0 0 0 0

13
0 0 0 1 1 1

14
0 0 0

15
0 0 0

16
0 0 0

17
0 0 0

18
0 0 1

19
1 1 1

20
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

21
1 1 1 1 1 1 1 1 1 1 1 1 1 1

22
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1

1 1

1 1 1 1 1

1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 2 2 2

1 1 1 1 1 1 1 1 1 1 1 1 1 1

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

3 3 3 3 3 3 3 3 2

0 0 0 1

3 1 3 1 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1

1 1 1 1

1 2 2 2 2 2 2

3 3 3 3 2 2

2 2 2 2 2 2

A B C D E F G H J K L M N P R T U V W Y AA AB

10

11

12

13

14

15

16

17

18

19

20

21

22

UG385_c3_44_110209

Figure 3-44:

CS(G)484 PackageLX100 and LX150 I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

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Chapter 3: Pinout and I/O Bank Diagrams

CS(G)484 PackageLX75T
X-Ref Target - Figure 3-45

1 A B C D E F G H J K L M N P R T U V W Y AA AB

3
H

7
V

9
E

10

11

12

13
E

14

15
V

16

17

18

19

20

21

22 A B C D E F G H J K L M N P R T U V W Y AA AB

E V G
V

K V E I O M
E E

a a a a e g n n Y P b U B n n C N Z 0 1 D W A f a

10

11

12

13

14

15

16

17

18

19

20

21

22

User I/O Pins IO_LXXY_# VREF

Multi-Function Pins C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

Transceiver Pins

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

E MGTAVCC

MGTRXP MGTRXN MGTTXN MGTTXP

E V

MGTAVCCPLL

V MGTAVTTRX MGTAVTTRCAL MGTAVTTTX MGTREFCLK (P) MGTREFCLK (N) G MGTRREF

O TDO M TMS D DONE_2


Z SUSPEND g e

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_45_111909

Figure 3-45:

CS(G)484 PackageLX75T Pinout Diagram

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CS(G)484 PackageLX75T

X-Ref Target - Figure 3-46

1 A B C D E F G H J K L M N P R T U V W Y AA AB
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
3 3 3 3 3 3 3 3 3 3 3 3 3

3
3 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4
0 3 3 3 3 3 3 3 3 3 3 3 3 3 3

6
101

8
101 101

10
101 101

11

12
123 123

13

14
123 123

15

16
123

17

18
0 0 0 0

19
0

20
1 0 1

21
1 1 1 1 1 1 1 1 1 1 1 1 1

22
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 101 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 3 3 3 3 3 3 0 0 0
101 101

123 0

101 101

101 101

123 123 123

123 123

0 0 0 0

0 1

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0

123

0 0

0 1 1

1 1 1 1 1 1 1 1 1 1 2 1 1 2 2 2 2 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1

1 3 1 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 3 3 3 3 2 2 2 2 2 2 2 3 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1 2 2 2 2 2 2 2 1 1 1 1 1 1

3 3 3 3

A B C D E F G H J K L M N P R T U V W Y AA AB

10

11

12

13

14

15

16

17

18

19

20

21

22

UG385_c3_46_110209

Figure 3-46:

CS(G)484 PackageLX75T I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

307

Chapter 3: Pinout and I/O Bank Diagrams

CS(G)484 PackageLX45T, LX100T, and LX150T


X-Ref Target - Figure 3-47

1 A B C D E F G H J K L M N P R T U V W Y AA AB

3
H

7
V

9
E

10

11

12

13
E

14

15
V

16

17

18

19

20

21

22 A B C D E F G H J K L M N P R T U V W Y AA AB

E V G
V

K V E I O M
E E

a a a a e g 1 D C Y P b U B N Z 0 W A f a

1
User I/O Pins IO_LXXY_# VREF P_GCLK N_GCLK D0 - D15 A0 - A25

10

11

12

13

14

15

16

17

18

19

20

21

22

Multi-Function Pins C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

Transceiver Pins

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

E MGTAVCC

MGTRXP MGTRXN MGTTXN MGTTXP

E V

MGTAVCCPLL

V MGTAVTTRX MGTAVTTRCAL MGTAVTTTX MGTREFCLK (P) MGTREFCLK (N) G MGTRREF

O TDO M TMS D DONE_2


Z SUSPEND g e

a FCS / FWE / FOE / HDC / LDC

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_47_111909

Figure 3-47:

CS(G)484 PackageLX45T, LX100T, and LX150T Pinout Diagram

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

CS(G)484 PackageLX45T, LX100T, and LX150T

X-Ref Target - Figure 3-48

1 A B C D E F G H J K L M N P R T U V W Y AA AB
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
3 3 3 3 3 3 3 3 3 3 3 3 3

3
3 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4
0 3 3 3 3 3 3 3 3 3 3 3 3 3 3

6
101

8
101 101

10
101 101

11

12
123 123

13

14
123 123

15

16
123

17

18
0 0 0 0

19
0

20
1 0 1

21
1 1 1 1 1 1 1 1 1 1 1 1 1

22
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 101 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 0 0 0
101 101

123 0

101 101

101 101

123 123 123

123 123

0 0 0 0

0 1

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0

123

0 0

0 1 1

1 1 1 1 1 1 1 1 1 1 2 1 1 2 2 2 2 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1

1 3 1 3 3 3 3 2 2 2 2 2 3 2 2 2 2 2 2 2 2 3 3 3 3 2 2 2 2 2 2 2 3 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1 2 2 2 2 2 2 2 1 1 1 1 1 1

3 3 3 3

A B C D E F G H J K L M N P R T U V W Y AA AB

10

11

12

13

14

15

16

17

18

19

20

21

22

UG385_c3_48_110209

Figure 3-48: CS(G)484 PackageLX45T, LX100T, and LX150T I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

309

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)676 PackageLX45
X-Ref Target - Figure 3-49

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1
User I/O Pins IO_LXXY_#

3
H

10
n n

11

12

13

14

15

16

17

18

19

20

21

22

23

24
O

25

26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF

n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n

n n n n n n n n n n n

n n n n n n n n n n n n n n n n n n n n n n

n n n n n n n n n n n n n n n n n n n n n I n n n n n n n n n K n n n n n n

M n n n n

n n n n

n n n n n n n n n n n n n n 1 Y P b U n n n n n n

n n n n a a

n a n n N B n n g C 0 Z W D A a a

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26
Other Pins GND VCCAUX VCCINT VCCO n NC

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2

UG385_c3_49_111909

Figure 3-49:

FG(G)676 PackageLX45 Pinout Diagram

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX45

X-Ref Target - Figure 3-50

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
0 3 3 3 3

3
0 3 3 3 3 3

4
0 0 3 3

5
0 0

6
0 0 0 0

7
0 0

8
0 0

9
0 0

10

11
0 0

12
0 0

13
0 0

14
0 0 0 0

15
0 0

16
0 0

17
0 0

18
0 0 0 0

19
0 0

20
0 0 0

21
0 0 0

22
0 0

23
1 1

24
1 1

25
1 1 1 1

26
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 3 3 3 3 2 2 2 2 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 3 3 3 3 3 1 3 3 3 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

UG385_c3_50_111709

Figure 3-50: FG(G)676 PackageLX45 I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

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311

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)676 PackageLX75
X-Ref Target - Figure 3-51

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1
User I/O Pins IO_LXXY_#

3
H

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24
O

25

26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF

n n n n n n n n n n n

n n n n n n n n n

n n n n n n n n n n n n n n n n n n n n

n n n n n n n n n n n n n n I K

a n n n n n n n n Y P b U B 0 n n n n 1 n n n n n n n n n n n n n n n n n n n n f n n n N n g C Z W D A a e a

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26
Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g e

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_51_111909

Figure 3-51:

FG(G)676 PackageLX75 Pinout Diagram

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX75

X-Ref Target - Figure 3-52

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3

2
0 4 4 4 4 4 4 4 3 3 3 3 3 3 3

3
0 4 4 4 4 4 4 4 4 3 4 3 3 3 3 3 3 3 3 3 3 3 3 3

4
0 0 4 4 4 4 3 3 3 3 3 3 3

5
0 0 4 4 4 4 4 4

6
0 0 0 0

7
0 0

8
0 0

9
0 0

10
0 0

11
0 0

12
0 0

13
0 0

14
0 0 0 0

15
0 0

16
0 0

17
0 0

18
0 0 0 0

19
0 0

20
0 0 0

21
0 0 0

22
0 0 5 5

23
5 5 5 5

24
5 5 5 5 5 5 5 5 5 1 5 1 1 1 1 1 1 1 1

25
5 5 5 5 5 5 5 5 1 1 1 1 1 1 1

26
5 5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1

0 0 4 4 4 3 3 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 3 3 3 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 4 4 3 3 3 3 3 3 0 4 4 4 0 0 0

0 0 5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 5 1 1 1 1 1 1 1 1 1 1 1 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 5 5 5 5

5 5 1 1 1 1 1 1 1

3 3 3 3 3 3 3

3 3 3 3

3 3 3 3 2 2

3 3 3 3 2 2

1 1 1

1 1 1 1 1 1

A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

UG385_c3_52_110209

Figure 3-52: FG(G)676 PackageLX75 I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

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313

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)676 PackageLX75T
X-Ref Target - Figure 3-53

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1
User I/O Pins IO_LXXY_# VREF P_GCLK N_GCLK D0 - D15 A0 - A25

7
V

10

11
E

12

13

14

15
E

16

17

18

19
V

20

21

22

23

24
K

25

26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF

n n V n G n H

E n n n n

E V n n n n n n M O

n n n n n

n n n n

n n n n n n n Y P b n n
V

n n n n n n E
E

e f g n n n V W A 1 N B a C 0 D Z a a a a

n n

G V

U E

10

11

12

13

14

15

16

17

18

19

20

V E

Multi-Function Pins C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

Transceiver Pins

E MGTAVCC
E V V

MGTAVCCPLL

V MGTAVTTRX MGTAVTTRCAL MGTAVTTTX MGTREFCLK (P) MGTREFCLK (N) G MGTRREF

21

22

23

24

25

26

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

MGTRXP MGTRXN MGTTXN MGTTXP

O TDO M TMS D DONE_2


Z SUSPEND g e

a FCS / FWE / FOE / HDC / LDC

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_53_110209

Figure 3-53:

FG(G)676 PackageLX75T Pinout Diagram

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX75T

X-Ref Target - Figure 3-54

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3

2
0 4 4 4 4 4 4 4 3 3 3 3 3 3

3
0 0 0 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 2 2

4
0 0

8
101 101

10
101 101

11

12
0 0

13
0 0 0 0

14
0 0

15

16
123 123

17

18
123 123

19

20
123

21

22
0 0 0 5

23
0 0 5 5 5 5

24

25
5 5 5 5 5 5 5 5 1 1 1 1 1 1

26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF

0 101 0 101
101 101

123 0 123 123

5 5 5 5 5 5 5 5 5 1 5 1 1 1 1 1 1 1 1

5 5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1

101 101

101 101

123 123

123 123

0 0 0 0 5 5 5 5 5 1 1 1 1 1 2 2 2 2 2 2 2 2 2
267 267 2

4 4

0 0 4

0 0 0 4 4 4 4 0 0 0 4 4 4 3 3 3 3 3 2 2
245

0 0 0 4 4 4 3 3 3 3 3 2 2 2 2
245 245 245 245 245 245

0 0 0 5 5 0 5 5 5 1 1 1 1 1 1

0 0 4 4 4 3 3 3 3 3 3 2 3 4 4 3

0 0 0 0 0

0 0 0

0 0

0 0 0

5 5 5 5 1 1 1

5 5 5 1 5 1 1 1 1 1 1 1 1 1 5

4 4 4 3 3 3 3 3

4 4

3 3 3 3 3 3 3

3 3 3 3

1 1

2 2 2 2 2 2
245 245

1 1

3 2

2 2 2 2 2
267 267

2 2 2

3 3 3 2 2 3 2 2

2 2

2
267 267 267 267 267 267 267 267

1 1 2 2

1 1 1 1 2 2

2 2 2 2 2 2 2

2
245

245

2 245

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

UG385_c3_54_110209

Figure 3-54:

FG(G)676 PackageLX75T I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

315

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)676 PackageLX100
X-Ref Target - Figure 3-55

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1
User I/O Pins

3
H

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24
O

25

26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF

M n n n n n n n n n n n n n n n n n n I K

a e f g 1 Y P b U B 0 N C Z W D A a

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

IO_LXXY_#

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g e

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_55_111909

Figure 3-55:

FG(G)676 PackageLX100 Pinout Diagram

316

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX100

X-Ref Target - Figure 3-56

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3

2
0 4 4 4 4 4 4 4 3 3 3 3 3 3 3

3
0 4 4 4 4 4 4 4 4 3 4 3 3 3 3 3 3 3 3 3 3 3 3 3

4
0 0 4 4 4 4 3 3 3 3 3 3 3

5
0 0 0 4 4 4 4 4 4

6
0 0 0 0 0

7
0 0 0 0

8
0 0 0 0 0

9
0 0 0 0

10
0 0 0 0 0 0

11
0 0 0 0

12
0 0 0 0

13
0 0 0 0

14
0 0 0 0 0

15
0 0 0 0

16
0 0 0 0 0 0 0 0

17
0 0 0 0 0 0 0

18
0 0 0 0 0 0

19
0 0 0 0 5

20
0 0 0 0 0

21
0 0 0

22
0 0 5 5

23
5 5 5 5

24
5 5 5 5 5 5 5 5 5 1 5 1 1 1 1 1 1 1 1

25
5 5 5 5 5 5 5 5 1 1 1 1 1 1 1

26
5 5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1

4 4 4 3 3

4 4 4 4 3 3 3 3

0 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 4 4 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 3 4

0 0 0 0

5 5 5 5 5 1 1 1 1 1 1 1

5 5 5 5 1 1 1 1 1

5 5 5 5

5 5 1 1

5 1

5 1 1 1 1 1 1 1 1 1

1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 2

1 1 1 1 1 1 1 1 2 2 2

3 3 3 3 3 3 3

3 3 3 3

1 1 1 1 1 1 1

1 1 1 1 1

3 3 3 3 3 2 2 3 3 3 2 2 3 3

1 1

1 1 1 1 2 1 2 1

3 3 3 3 2 2

3 3 3 3 2 2

2 2 2 2 2 2 2 2

1 1 1 1 1 1

2 2

2 2 2

A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

UG385_c3_56_110209

Figure 3-56: FG(G)676 PackageLX100 I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

317

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)676 PackageLX100T
X-Ref Target - Figure 3-57

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1
User I/O Pins IO_LXXY_# VREF P_GCLK N_GCLK D0 - D15 A0 - A25

7
V

10

11
E

12

13

14

15
E

16

17

18

19
V

20

21

22

23

24
K

25

26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF

E V G

E V

n n n n n

n n n n M O

n H

n n n n n G V E Y P b
V E

e f g n V E
E

a a W A

a a

n 1 N B a C 0 D

10

11

12

13

14

15

16

17

18

19

20

Multi-Function Pins C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

Transceiver Pins

E MGTAVCC
E V V

MGTAVCCPLL

V MGTAVTTRX MGTAVTTRCAL MGTAVTTTX MGTREFCLK (P) MGTREFCLK (N) G MGTRREF

21

22

23

24

25

26

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

MGTRXP MGTRXN MGTTXN MGTTXP

O TDO M TMS D DONE_2


Z SUSPEND g e

a FCS / FWE / FOE / HDC / LDC

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_57_111909

Figure 3-57:

FG(G)676 PackageLX100T Pinout Diagram

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX100T

X-Ref Target - Figure 3-58

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3

2
0 4 4 4 4 4 4 4 3 3 3 3 3 3

3
0 0 0 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 2 2

4
0 0

8
101 101

10
101 101

11

12
0 0

13
0 0 0 0

14
0 0

15

16
123 123

17

18
123 123

19

20

21

22
0 0 0 5

23
0 0 5 5 5 5

24
5 5 5 5 5 5 5 5 5 1 5 1 1 1 1 1 1 1

25
5 5 5 5 5 5 5 5 1 1 1 1 1 1

26
5 5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1

0 101 0 101 0 0
101 101

123 123 0 123 123

101 101

101 101

123 123

123 123

0 0 0 0 5 5 5 5 5 1 1 1 1 1 2 2 2 2 2
267 267

4 4

0 0 4

0 0 0 4 4 4 4 0 0 0 4 4 4 3 3 3 3 3 2 2 2 2 2
245

0 0 0 0 4 4 4 3 3 3 3 3 2 2
245 245 245 245

0 0 0 0 0 4 4 3 0 0 0 0 0 0 4 4 4 3 3 3 3 3 3 2 2 2 2 2
245 245 245 245

0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 5 5 1 1 1 1 0 0 0 5 5 5 1 1 1 1 1

5 5 5 5 1 1 1

5 5 5 1 5 1 1 1 1 1 1 1 1 1 5

4 4 4 3 3 3 3 3

4 4

3 3 3 3 3 3 3

3 3 3 3

3 2 2 2 2 2 2 2
245 245

1 1

3 2

2 2 2 2 2 2 2 2 2 2 2 2 2
267 267 267 267

2 2 2 2 2
267 267 267 267

2 2 2 2

2 2

2 2 2

1 2 2 2 2 1 2 2 1 1 1 1 1 2 2

3 3 3 2 2 3 2 2 2 2

267 267 2

2 245

A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

UG385_c3_58_110209

Figure 3-58:

FG(G)676 PackageLX100T I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

319

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)676 PackageLX150
X-Ref Target - Figure 3-59

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1
User I/O Pins IO_LXXY_#

3
H

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24
O

25

26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF

M K I

a e f g 1 Y P b U B 0 N C Z W D A a

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26
Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g e

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_59_111909

Figure 3-59:

FG(G)676 PackageLX150 Pinout Diagram

320

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX150

X-Ref Target - Figure 3-60

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3

2
0 4 4 4 4 4 4 4 3 3 3 3 3 3 3

3
0 4 4 4 4 4 4 4 4 3 4 3 3 3 3 3 3 3 3 3 3 3 3 3

4
0 0 4 4 4 4 3 3 3 3 3 3 3

5
0 0 0 4 4 4 4 4 4

6
0 0 0 0 0

7
0 0 0 0

8
0 0 0 0 0 0 0 4 4 4 3 3 3

9
0 0 0 0 0 0 4 4 3 3

10
0 0 0 0 0 0 0 4 4 3

11
0 0 0 0 0

12
0 0 0 0 0 0 0

13
0 0 0 0 0 0 0

14
0 0 0 0 0 0 0

15
0 0 0 0 0

16
0 0 0 0 0 0 0 0 0

17
0 0 0 0 0 0 0

18
0 0 0 0 0 0

19
0 0 0 0 5

20
0 0 0 0 0

21
0 0 0

22
0 0 5 5

23

24

25

26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF

5 5 5 5 5 5 5 5 5 5 5 1 1 5 5 5 5 1 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 5 5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1

4 4 4 3 3

4 4 4 4 3 3 3 3

5 5 5 5 5 1 1 1 1 1 1 1

5 5 5 5 1 1 1 1 1

5 5 5 5

5 1

5 1 1 1 1 1 1 1 1 1

0 0

0 0

0 0

1 1 3 1 1 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 3 3

1 1 1 1 1 1 1 1 2 2 2

3 3 3 3 3 3 3

3 3 3 3

1 1 1 1 1 1 1

3 3 3 3 3 3 2 2 2 2 2 2 2 2 3 3 3 3 3 3

3 3 3 3 3 2 2 3 3 3 2 2 3 3

1 1

1 1 1 2 2

3 3 3 3 2 2

3 3 3 3 2 2

2 2 2 2 2 2 2 2

2 2

2 2 2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

UG385_c3_60_111709

Figure 3-60: FG(G)676 PackageLX150 I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

321

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)676 PackageLX150T
X-Ref Target - Figure 3-61

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1
User I/O Pins IO_LXXY_# VREF P_GCLK N_GCLK D0 - D15 A0 - A25

7
V

10

11
E

12

13

14

15
E

16

17

18

19
V

20

21

22

23

24
K

25

26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF

E V G
V

E V M O

e f g G V E Y P b
V E

a a

a a

10

11

12

13

14

15

16

17

18

19

20

V E
E

W A 1 N B a C 0 D

Multi-Function Pins C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

Transceiver Pins

E MGTAVCC
E V V

MGTAVCCPLL

V MGTAVTTRX MGTAVTTRCAL MGTAVTTTX MGTREFCLK (P) MGTREFCLK (N) G MGTRREF

21

22

23

24

25

26

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

MGTRXP MGTRXN MGTTXN MGTTXP

O TDO M TMS D DONE_2


Z SUSPEND g e

a FCS / FWE / FOE / HDC / LDC

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_61_111909

Figure 3-61:

FG(G)676 PackageLX150T Pinout Diagram

322

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)676 PackageLX150T

X-Ref Target - Figure 3-62

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3

2
0 4 4 4 4 4 4 4 3 3 3 3 3 3

3
0 0 0 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 2 2

4
0 0

8
101 101

10
101 101

11

12
0 0

13
0 0 0

14
0 0

15

16
123 123

17

18

19

20

21

22
0 0 0 5

23
0 0 5 5 5 5

24
5 5 5 5 5 5 5 5 5 1 5 1 1 1 1 1 1 1

25
5 5 5 5 5 5 5 5 1 1 1 1 1 1

26
5 5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1

0 101 0 101 0 0
101 101

123 123 123 123 123 123

123 123 0

101 101

101 101

123 123

0 0 0 0 5 5 5 5 5 1 1 1 1 1 2 2 2 2 2
267 267

4 4

0 0 4

0 0 0 4 4 4 4 0 0 0 4 4 4 3 3 3 3 3 2 2 2 2 2
245

0 0 0 0 4 4 4 3 3 3 3 3 2 2
245 245 245 245

0 0 0 0 0 4 4 3 0 0 0 0 4 4 4 3 3 3 3 3 3 2 2 2 2 2
245 245 245 245

0 0 0 0 0 0

0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0 0 0 5 5 1 1 1 1 0 0 0 5 5 5 1 1 1 1 1

5 5 5 5 1 1 1

5 5 5 1 5 1 1 1 1 1 1 1 1 1 5

4 4 4 3 3 3 3 3

4 4

3 3 3 3 3 3 3

3 3 3 3

3 2 2 2 2 2 2
245 245

2 2 2 2 2 2 2 2 2 2
267 267

1 1

3 2

2 2 2 2

2 2 2 2

2 2 2 2 2 2 2 2

2 2 2
267 267 267 267 267 267

2 2 2

1 2 2 2 2 1 2 2 1 1 1 1 1 2 2

3 3 3 2 2 3 2 2 2 2

2 2 2

2 2

267 267 2

2 245

A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

UG385_c3_62_110209

Figure 3-62:

FG(G)676 PackageLX150T I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

323

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)900 PackageLX100T
X-Ref Target - Figure 3-63

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK 1

10
V

11

12

13

14
E

15

16

17

18
E

19

20

21

22
V

23

24

25

26

27

28

29

30 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK

n n n n H n n V n n G n n

E n n

E V n n n n K I M n n O

E V

n n

n n

n n n P n n n n G n n Y b
V V

n n W A n U n n n n f V E
E

a Z g D

a a e a a

n n

V E
E E E

1 N B C 0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

User I/O Pins IO_LXXY_# VREF

Multi-Function Pins C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

Transceiver Pins

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

E MGTAVCC E V V MGTAVCCPLL

MGTRXP MGTRXN MGTTXN MGTTXP

V MGTAVTTRX MGTAVTTRCAL MGTAVTTTX MGTREFCLK (P) MGTREFCLK (N) G MGTRREF

O TDO M TMS D DONE_2


Z SUSPEND g e

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_63_111909

Figure 3-63:

FG(G)900 PackageLX100T Pinout Diagram

324

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX100T

X-Ref Target - Figure 3-64

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3

3
4 4

4
4 4

5
4 4 4 4 4 4

6
0 0 0 0 0 0

7
0 0 0 0 0

9
101 101

10

11
101 101

12

13
101 101

14

15
0 0

16
0 0 0

17
0 0

18

19
123 123

20

21
123 123

22

23
123 123

24

25
0 0

26
5 5

27
5 5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1

28
5

29
5 5 5

30
5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

101 101

101 101

101 101

123 123

123 123

123 123

0 0 0 0 0 0 0 0 5 5

4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

5 5 5 5 5

5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 5 5

0 0 0 0 0 0 0 0 0 0 0 0 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0

4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 4 4 3

4 3 3 3 3 3 3 3 3 3 3 3 2 3 3 2 2 2
245

5 1 1 1 5 1 1 1 1

5 5 5 1 1 1 1 1 1 1 1 1 1 1

3 3 3

3 3 3 3 3 3 2 2 2 2 2
245 245 245 245 245 245 245 245

3 3 3 3 2 2 2 2 2 2 2 2 2
245 245

1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
267 267 267 267

1 1 1 1

1 2 2 2 2 2 2

1 1 2 2 2 2 2
267 267

2 2 2 2 2 2 2 2 2 2

2 2 2 2 2
267 267

2 2 2

2 2 2 2 2 2 1 2 2 2 2 1 1 2 2 1 1

2 2

2 2 2

1 1 1 1 1

267 267

267 267

245

A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

UG385_c3_64_110209

Figure 3-64:

FG(G)900 PackageLX100T I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

325

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)900 PackageLX150
X-Ref Target - Figure 3-65

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK 1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK

K H O I M

a W A P Z g D

a a e a f a

N Y b U 1 B C 0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

User I/O Pins IO_LXXY_#

Multi-Function Pins VREF P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

O TDO M TMS D DONE_2


Z SUSPEND g e

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_65_012810

Figure 3-65:

FG(G)900 PackageLX150 Pinout Diagram

326

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX150

X-Ref Target - Figure 3-66

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3

3
4 4

4
4 4

5
4 4 4 4 4 4 4 4 3

6
0 0 0 0 0 0 4 4 4 3 3

7
0 0 0 0 0 0

8
0 0 0 0 0 0

9
0 0 0 0 0 0

10
0 0 0 0

11
0 0 0 0 0

12
0 0 0 0 0 0 0 0

13
0 0 0 0 0 0 0 0

14
0 0 0 0 0 0 0 0

15
0 0 0 0 0 0 0 0

16
0 0 0 0 0 0

17
0 0 0 0 0 0 0 0

18
0 0 0 0 0 0

19
0 0 0 0 0 0 0 0

20
0 0 0 0

21
0 0 0 0 0

22
0 0 0 0 0 0

23
0 0 0 0 0 0

24
0 0 0 0

25
0 0 0 0 5 5

26
5 5 5 5 5 5 5

27
5 5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1

28
5

29
5 5 5

30
5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 5 5

0 0

0 0 0

0 0

0 0 0

4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 2 2 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 1 1 1 1 1 3 3 3 3 3 3 1 3 3 3 1 1 1 1

5 1 5 1 1 1 1 1 1 1 1

5 5 5 1 1 1 1 1 1 1 1 1 1 1

3 3 3 3 3 3 3 3 3

3 3 3 3 3 3 3 3 3 3 3 2 2 2 2

2 2 2 2 2 2 2 1 2 2 2

1 1 1 1 2 2

1 1 1 1 1

A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

UG385_c3_66_111709

Figure 3-66: FG(G)900 PackageLX150 I/O Bank Diagram

Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

www.xilinx.com

327

Chapter 3: Pinout and I/O Bank Diagrams

FG(G)900 PackageLX150T
X-Ref Target - Figure 3-67

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK 1

10
V

11

12

13

14
E

15

16

17

18
E

19

20

21

22
V

23

24

25

26

27

28

29

30 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK

E V G
V

E V

K I

O M

a W A P U Z g D G V E Y b
V E

a a e a f a

10

11

12

13

14

15

16

17

18

19

20

21

22

V E
E E E

1 N B C 0

23

24

25

26

27

28

29

30

User I/O Pins IO_LXXY_# VREF

Multi-Function Pins C CCLK B CSI b CSO N DIN A DOUT_BUSY H HSWAPEN Y INIT

Transceiver Pins

Dedicated Pins P PROGRAM_B_2 K TCK I TDI

Other Pins GND f VFS VBATT VCCAUX VCCINT VCCO n NC

P_GCLK N_GCLK D0 - D15 A0 - A25


a FCS / FWE / FOE / HDC / LDC

E MGTAVCC E V V MGTAVCCPLL

MGTRXP MGTRXN MGTTXN MGTTXP

V MGTAVTTRX MGTAVTTRCAL MGTAVTTTX MGTREFCLK (P) MGTREFCLK (N) G MGTRREF

O TDO M TMS D DONE_2


Z SUSPEND g e

U RDWR_B_VREF 1 0 M1, M0
W AWAKE

CMPCS_B_2 RFUSE

UG385_c3_67_111909

Figure 3-67:

FG(G)900 PackageLX150T Pinout Diagram

328

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Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011

FG(G)900 PackageLX150T

X-Ref Target - Figure 3-68

1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

2
4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3

3
4 4

4
4 4

5
4 4 4 4 4 4

6
0 0 0 0 0 0

7
0 0

9
101 101

10

11
101 101

12

13
101 101

14

15
0 0

16
0 0 0

17
0 0

18

19
123 123

20

21
123 123

22

23
123 123

24

25
0 0

26
5 5

27
5 5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1

28
5

29
5 5 5

30
5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0 0 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 3 3 2 2 2 2 2 2
245 245

101 101

101 101

101 101

123 123

123 123

123 123

0 0 0 0 0 0 0 0 5 5

4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

5 5 5 5 5

5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 5 5

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0

0 0 0

0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0

4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 4 4 3

0 0 3

5 1 1 1 1 5 1 1 1 1

5 5 5 1 1 1 1 1 1 1 1 1 1 1

1 3 3 3 3 3 2 2 2
245 245 245 245

1 3 3 2 2 2 2 2 2
245 245 245 245

1 1 1 1

3 3 3 3 2 2

2 2 2 2 2 2 2 2 2 2 2

2 2 2 2 2 2 2
245 245

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
267 267 267 267

2 2 2 2 2 2
267 267

1 2 2 2 2 2 2

1 1 2 2 2 2 2
267 267

2 2 2 2 2 2 2

2 2 2 2 2 2 2

2 2 2

2 2 2 2 2 2 1 2 2 2 2 1 1 2 2 1 1

2 2 2

1 1 1 1 1

267 267

267 267

A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

UG385_c3_68_111909

Figure 3-68:

FG(G)900 PackageLX150T I/O Bank Diagram

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Chapter 3: Pinout and I/O Bank Diagrams

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Chapter 4

Mechanical Drawings
Summary
This chapter provides mechanical drawings of the following Spartan-6 FPGA packages: TQG144 Thin Quad Flat-Pack Package Specifications (0.5 mm Pitch), page 332 CPG196 Chip-Scale BGA Package Specifications (0.5 mm Pitch), page 333 CSG225 Chip-Scale BGA Package Specifications (0.8 mm Pitch), page 334 FT(G)256 Fine-Pitch Thin BGA Package Specifications (1.00 mm Pitch), page 335 CSG324 Chip-Scale BGA Package Specifications (0.8 mm Pitch), page 336 FG(G)484 Fine-Pitch BGA Package Specifications (1.00 mm Pitch), page 337 CS(G)484 Chip-Scale BGA Package Specifications (0.8 mm Pitch), page 338 FG(G)676 Fine-Pitch BGA Package Specifications (1.00 mm Pitch), page 339 FG(G)900 Chip-Scale BGA Package Specifications (1.00 mm Pitch), page 340

Material Declaration Data Sheets (MDDS) are available for each package listed at: http://www.xilinx.com/support/documentation/spartan-6.htm#131532 UG393, Spartan-6 FPGA PCB Design and Pin Planning Guide includes recommendations for board layout, PCB design rules, and pin planning for these Spartan-6 FPGA packages.

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TQG144 Thin Quad Flat-Pack Package Specifications (0.5 mm Pitch)


X-Ref Target - Figure 4-1

ug385_c4_01_100509

Figure 4-1:

TQG144 Thin Quad Flat-Pack Package

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CPG196 Chip-Scale BGA Package Specifications (0.5 mm Pitch)

CPG196 Chip-Scale BGA Package Specifications (0.5 mm Pitch)


X-Ref Target - Figure 4-2

ug385_c4_02_100709

Figure 4-2:

CPG196 Chip-Scale BGA Package

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CSG225 Chip-Scale BGA Package Specifications (0.8 mm Pitch)


X-Ref Target - Figure 4-3

UG385_c4_03_110509

Figure 4-3:

CSG225 Chip-Scale BGA Package

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FT(G)256 Fine-Pitch Thin BGA Package Specifications (1.00 mm Pitch)

FT(G)256 Fine-Pitch Thin BGA Package Specifications (1.00 mm Pitch)


X-Ref Target - Figure 4-4

ug385_c4_04_021411

Figure 4-4:

FT(G)256 Fine-Pitch Thin BGA Package

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CSG324 Chip-Scale BGA Package Specifications (0.8 mm Pitch)


X-Ref Target - Figure 4-5

ug385_c4_05_110509

Figure 4-5:

CSG324 Chip-Scale BGA Package

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FG(G)484 Fine-Pitch BGA Package Specifications (1.00 mm Pitch)

FG(G)484 Fine-Pitch BGA Package Specifications (1.00 mm Pitch)

ug385_c4_06_061709

Figure 4-5:

FG(G)484 Fine-Pitch BGA Package

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CS(G)484 Chip-Scale BGA Package Specifications (0.8 mm Pitch)


X-Ref Target - Figure 4-6

ug385_c4_07_061809

Figure 4-6:

CS(G)484 Chip-Scale BGA Package

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FG(G)676 Fine-Pitch BGA Package Specifications (1.00 mm Pitch)

FG(G)676 Fine-Pitch BGA Package Specifications (1.00 mm Pitch)


X-Ref Target - Figure 4-7

ug385_c4_08_051711

Figure 4-7:

FG(G)676 Fine-Pitch BGA Package

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FG(G)900 Chip-Scale BGA Package Specifications (1.00 mm Pitch)


X-Ref Target - Figure 4-8

ug385_c4_09_111809

Figure 4-8:

FG(G)900 Chip-Scale BGA Package

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Chapter 5

Thermal Specifications
Summary
This chapter provides thermal data associated with Spartan-6 FPGA packages. The following topics are discussed: Introduction Cavity-Up Plastic BGA Packages Support for Compact Thermal Models (CTM) Soldering Guidelines References

Introduction
Spartan-6 devices are offered in a wide variety of packages. The suite of packages is used to address the various power requirements of the Spartan-6 devices. All Spartan-6 devices are implemented in the 45 nm process technology All Spartan-6 devices feature versatile SelectIO resources that support a variety of I/O standards. They also include DSPs and other traditional features and blocks (such as block RAM) contained in earlier Spartan and Virtex products. In line with Moore's law, the transistor count in this family of devices has been increased substantially. Though several innovative features at the silicon level have been deployed to minimize power dissipation, including leakage at the 45 nm node, these products have more densely packed transistors and embedded blocks with the capability to run faster than before. Thus, a fully configured Spartan-6 FPGA design that exploits the internal logic speed and incorporates several embedded circuits and systems can present power consumption challenges that must be managed. Unlike features in an ASIC or a microprocessor, the combination of FPGA features used in a user application are not known to the component supplier. Therefore, it remains a challenge for Xilinx to predict the power requirements of a given FPGA when it leaves the factory. Accurate estimates are obtained when the board design takes shape. For this purpose, Xilinx offers and supports a suite of integrated device power analysis tools to help users quickly and accurately estimate their design power requirements. Spartan-6 devices are supported similarly to previous FPGA products. The uncertainty of design power requirements makes it difficult to apply canned thermal solutions to fit all users. Therefore, Xilinx devices do not come with preset thermal solutions. The users operating conditions dictate the appropriate solution.

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Table 5-1 shows the thermal resistance data for Spartan-6 devices (grouped in the packages offered). The data includes junction-to-ambient in still air, junction-to-case, and junctionto-board data based on standard JEDEC four-layer measurements. Thermal data is available on the Xilinx website at: http://www.xilinx.com/cgi-bin/thermal/thermal.pl. Compact package thermal models for these products are available on the Xilinx support download center (under the Device Model tab) at: http://www.xilinx.com/support/download/index.htm Table 5-1:
Package

Thermal Resistance DataAll Devices


Package Body Size Devices LX4 JA (C/W) 58.5 58.5 36.9 38.4 38.4 32.2 32.2 30.6 31.9 30.2 26.8 30.5 27.8 26.2 26.2 22.6 22.6 JB (C/W) 18.6 18.6 17.1 26.7 26.7 17.4 17.4 15.6 22.7 20.1 16.6 18.0 13.7 12.5 12.5 8.8 8.8 JC (C/W) 8.8 8.8 7.8 12.5 12.5 10.6 10.6 9.4 10.0 8.6 6.8 10.6 8.9 7.1 7.1 5.3 5.3 JA (C/W) @ 250 LFM 49.9 49.9 31.5 33.1 33.1 26.7 26.7 27.1 26.9 25.2 21.9 26.2 22.5 20.9 20.9 17.3 17.3 JA (C/W) @ 500 LFM 46.7 46.7 29.3 31.5 31.5 25.1 25.1 23.5 25.3 23.6 20.3 24.7 21.1 19.4 19.4 15.9 15.9 JA (C/W) @ 750 LFM 44.9 44.9 28.2 30.6 30.6 24.2 24.2 22.7 24.4 22.8 19.5 23.9 20.0 18.6 18.6 15.1 15.1

CPG196

8x8

LX9 LX16

TQG144

20 x 20

LX4 LX9 LX4

CSG225

13 x 13

LX9 LX16 LX9

FT(G)256

17 x 17

LX16 LX25 LX9 LX16

CSG324

15 x 15

LX25 LX25T LX45 LX45T

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Table 5-1:
Package

Thermal Resistance DataAll Devices (Contd)


Package Body Size Devices LX25 LX25T LX45 LX45T JA (C/W) 21.0 21.0 19.1 19.1 17.2 17.2 16.4 16.4 15.8 15.8 20.3 20.3 18.5 18.5 17.6 17.6 17.0 17.0 17.6 15.9 15.9 15.0 15.0 14.4 14.4 15.0 14.2 14.2 JB (C/W) 13.4 13.4 10.0 10.0 8.0 8.0 7.0 7.0 6.3 6.3 9.1 9.1 7.4 7.4 6.5 6.5 5.9 5.9 9.6 7.5 7.5 6.6 6.6 6.0 6.0 7.3 6.5 6.5 JC (C/W) 8.1 8.1 6.0 6.0 4.7 4.7 4.2 4.2 3.7 3.7 3.9 3.9 2.9 2.9 2.5 2.5 2.2 2.2 5.9 4.5 4.5 4.0 4.0 3.5 3.5 4.4 3.8 3.8 JA (C/W) @ 250 LFM 17.2 17.2 14.3 14.3 12.5 12.5 11.7 11.7 11.1 11.1 15.5 15.5 13.7 13.7 12.9 12.9 12.2 12.2 14.5 11.6 11.6 11.0 11.0 10.2 10.2 10.8 10.0 10.0 JA (C/W) @ 500 LFM 15.9 15.9 13.0 13.0 11.3 11.3 10.5 10.5 9.9 9.9 14.4 14.4 12.4 12.4 11.6 11.6 10.9 10.9 12.2 10.5 10.5 9.6 9.6 9.7 9.7 9.7 8.9 8.9 JA (C/W) @ 750 LFM 15.2 15.2 12.4 12.4 10.6 10.6 9.8 9.8 9.3 9.3 13.8 13.8 11.7 11.7 11.0 11.0 10.3 10.3 11.6 9.9 9.9 9.1 9.1 8.5 8.5 9.1 8.5 8.5

FG(G)484

23 x 23

LX75 LX75T LX100 LX100T LX150 LX150T LX45 LX45T LX75

CS(G)484

19 x 19

LX75T LX100 LX100T LX150 LX150T LX45 LX75 LX75T

FG(G)676

27 x 27

LX100 LX100T LX150 LX150T LX100T

FG(G)900

31 x 31

LX150 LX150T

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Package Strategy
Cavity-Up Plastic BGA Packages
BGA is a plastic package technology that utilizes area array solder balls at the bottom of the package to make electrical contact with the system circuit board. The area array format of solder balls reduces package size considerably when compared to leaded products. It also results in improved electrical performance as well as having higher manufacturing yields. The substrate is made of a multilayer BT (bismaleimide triazene) epoxy-based material. Power and ground pins are grouped together and the signal pins are assigned in the perimeter format for ease of routing on to the board. The package is offered in a die up format and contains a wirebonded device that is covered with a mold compound.

Package Construction
X-Ref Target - Figure 5-1

Plastic Mold

Plated Copper Conductor

Soldermask

Thermal Vias

BT (PCB Laminate)

Solder Ball
UG385_c5_01_041009

Figure 5-1:

Cavity-Up Ball Grid Array Package

As shown in the cross section of Figure 5-1, the BGA package contains a wire bonded die on a single-core printed circuit board with an overmold. Beneath the die are the thermal vias which can dissipate the heat through a portion of the solder ball array and ultimately into the power and ground planes of the system circuit board. This thermal management technique provides better thermal dissipation than a standard PQFP package. Metal planes also distribute the heat across the entire package, enabling a 1520% decrease in thermal resistance to the case.

Key Features/Advantages of Cavity-Up BGA Packages


Low profile and small footprint Enhanced thermal performance Excellent board-level reliability

Chip Scale Packages


Chip Scale (CSP) packages meet the demands of miniaturization while offering improved performance. Applications for CSP packages are targeted to portable and consumer products where real estate is of utmost importance, miniaturization is key, and power consumption/dissipation must be low. By employing Spartan-6 FPGA CSP packages, system designers can dramatically reduce board real estate. Xilinx CSP packages are rigid BT-based substrates (see Figure 5-2).

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Support for Compact Thermal Models (CTM)

X-Ref Target - Figure 5-2

Die Attach

Molding Compond

IC BT Resin

Solder Ball

Solder Mask

Plated Via

UG385_c5_02_062209

Figure 5-2:

Rigid BT-Based Substrate CSP Packages

Key Features/Advantages of CSP Packages


An extremely small form factor which significantly reduces board real estate for such applications as portable and wireless designs and PC add-in cards Lower inductance and lower capacitance The absence of thin, fragile leads found on other packages A very thin, light-weight package

Support for Compact Thermal Models (CTM)


Table 5-1 provides the traditional thermal resistance data for Spartan-6 devices. These resistances are measured using a prescribed JEDEC standard that might not necessarily reflect the users actual board conditions and environment. The quoted JA and JC numbers are environmentally dependent, and JEDEC has traditionally recommended that these be used with that awareness. For more accurate junction temperature prediction, these might not be enough, and a system-level thermal simulation might be required. Though Xilinx continues to support these figure of merit data, for Spartan-6 FPGAs, boundary conditions independent compact thermal models (BCI-CTM) are also available to assist users in their thermal simulations. Two-resistor as well as eight to ten-resistor network models are offered for all Spartan-6 devices. These compact models seek to capture the thermal behavior of the packages more accurately at predetermined critical points (junction, case, top, leads, and so on) with the reduced set of nodes as illustrated in Figure 5-3. Unlike a full 3D model, these are computationally efficient and work well in an integrated system simulation environment. Delphi CTM models are available on the Xilinx support download center at: http://www.xilinx.com/support/download/index.htm.

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X-Ref Target - Figure 5-3

DELPHI BCI-CTM Topology for FCBGA


TI TO

Two Resistor Model

Rjc

Junction SIDE

Junction

Rjb

BI

BO

UG385_c05_03_021209

Figure 5-3: Thermal Model Topologies The CTM models are based on the DELPHI approach that JEDEC has proposed. Since the JEDEC neutral (XML) format proposal has not been adopted yet, the DELPHI approach is used to generate these files and the data saved in the NATIVE and proprietary file formats of the targeted CFD tools - rather than follow a neutral file format. The CTM libraries are available in Flotherm (PDML) format good for V5.1 and above and Icepack (version 4.2 and above) format.

Soldering Guidelines
To implement and control the production of surface-mount assemblies, the dynamics of the solder reflow process and how each element of the process is related to the end result must be thoroughly understood.
Note: Xilinx recommends that customers qualify their custom PCB assembly processes using package samples. UG112: Device Package User Guide contains further details on recommended assembly procedures.

The primary phases of the reflow process are: 1. 2. 3. Melting the particles in the solder paste Wetting the surfaces to be joined Solidifying the solder into a strong metallurgical bond

In a Pb-free soldering system, the sequences are the same. However, for the Pb-free soldering system, higher reflow temperature is applied. The peak reflow temperature of a plastic surface-mount component (PSMC) body should not be more than 220C for standard packages and 245260C for Pb-free packages (package size dependent). For multiple BGAs in a single board and because of surrounding component differences, Xilinx recommends checking all BGA sites for varying temperatures. The infrared reflow (IR) process is strongly dependent on equipment and loading. Components might overheat due to lack of thermal constraints. Unbalanced loading can lead to significant temperature variation on the board. These guidelines are intended to assist users in avoiding damage to the components; the actual profile should be determined by those using these guidelines. For complete information on package

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Soldering Guidelines

moisture / reflow classification and package reflow conditions, refer to the Joint IPC/JEDEC Standard J-STD-020C.

Sn/Pb Reflow Soldering


Figure 5-4 shows typical conditions for solder reflow processing of Sn/Pb soldering using IR/convection. Both IR and convection furnaces are used for BGA assembly. The moisture sensitivity of PSMCs must be verified prior to surface-mount flow.
X-Ref Target - Figure 5-4

TMAX (body) = 220C TMAX (leads) = 235C 24C/s

Temperature (C)

Ramp down 24C/s

T = 183C t183 Preheat & drying dwell 120180 s between 95180C (Note 3) (Note 2) 60s < t183< 120s applies to lead area

Time (s)
ug385_c5_04 _072711

Figure 5-4:

Typical Conditions for IR Reflow Soldering of Sn/Pb Solder

Notes for Figure 5-4:


1. 2. 3. 4. Maximum temperature range = 220C (body). Minimum temperature range before 205C (leads/balls). Preheat drying transition rate 24C/s Preheat dwell 95180C for 120180 seconds IR reflow must be performed on dry packages

Pb-Free Reflow Soldering


Xilinx uses a matte Sn lead finish for lead-frame packages and SnAgCu solder balls for BGA packages. In addition, suitable material are qualified for the higher reflow temperatures (245C260C) required by Pb-free soldering processes. Lead frame packages (TQG) from Xilinx are backwards compatible, that is the component can be soldered with Sn/Pb solder using a Sn/Pb soldering process. Lead-frame packages from Xilinx use a matte Sn plating on the leads which is compatible with Pb-free and Sn/Pb soldering alloys. Xilinx does not recommend soldering BGA packages (CPG, CSG, FTG, FGG) with SnPb solder using a Sn/Pb soldering process. Traditional Sn/Pb soldering processes have a peak reflow temperature of 220C. At this temperature range, the SnAgCu BGA solder balls do not properly melt and wet to the soldering surfaces. As a result, reliability and assembly yields can be compromised. The optimal profile must take into account the solder paste/flux used, the size of the board, the density of the components on the board, and the mix between large components and smaller, lighter components. Profiles should be established for all new board designs

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using thermocouples at multiple locations on the component. In addition, if there is a mixture of devices on the board, then the profile should be checked at various locations on the board. Ensure that the minimum reflow temperature is reached to reflow the larger components and at the same time, the temperature does not exceed the threshold temperature that might damage the smaller, heat sensitive components. Table 5-2 and Figure 5-5 provide guidelines for profiling Pb-free solder reflow. In general, a gradual, linear ramp into a spike has been shown by various sources to be the optimal reflow profile for Pb-free solders (Figure 5-5). This profile has been shown to yield better wetting and less thermal shock than conventional ramp-soak-spike profile for the Sn/Pb system. SnAgCu alloy reaches full liquidus temperature at 235C. When profiling, identify the possible locations of the coldest solder joints and ensure that those solder joints reach a minimum peak temperature of 235C for at least 10 seconds. It might not be necessary to ramp to peak temperatures of 260C and above. Reflowing at high peak temperatures of 260C and above can damage the heat sensitive components and cause the board to warp. Users should reference the latest IPC/JEDEC J-STD-020 standard for the allowable peak temperature on the component body. The allowable peak temperature on the component body is dependent on the size of the component. Refer to Table 5-2 for peak package reflow body temperature information. In any case, use a reflow profile with the lowest peak temperature possible. Table 5-2: Pb-Free Reflow Soldering Guidelines
Profile Feature Ramp-up rate Preheat Temperature 150200C Temperature maintained above 217C Convection, IR/Convection 3C/s maximum 60120 seconds 60150 seconds (6090 seconds typical)

Time within 5C of actual peak temperature 30 seconds maximum Peak Temperature (lead/ball) Peak Temperature (body) Ramp-down Rate Time 25C to Peak Temperature 235C minimum, 245C typical (depends on solder paste, board size, components mixture) 245C260C, package body size dependent (reference Table 5-3) 6C/s maximum 3.5 minutes minimum, 5.0 minutes typical, 8 minutes maximum

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Soldering Guidelines

X-Ref Target - Figure 5-5

Tbody (MAX) = 245260C (package type dependent) See Table 5-3 for maximum value for each package Tlead (MIN) = 235260C (10s minimum) Ramp down 6C/s max

Temperature (C)

217C t 217 Wetting time = 60150 s 150200C Ramp up 3C/s max Preheating 60120s

Time (s)

ug385_c5_05_081611

Figure 5-5:

Typical Conditions for Pb-Free Reflow Soldering

Table 5-3: Peak Package Reflow Body Temperature for Xilinx Pb-Free Packages (Based on J-STD-020 Standard)
Package Lead Frame TQFP BGA FTG256 BGA FGG484 FGG676 FGG900 CPG196 CSG225 CSG324 CSG484 260C 250C 3 3 TQG144 260C 3 Peak Package Reflow Body Temperature JEDEC Moisture Sensitivity Level (MSL)

Chip Scale

260C

For sophisticated boards with a substantial mix of large and small components, it is critical to minimize the T across the board (<10C) to minimize board warpage and thus, attain higher assembly yields. Minimizing the T is accomplished by using a slower rate in the warm-up and preheating stages. Xilinx recommends a heating rate of less than 1C/s during the preheating and soaking stages, in combination with a heating rate of not more than 3C/s throughout the rest of the profile. It is also important to minimize the temperature gradient on the component, between top surface and bottom side, especially during the cooling down phase. The key is to optimize cooling while maintaining a minimal temperature differential between the top surface of the package and the solder joint area. The temperature differential between the top surface of the component and the solder balls should be maintained at less than 7C during the critical region of the cooling phase of the reflow process. This critical region is in the part of the cooling phase where the balls are not completely solidified to the board yet, usually

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between the 200C217C range. To efficiently cool the parts, divide the cooling section into multiple zones, with each zone operating at different temperatures.

References
The following Xilinx links are to additional information on topics outlined in this chapter. UG394, Spartan-6 FPGA Power Management User Guide contains more information on power analysis and optimization. UG112, Device Package User Guide contains general information on Xilinx packaging. More information on Xilinx Pb-free solutions is available at: http://www.xilinx.com/system_resources/lead_free/index.htm. XAPP427: Implementation and Solder ReflowGuidelines for Pb-Free Packages provides further information on the Pb-free reflow process.

The following websites contain additional information on heat management and contact information. http://www.wakefield.com http://www.aavidthermalloy.com http://www.qats.com

Refer to the following websites for interface material sources: Henkel Electronics: http://www.henkel.com/electronics.htm Bergquist Company: http://www.bergquistcompany.com AOS Thermal Compound: http://www.aosco.com Chomerics: http://www.chomerics.com Kester: http://www.kester.com

Refer to the following websites for CFD tools Xilinx supports with thermal models. Mentor Graphics Flotherm: http://www.mentor.com/products/mechanical/flomerics ANSYS Icepak: http://www.ansys.com/Products/Simulation+Technology/Fluid+Dynamics/ANSY S+Icepak

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Chapter 6

Package Marking
The Spartan-6 devices in the TQ, CS, and FG packages have package top-markings similar to the example shown in Figure 6-1 and explained in Table 6-1. In BGA packages, the ball A1 indicator is in the top-left corner. In the TQG144 packages, the pin P1 indicator is in the bottom left of the mark.
X-Ref Target - Figure 6-1

Device Type Package

Speed Grade

XC6SLX16 CSG324xxxXXXX DxxxxxxxA 2C

TM

Date Code Lot Code

Operating Range

ug385_c6_01_012810

Figure 6-1: Table 6-1:


Item Xilinx Logo Family Brand Logo 1st Line 2nd Line

Spartan-6 Device Package Marking

Xilinx Device Marking DefinitionExample


Definition Xilinx logo, Xilinx name with trademark, and trademark-registered status. Spartan-6 family name with trademark and trademark-registered status. This line is optional and could appear blank. Device type. Package code, circuit design revision, the location code for the wafer fab, the geometry code, and date code. A G in the third letter of a package code indicates a Pb-free RoHS compliant package. For more details on Xilinx Pb-Free and RoHS Compliant Products, see: http://www.xilinx.com/pbfree.

3rd Line

Ten alphanumeric characters for Assembly and Lot information. The last digit is usually an A or an M.

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Table 6-1:
Item

Xilinx Device Marking DefinitionExample (Contd)


Definition Device speed grade and temperature range. If a grade is not marked on the package, the product is considered commercial grade. Other variations for the 4th line: L1C 2C-xxxx 2C-ES The L1C indicates a lower-power (1.0V core voltage) device with a -1L speed grade. The xxxx indicates the SCD for the device. An SCD is a special ordering code that is not always marked in the device top mark. An ES, when present, indicates an Engineering Sample.

4th Line

The Spartan-6 devices in the CPG196 package have package top-markings similar to the example shown in Figure 6-2 and explained in Table 6-2. The package markings are abbreviated.
X-Ref Target - Figure 6-2

6SLX16
Lot Code

Device Type

Axxxxx-xxxx xxxxxxxxxxx C7-xxx 2C

Date Code

Country of Origin

Package Code

Speed Grade

ug385_c6_02_100510

Figure 6-2: Table 6-2:


Item 1st Line 2nd Line 3rd Line 4th Line

Spartan-6 Device CPG196 Package Marking

Xilinx CPG196 Device Marking DefinitionExample


Definition Xilinx Logo, Device type. Abbreviated without the leading XC. Lot code and date code (abbreviated). Country of Origin Package code (C7 = CPG196), circuit design revision, the location code for the wafer fab, the geometry code, and the device speed grade and temperature (in this example: 2C). Other variations for the 4th line: L1C 2C ES An L1C indicates a lower-power (1.0V core voltage) device with a -1L speed grade. An ES, when present, indicates an Engineering Sample.

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Chapter 7

Density Migration
Introduction
Spartan-6 FPGA pinouts are 100% compatible across density in the same package and within the same set of LX or LXT devices. Designs implemented in a given device/package combination can be migrated up or down in density without changing a board layout. The guidelines in this chapter facilitate migration between Spartan-6 devices. For general information on pin planning, see the I/O Pin and Clock Planning chapter in UG393, Spartan-6 FPGA PCB Design and Pin Planning Guide.

Compatibility
A common layout for multiple devices using the same package is the goal of pinout compatibility. Generally, the only difference between densities is the number or placement of No Connects (NCs) within the package. In Spartan-6 FPGAs, all pins maintain their same names from one density to the next. However, there are some unique situations where pin names change because of differences in functionality from one density to the next, as explained in the Special Cases section. All Spartan-6 LX devices are pinout compatible in the same package, and all Spartan-6 LXT devices are pinout compatible in the same package. The Spartan-6 LX and Spartan-6 LXT devices are not pinout compatible in the same package due to the additional GTP transceiver pins in the LXT family. Although many of the other pins are in the same location, there can be significant differences between LX and LXT devices, and migration between devices requires a different board layout. Package compatibility refers only to changing densities within a common package. No compatibility between packages, even between packages with the same amount of pins, such as the FG(G)484 and the CS(G)484, is implied. However, a design using one package can be implemented in another package with a similar quality of results, since the pin locations are similar. The Spartan-6 LX devices and LXT devices use the same package designators for common packages, such as FG(G)484, even though the pinouts are different. There is no difference in pinout between the Pb-free packages and the leaded equivalent, such as the FGG484 and the FG484. The Spartan-6 FPGA pinouts are optimized for the unique Spartan-6 FPGA architecture. No compatibility is implied between the Spartan-6 FPGA pinouts and any other FPGA family.

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The Spartan-6 FPGA pinout compatibility is summarized in Table 7-1. Table 7-1: Pinout Compatibility Summary
Device Any LX device, any package Any LXT device, any package LX device Any device and package, Pb-free Any package Spartan-6 FPGA Device Any LX device, any package Any LXT device, any package LXT device Same device and package, Pb-equivalent Different package Other FPGAs Compatible? Yes Yes No Yes No No

No Connects
The primary difference between densities in the same package is the number or location of the No Connects (NCs). To make a board layout compatible, refer to Chapter 2, Pinout Tables and prohibit the use of any pin where a potential target density is shown in the NC column. Typically, the largest device in a package has zero No Connects and smaller devices add NCs as the size limits the amount of I/O available. In the Spartan-6 family, there are instances where a larger density has fewer I/O than the smaller device in the same package. Referring to Table 1-4, page 14 for example, the I/O available is less than for a smaller device for the LX25 and LX45 in the CSG324, the LX75 in the FG(G)484, and the LX75T in the CS(G)484 and FG(G)484. In these instances, the available I/O count in banks 0 and 2 (top and bottom) is reduced in the larger device. The I/O count per bank is shown in Table 1-5, page 15. No Connects can be in different locations in one density versus another. To create a compatible pinout across densities, all the potential NCs should be prohibited, which can result in fewer usable I/O than the number available in the device with the fewest I/O. For example, in the CS(G)484 package, out of the 338 I/O in the two largest devices (LX100 and LX150), the LX75 has 10 NCs (328 I/O) and the LX45 has 18 NCs (320 I/O). Since the NCs are on different pins, all 28 NCs are used to create a 310 I/O pinout that can be migrated between the LX45 and LX75. No Connects are almost always on single-purpose pins. Dual-purpose pins, including memory controller pins and configuration pins, are used consistently across all densities in a package. The only exception is the CSG225 package, because the LX4 does not include the memory controllers and does not support parallel configuration.

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No Connects

Table 7-2 and Table 7-3 show the number of I/Os to produce compatibility across various density ranges in a package. For all the ranges not noted, the pinout of the lowest I/O count device is compatible with the rest of the range. A design can simply be implemented in the device with the lowest I/O count and restricted to the same pinout if migrated to a device with more I/O. Table 7-2:
Package TQG144

I/O Count for Compatibility Across Density Ranges in LX the Family


I/O Count Total I/O Compatible I/O Total I/O Compatible I/O Total I/O 132 106 LX4 102 102 106 106 160 132 160 186 186 186 200 232 200 Compatible I/O 226 218 Total I/O 320 328 310(1) Compatible I/O 328 338 Total I/O 266 254(1) 316 280 326 338 338 338 226 218 186 160 106 LX9 102 LX16 LX25 LX45 LX75 LX100 LX150

CPG196

CSG225

Compatible I/O Total I/O Compatible I/O Total I/O

FT(G)256

CSG324

CS(G)484

FG(G)484

226(1) Compatible I/O 270(1) 280 326 Total I/O 358 408 324(1) Compatible I/O 408 480 480 498

FG(G)676

FG(G)900
Notes:

Total I/O

576

1. The compatible number of I/O is less than the number of I/O in the device with the lowest I/O count because NCs do not completely align with each other.

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Table 7-3:

I/O Count for Compatibility Across Density Ranges in the LXT Family
I/O Count Total I/O Compatible I/O Total I/O LX25T(1) 190 190 296 292 292 296 250 250 296 268 296 296 296 296 LX45T 190 LX75T LX100T LX150T

Package CSG324

CS(G)484

Compatible I/O Total I/O

FG(G)484

Compatible I/O

226(2) 268 296

Total I/O FG(G)676 Compatible I/O Total I/O Compatible I/O

348

376 348 376 498 498

396

FG(G)900
Notes:

540

1. The LX25T devices have NCs in place of one GTPA1_DUAL available in the larger devices. 2. The compatible number of I/O is less than the number of I/O in the device with the lowest I/O count because the NCs do not completely align with each other.

Special Cases
MCBs and Parallel Configuration in the LX4
The LX4 device does not support Memory Controller Blocks (MCBs) or parallel configuration modes. The same is true of all devices in the TQG144 and CPG196 packages, but in the CSG225 package the larger devices support these functions. Therefore, the names of several I/O on the LX4 are different than the LX9 and LX16 in the CSG225 because the dual function name is not included in the pin name. For example, pin B14 is IO_L1P_A25_1 in the LX9 and LX16 but IO_L1P_1 in the LX4. This name change does not affect its compatibility as an I/O pin.

GTP Transceiver Connections in the LX25T


The LX25T device, available in the CSG324 and FG(G)484 packages, has two GTP transceiver ports. The other LXT devices in these packages have four GTP transceiver ports. The two additional ports are left as No Connects in the LX25T in the CSG324 and FG(G)484 packages. Therefore, the LX25T has more NCs than is implied by the I/O count. For example, although the LX25T and LX45T have the same I/O count in the CSG324 package, the LX25T has 17 NCs while the LX45T has none.

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Special Cases

Encryption Pins
The LX75, LX100, LX150, LX75T, LX100T, and LX150T include three pins used for the bitstream encryption functionVFS, RFUSE, and VBATT. This function is not available in the smaller devices. To maintain compatibility with the larger devices, these pins are left as NCs in the smaller devices. For example, in packages that support both the LX45 or LX45T and the LX75 or LX75T, the LX45 and LX45T will have three NCs in addition to any NCs in place of I/O pins. In the larger devices, these encryption pins should be tied High or Low. However, they can be left floating for ease of migration. In the smaller devices, the encryption pins can treated as standard NCs, however, to allow for migration, avoid routing active signals through these NC pins. If there is a potential to add encryption and migrate the design to a larger devices, connect the pins in the smaller devices as they would be used for encryption.

MCBs and I/O Banks in the FG(G)676 and FG(G)900


The MCB associated I/O pins have a similar relative layout across multiple packages. A board layout for one package can be similar for a different package. The larger Spartan-6 devices (LX75/T, LX100/T, and LX150/T) have four MCBs in the larger packages, the FG(G)676 and FG(G)900. To support the extra MCBs, the two side banks 1 and 3 are split in half, with a bank 4 added to the top left and a bank 5 added to the top right (Figure 7-1).
X-Ref Target - Figure 7-1

BANK0 BANK4 BANK3 BANK1 BANK3 BANK2 LX4, LX9, LX16, LX25, LX25T, LX45, LX45T and all devices in the 484-pin packages

BANK0 BANK5

BANK1 BANK2

LX75, LX75T, LX100, LX100T, LX150, LX150T except devices in the 484-pin packages
ug385_c7_01_020910

Figure 7-1:

Spartan-6 FPGA I/O Bank Migration

In the LX devices, when migrating from the LX45 to the LX75 in the FG(G)676 package, the pinout designations change for some of the pins from bank 3 to bank 4, and for others from bank 1 to bank 5. In addition, many of these pins also add dual-purpose MCB names. For an FG(G)676 design to migrate (in either direction) between the LX45 and the LX75 or larger, restrict MCB use to banks 1 and 3. Treat bank 4 as an extension of bank 3, and treat bank 5 as an extension of bank 1, using the same VCCO and optional VREF voltages. Calculate SSO requirements independently for the 4-bank and 6-bank implementations. Also follow all I/O design rules for both implementations, including the restriction of two differential I/O standards per bank. When the LX75 and LX75T and larger devices are packaged in the 484-pin packages, only four banks are provided in the pinout. The device designs in this package should be for a 4-bank device, not a 6-bank device. Limiting to four banks allows migration between the LX45 and LX45T or smaller devices and the LX75 and LX75T and larger devices in the 484-pin packages.

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GTP Transceiver Banks


The GTP transceivers have a similar relative layout of their associated I/O and power pins across multiple packages. An effective board layout for one package can be used for a different package. The MGTREFCLK pins in the FG(G)484 package have the P side toward the outside of the package, while in all other packages and all other I/O the N side is toward the outside of the package.

LX25 and LX25T Migration


The pinouts for the LX25 and LX25T are compatible with the other Spartan-6 devices in the same packages. However, there are two unique characteristics to consider when migrating from the LX25 to other Spartan-6 LX devices or when migrating from the LX25T to other Spartan-6 LXT devices. The LX25 and LX25T do not support BPI configuration. For more details, see UG380, Spartan-6 FPGA Configuration User Guide. 12 pins in bank 1 and bank 3 of the LX25 and LX25T are associated with different BUFIO2 clocking regions for the other devices in the same package. This difference affects package migration when using the FT(G)256, CSG324, and FG(G)484 packages. For more information, see the notes in Table 2-6 through Table 2-10, and refer to the Clock Inputs section in UG382, Spartan-6 FPGA Clocking Resources User Guide.

Pin Names and Physical Pad Locations


In general, the same pin name will have the same location on the device across different packages. For example, the HSWAPEN pin is always in the top-left corner of the device and the I/O name is consistently IO_L1P_0. Pins with dual-purpose names, such as the MCB and configuration pins, always refer to the same specific pad location on the device. As a design migrates between densities in a package, these pins will connect to the same general area of the device, allowing the pinout to be maintained. However, some pins may connect to a different area of the device, either because of the different size of the FPGA array or because of different pad-to-package connections. When possible, when migrating between densities, allow the software to change the pin locations to optimize for the new target device.

Migrating Between Packages


Although general layout will be consistent between packages, there is no direct compatibility, even between the CS(G)484 and FG(G)484, to facilitate migration between packages. Pin names are generally maintained across packages, so a function locked to a particular pin name in one package should use the same I/O pad when migrated to a different package. However, some associations between pin names and physical pad locations can change. Either create new constraints for the new package, or use the software tools to verify that the same pad is being used.

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PlanAhead Software Tool

PlanAhead Software Tool


The PinAhead environment with the PlanAhead tool provides an interface to analyze the design and device I/O requirements and to define an I/O pinout configuration that satisfies the needs of both the PCB and FPGA designers. The PlanAhead software enables the creation of I/O port signals and can import an I/O port list in CSV, UCF, or HDL format. Using this tool allows for early and intelligent pinout definition and can eliminate some of the unnecessary pinout related changes that typically happen later in the design. The graphical tools make it easier to analyze possible pinouts across different options. The PinAhead environment consists of a split workspace showing both the package and device views. There are other views that provide additional I/O information: the clock region view, package pins view, and the I/O ports view. The package pins view table is categorized by I/O banks allowing easy cross selection and highlighting of I/O banks in both the device and package views. This clearly shows the relationship of the physical pin location and the I/O pad location on the device, which simplifies optimal I/O bank selection. Pin information for each pin in the I/O bank is displayed in the package pins view. For more information on the PlanAhead tool, see http://www.xilinx.com/tools/planahead.htm.

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