74LV125

Quad buffer/line driver; 3-state

Rev. 03 7 April 2009 Product data sheet

1. General description
The 74LV125 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC125 and 74HCT125. The 74LV125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state.

2. Features
I I I I I Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 C I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Multiple package options I Specied from 40 C to +85 C and from 40 C to +125 C

3. Ordering information
Table 1. Ordering information Package Temperature range 74LV125N 74LV125D 74LV125DB 74LV125PW 40 C to +125 C 40 C to +125 C 40 C to +125 C 40 C to +125 C Name DIP14 SO14 SSOP14 TSSOP14 Description plastic dual in-line package; 14 leads (300 mil) plastic small outline package; 14 leads; body width 3.9 mm plastic shrink small outline package; 14 leads; body width 5.3 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT27-1 SOT108-1 SOT337-1 SOT402-1 Type number

NXP Semiconductors

74LV125
Quad buffer/line driver; 3-state

4. Functional diagram

2 1 5 4 9 10 12 13

1A 1OE 2A 2OE

1Y

3 2 1

2Y

1 5

EN1
6

4 3A 3OE 4A 4OE
mna228

3Y

8
9 8 10

4Y

11

12 11 13

nA

nY

nOE
mna229 mna227

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram (one buffer)

5. Pinning information
5.1 Pinning
74LV125
1OE 1A 1Y 2OE 2A 2Y GND 1 2 3 4 5 6 7
001aaj961

14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 8 3A 3Y 1OE 1A 1Y 2OE 2A 2Y GND 1 2 3 4 5 6 7

001aaj921

74LV125
14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 8 3A 3Y

Fig 4.

Pin conguration DIP14, SO14

Fig 5.

Pin conguration SSOP14, TSSOP14

74LV125_3

NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 7 April 2009

2 of 15

NXP Semiconductors

74LV125
Quad buffer/line driver; 3-state

5.2 Pin description

Table 2. Symbol 1OE, 2OE, 3OE, 4OE, 1A, 2A, 3A, 4A 1Y, 2Y, 3Y, 4Y GND VCC Pin description Pin 1, 4, 10, 13 2, 5, 9, 12 3, 6, 8, 11 7 14 Description output enable input (active LOW) data input data output ground (0 V) supply voltage

6. Functional description
Table 3. Control nOE L L H
[1]

Function table[1] Input nA L H X Output nY L H Z

H = HIGH voltage level; L = LOW voltage level; X = dont care; Z = high-impedance OFF-state.

7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Tamb = 40 C to +125 C DIP14 SO14, SSOP14, TSSOP14
[1] [2]
[2]

Conditions VI < 0.5 V or VI > VCC + 0.5 V VO < 0.5 V or VO > VCC + 0.5 V VO = 0.5 V to (VCC + 0.5 V)
[1] [1]

Min 0.5 70 65 -

Max +7.0 20 50 35 70 +150 750 500

Unit V mA mA mA mA mA C mW mW

The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For DIP14 packages: above 70 C the value of Ptot derates linearly with 12 mW/K. For SO14 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. For (T)SSOP14 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.

74LV125_3

NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 7 April 2009

3 of 15

NXP Semiconductors

74LV125
Quad buffer/line driver; 3-state

8. Recommended operating conditions

Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO Tamb t/V Parameter supply voltage[1] input voltage output voltage ambient temperature input transition rise and fall rate VCC = 1.0 V to 2.0 V VCC = 2.0 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 5.5 V
[1]

Conditions

Min 1.0 0 0 40 -

Typ 3.3 +25 -

Max 5.5 VCC VCC +125 500 200 100 50

Unit V V V C ns/V ns/V ns/V ns/V

The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC).

9. Static characteristics
Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOH HIGH-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.2 V IO = 100 A; VCC = 2.0 V IO = 100 A; VCC = 2.7 V IO = 100 A; VCC = 3.0 V IO = 100 A; VCC = 4.5 V IO = 8 mA; VCC = 3.0 V IO = 16 mA; VCC = 4.5 V 1.8 2.5 2.8 4.3 2.4 3.6 1.2 2.0 2.7 3.0 4.5 2.82 4.2 1.8 2.5 2.8 4.3 2.2 3.5 V V V V V V V 40 C to +85 C Min 0.9 1.4 2.0 0.7VCC Typ[1] Max 0.3 0.6 0.8 0.3VCC 40 C to +125 C Unit Min 0.9 1.4 2.0 0.7VCC Max 0.3 0.6 0.8 V V V V V V V

0.3VCC V

74LV125_3

NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 7 April 2009

4 of 15

NXP Semiconductors

74LV125
Quad buffer/line driver; 3-state

Table 6. Static characteristics continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-level output voltage Conditions VI = VIH or VIL IO = 100 A; VCC = 1.2 V IO = 100 A; VCC = 2.0 V IO = 100 A; VCC = 2.7 V IO = 100 A; VCC = 3.0 V IO = 100 A; VCC = 4.5 V IO = 8 mA; VCC = 3.0 V IO = 16 mA; VCC = 4.5 V II IOZ input leakage current OFF-state output current VI = VCC or GND; VCC = 5.5 V VI = VIH or VIL; VO = VCC or GND; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V per input; VI = VCC 0.6 V; VCC = 2.7 V to 3.6 V 0 0 0 0 0 0.20 0.35 0.2 0.2 0.2 0.2 0.40 0.55 1.0 5 0.2 0.2 0.2 0.2 0.50 0.65 1.0 10 V V V V V V V A A 40 C to +85 C Min Typ[1] Max 40 C to +125 C Unit Min Max

ICC ICC CI
[1]

supply current additional supply current input capacitance

3.5

20 500 -

160 850 -

A A pF

Typical values are measured at Tamb = 25 C.

10. Dynamic characteristics

Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol Parameter tpd propagation delay Conditions nA to nY; see Figure 6 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V; CL = 15 pF VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V ten enable time nOE to nY; see Figure 7 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V
[3] [2] [3] [3] [2]

40 C to +85 C Min Typ[1] 55 19 14 9 10 75 26 19 14 Max 24 18 14 12 31 23 18 15

40 C to +125 C Min Max 31 23 18 15 39 29 23 19

Unit

ns ns ns ns ns ns ns ns ns ns ns

74LV125_3

NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 7 April 2009

5 of 15

NXP Semiconductors

74LV125
Quad buffer/line driver; 3-state

Table 7. Dynamic characteristics continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol Parameter tdis disable time Conditions nOE to nY; see Figure 7 VCC = 1.2 V VCC = 2.0 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD power dissipation capacitance CL = 50 pF; fi = 1 MHz; VI = GND to VCC; VCC = 3.3 V
[4] [3] [2]

40 C to +85 C Min Typ[1] 65 24 18 14 22 Max 32 24 20 17 -

40 C to +125 C Min Max 39 29 24 21 -

Unit

ns ns ns ns ns pF

[1] [2]

All typical values are measured at Tamb = 25 C. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. Typical values are measured at nominal supply voltage (VCC = 3.3 V). CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fI = input frequency in MHz, fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL VCC2 fo) = sum of the outputs.

[3] [4]

11. Waveforms
VI nA input GND

VM

tPHL VOH
nY output VOL

tPLH

VM
mna230

Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load.

Fig 6.

The input (nA) to output (nY) propagation delays

74LV125_3

NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 7 April 2009

6 of 15

NXP Semiconductors

74LV125
Quad buffer/line driver; 3-state

VI nOE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM VM VX tPZH tPZL VM

outputs disabled

outputs enabled
mna362

Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load.

Fig 7. Table 8. VCC < 2.7 V

Enable and disable times Measurement points Input VM 0.5VCC 1.5 V 0.5VCC Output VM 0.5VCC 1.5 V 0.5VCC VX VOL + 0.1VCC VOL + 0.3 V VOL + 0.1VCC VY VOH 0.1VCC VOH 0.3 V VOH 0.1VCC

Supply voltage

2.7 V to 3.6 V 4.5 V

74LV125_3

NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 7 April 2009

7 of 15

NXP Semiconductors

74LV125
Quad buffer/line driver; 3-state

VI negative pulse 0V

tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW
VEXT VCC VI VO
RL

VM

VI positive pulse 0V

VM

G
RT

DUT
CL RL

001aae331

Test data is given in Table 9. Denitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times.

Fig 8. Load circuit for measuring switching times Table 9. VCC < 2.7 V 2.7 V to 3.6 V 4.5 V Test data Input VI VCC 2.7 V VCC tr, tf 2.5 ns 2.5 ns 2.5 ns Load CL 50 pF 15 pF, 50 pF 50 pF RL 1 k 1 k 1 k VEXT tPHL, tPLH open open open tPZH, tPHZ GND GND GND tPZL, tPLZ 2VCC 2VCC 2VCC

Supply voltage

74LV125_3

NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 7 April 2009

8 of 15

NXP Semiconductors

74LV125
Quad buffer/line driver; 3-state

12. Package outline

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

D seating plane

ME

A2

A1

c Z e b1 b 14 8 MH w M (e 1)

pin 1 index E

5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.13 0.068 0.044 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087

Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION

ISSUE DATE 99-12-27 03-02-13

Fig 9.
74LV125_3

Package outline SOT27-1 (DIP14)

NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 7 April 2009

9 of 15

NXP Semiconductors

74LV125
Quad buffer/line driver; 3-state

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

A X

c y HE v M A

Z 14 8

Q A2 pin 1 index Lp 1 e bp 7 w M L detail X A1 (A 3) A

2.5 scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3

0.010 0.057 inches 0.069 0.004 0.049

0.019 0.0100 0.35 0.014 0.0075 0.34

0.244 0.039 0.041 0.228 0.016

0.028 0.004 0.012

8 o 0

Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION

ISSUE DATE 99-12-27 03-02-19

Fig 10. Package outline SOT108-1 (SO14)

74LV125_3 NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 7 April 2009

10 of 15

NXP Semiconductors

74LV125
Quad buffer/line driver; 3-state

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm

SOT337-1

A X

c y HE v M A

Z 14 8

Q A2 A1 pin 1 index Lp L 1 bp 7 w M detail X (A 3) A

2.5 scale

5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 8 o 0
o

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION

ISSUE DATE 99-12-27 03-02-19

Fig 11. Package outline SOT337-1 (SSOP14)

74LV125_3 NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 7 April 2009

11 of 15

NXP Semiconductors

74LV125
Quad buffer/line driver; 3-state

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm

SOT402-1

c y HE v M A

14

Q A2 pin 1 index A1 Lp L (A 3) A

1
e bp

7
w M detail X

2.5 scale

5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 o 0
o

Fig 12. Package outline SOT402-1 (TSSOP14)

74LV125_3 NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 7 April 2009

12 of 15

NXP Semiconductors

74LV125
Quad buffer/line driver; 3-state

13. Abbreviations
Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic

14. Revision history

Table 11. 74LV125_3 Modications: Revision history Release date 20090407 Data sheet status Product data sheet Change notice Supersedes 74LV125_2 Document ID

The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name when appropriate. Product specication Product specication 74LV125_1 -

74LV125_2 74LV125_1

19980428 19970203

74LV125_3

NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 7 April 2009

13 of 15

NXP Semiconductors

74LV125
Quad buffer/line driver; 3-state

15. Legal information

15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]

Product status[3] Development Qualication Production

Denition This document contains data from the objective specication for product development. This document contains data from the preliminary specication. This document contains the product specication.

Please consult the most recently issued document before initiating or completing a design. The term short data sheet is explained in section Denitions. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

15.2 Denitions
Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofce. In case of any inconsistency or conict with the short data sheet, the full data sheet shall prevail.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specied use without further testing or modication. Limiting values Stress above one or more limiting values (as dened in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/prole/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

15.3 Disclaimers
General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental

15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nxp.com For sales ofce addresses, please send an email to: salesaddresses@nxp.com

74LV125_3

NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 7 April 2009

14 of 15

NXP Semiconductors

74LV125
Quad buffer/line driver; 3-state

17. Contents
1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information.

NXP B.V. 2009.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 April 2009 Document identifier: 74LV125_3