Analog & Digital VLSI Design Analog Assignment

March 10, 2011

1. OBJECTIVE:
To get you over the real world Analog Design. To give you an exposure on Layout. To develop your intuition for designing, i.e. selection of topology, biasing scheme, simulation techniques, interpretation of results/ graphs etc.. You should be able to determine how and which of the transistors sizes (W/L) in the circuit will affect which parameters (specs). Using EDA tools efficiently in system design

2. COMMON INSTRUCTION
The instructions given here will need to be followed by all students. Please note that failure to do the same will result in a penalty of marks. The assignment has to be done in a group of two students. A total of 26 assignments are listed below so every group has to pick up one assignment. You have to use Cadence Schematic editor to draw your circuit. For simulation you are free to use any of the two simulators: Spectre and Eldo. Everyone has to draw the layout (OpAmp only), extract the netlist and again simulate it to verify the performance. Your design should meet all the specifications, both before drawing layout and post layout. It is generally advised to overestimate your specs by around 25% at the schematic level to account for parasitic that result after the layout. If you are not able to meet your specs, you can go ahead, but you need to explain why it has happened at the time of demonstration and in report. You have to design your circuit using gm/Id methodology only. Validate your design for all process corners and temperatures 0, 27 and 100 :C.

 Library for circuit simulation; edatools/dk/tsmcmm018/6m/models/spectre/rf018.scs with Sections TT_3V, FF_3V, SS_3V , SF_3V , FS_3V edatools/dk/tsmcmm018/6m/models/eldo/rf018.eldo TT_3V, FF_3V, SS_3V Use Model names pch3 for PMOS and nch3 for NMOS, unless otherwise specified. Min. channel length that can be used is 0.35u For models nch/pch used TT, FF, SS, SF and FS sections in place of TT_3v, etc. All device dimensions (Ws and Ls) used must be whole number microns. Use Supply voltage of 3.3 V +/- 10% with a series resistance of 50 ohms (why?), unless
otherwise stated.

Power dissipation must be less than or equal to 3mW unless stated otherwise. Unless otherwise specified, load cap for all the systems is 200f F. You can use capacitors ranging from 50f F to 10n F in your design. Capacitors used within the OpAmp must be simulated and laid out using MOSFETs. All current sources have a temperature coefficient () of 0.003/ :C. Current sink means that one of the nodes is connected to ground and current source
means that one of the nodes is connected to the supply.

The suggested topologies are to be used unless there is a valid reason not to do the same. OTA stands for Operational Transconductance Amplifier, which is basically an OpAmp
with high output resistance.

All OpAmps/OTAs used feedback must be compensated for a phase margin of about
50: to 60:, unless your application requires it to be some other value.

The worst case analysis (.WCASE) and the Monte Carlo analysis (.MC) must be performed to verify practicality of the design.

1. RC Phase-Shift Oscillator Generate a 1 MHz signal Settling time = 50us for sustained oscillations THD <= 1% Oscillations of amplitude 1.5V Power Dissipation <=1mW Current Source of 5uA

Suggested Topology: 2-stage OTA

2. RC Phase-Shift Oscillator Generate a 1MHz signal Settling time = 80us THD <= 2% Rmax = 20k (Max resistance that can be used in the design) Current Sink of 5uA

Suggested Topology: 3-stage OTA with Rail-Rail swing

3. Triangular Wave Generator Freq = 100 kHz Amplitude = 2.0 V p2p Current Sink of 10uA

Suggested Topology: 3-stage OpAmp

4. Astable Multivibrator Duty Cycle = 20% Amplitude = 1.5V p2p Frequency of vibration = 100 MHz No Current Sink/Source available

Suggested Topology: pMOS folded Cascode

5. Fully-Differential Switched-Capacitor Integrator Input frequency = 50 kHz Current Sink of 6uA is available. Vout,CM = 1.5V Output Differential Swing = 5.5V

Suggested Topology: 2-stage Fully-Differential OTA

6. Parasitic - Insensitive Switched-Capacitor integrator Input frequency = 1 MHz Non-linearity <= 1% Current Sink of 1uA is available. Input Range: 0 to 3.3V

Suggested Topology: 2-stage OTA with mirroring in the 2nd stage

7. Fully-Differential Amplifier Gain = 500 V/V Rin >= 100 Mohms, Rout <= 1Kohm Gain error <= 0.01 % Signal frequency = 300 kHz Input Range: 1.4V to 3.3V Suggested Topology: nMOS Folded Cascode OpAmp followed by source follower Current Source of 4uA is available.

8. Analog Computation Solve the following equation: y + 9y = 0 , y(0) and y(0) will be given Accuracy of solution = 0.5% 500 KSamples/s Capacitors should be charged to their initial values through a switching ckt. Current Source of 20u is available.

Suggested Topology: 3-stage pMOS OpAmp

9. Analog Computation Solve the following equation: y 9y = 0 , y(0) = 1, y(0) = 0 100 KSamples/s Accuracy of Solution = 1% Current Sink of 15u is available.

Suggested Topology: 2-stage Fully Differential OTA

10. Current Reference Generate Current Sink Iref = 10uA +/- 10% Rout >= 1M ohm No Current Sink/Source available Maximum Length of transistors, lmax = 0.5um Voltage Headroom <= 0.5 V

Use the following topology for the OpAmp:

11. Current Reference Generate Current Source Iref = 10uA +/-20% Rout >= 100G ohm (Can be obtained through Gain Boosting) Suggested Topology: Single Stage nMOS Differential Amplifier No Current Sink/Source available

12. Log-Amplifier Input signal frequency = 50 kHz Input amplitude = 2V p2p P.M. of OpAmp = 80 degrees Current Source of 6uA is available.

Suggested Topology: Cascode DiffAmp with Source Follower

13. Antilog-Amplifier Signal frequency = 500kHz Signal Amplitude = 0.2V p2p, DC Level = 1V Power Dissipation <= 0.8mW Load Cap = 200p Rmax = 20k ohms models nch/pch to be used Current Sink of 15u is available.

Suggested Topology: 2-stage OTA with low output resistance

14. Half-wave Rectifier Rin >= 100MHz I/p varies from 0 to 2V I/p frequency = 100 kHz models pch/nch to be used. Current Source of 15u is available.

Suggested Topology: 3-stage pMOS-input OpAmp

15. Full-wave Rectifier I/p signal frequency = 50Hz Power Consumption <= 75uW Gain error <= 0.01% Input varies from 1V to 3V Current Source of 1.5u is available.

Suggested Topology: 3-stage nMOS-input OpAmp

16. Wien-Bridge Oscillator Freq = 800 kHz THD <= 2% Current Sink of 12u

Suggested Topology : Folded Cascode with Rail to Rail ICMR

17. Wien-Bridge Oscillator Freq = 5 kHz THD <= 1.5% Power Dissipation <= 100uW Oscillation Amplitude = 1.4V Current Source of 500 nA is available.

Suggested Topology : 2-stage OTA with Rail to Rail ICMR

18. 2nd Order Band-reject filter fo = 5 kHz Rejection Bandwidth = 500 Hz Non-linearity <= 0.005% Current Sink of 12uA is available.

Suggested Topology: 2-Stage OTA (pMOS Differential Amplifier with pMOS Cascode).

19. Current Feedback Operational Amplifier 3-dB frequeny >= 50 MHz Output Swing >= 2.4V Voltage gain >= 40 V/V Current Source of 2uA is available.

20. Bandgap Voltage Reference Vref = 1.2V +/- 1.2mV Corner = TT Use any nMOS diffamp Power supply has a 50mV noise at 500MHz frequency Current Sink of 5uA (=0.1/:C) is available.

21. Low-voltage reference Vref = 0.8V +/- 1mV across 0 to 100 Celcius and Vdd = 1.8 +/- 10% corner = TT No Current Sink/Source available Use any pMOS diffamp Current Source of 100nA(=0.1/:C) is available Power supply has a 50mV noise at 800MHz frequency.

22. 4-bit DAC R-2R Ladder Implementation 500 KSamples/s 1111 should correspond to 1 V 0000 should correspond to 3.2 V Error <= 1% Suggested Topology : pMOS Cascode with source follower Current source of 4uA is available. Only 10kohm resistors are available.

23. 3-bit Flash ADC Power Dissipation <= 5mW 3V corresponds to 111 and 0.3V corresponds to 000 Use any comparator with hysteresis of about 50mV 10 MSamples/s

24. Voltage Squarer I/p range: 0 to 2V Signal Frequency = 1MHz Current Sink of 8uA is available

Suggested Topology: Fully-Differential nMOS Amplifier followed by pMOS DiffAmp

25. Fully Differential OTA O/p Differential Swing = 5V Low Freq Differential Gain = 120 dB UGB >= 500kHz CMRR >= 180 dB ICMR: 0-2.5 Volts Vout,CM = 1.6V PSRR >= 180 dB Use the OTA in the following system for a gain of 50 V/V

Suggested topology for the OTA:

26. Low-power OTA Power Dissipation <= 2.5 uW Vdd = 1.2V +/- 120mV with series resistance of 50 ohms Gain = 10 V/V I/p frequency = 100 Hz I/p amplitude = 40mV Gain error <= 0.1% Current Source of 0.5uA.

Suggested Topology:

27. unity gain buffer Design a CMOS OPAMP with a bandwidth of 1MHz, a phase margin of 600, a gain of 1500 V/V. Results to be submitted--(a) Analog schematic for OPAMP. (b) Analysis of all equations for OPAMP, with a systematic derivation of all transistors W/L ratios.( Do not use hit-an-trial method) (c) What is the settling time for this OPAMP? (d) Spectre simulation of circuit schematic for OPAMP. (e) Cadence layout for OPAMP (f) Spectre simulation of circuit extracted from the layout. (g) Calculate the following parameters for your OPAMP: DC gain, Bode plot for AC gain and phase, CMRR plot, PSRR plot, slew rate, input and output voltage ranges, power consumption, and input referred offset voltage. (h) Configure your opamp to function as a unity-gain buffer. Characterize unity-gain buffer design for maximum bandwidth possible.

Ques 28. Design a differential output Folded Cascode OTA.

a) Analog schematic for OTA b) Analysis of all equations for OTA, with a systematic derivative of all transistors W/L ratios and spectre simulation of circuit for the following specifications. i) DC Gain 70 dB ii) UGB 500 MHz iii) Phase margin 600 - 650 iv) Slew rate 100 V/s v) CMRR 90dB vi) PSRR 40dB vii) Power Consumption 0.8mW c) Cadence layout for OPAMP d) Spectre simulation of circuit extracted from the layout. e) Configure your opamp to function as a unity-gain buffer. Characterize unity-gain buffer design for maximum bandwidth possible. Cc Ques 29. Design a CMOS OPAMP.

Biasing circuitry

Vin

A1

-A2

1 Buffer stage

Vout

Differential stage

Gain stage

a) Analog schematic for the above model b) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios and spectre simulation of circuit for the following specifications. i) UGB 800 MHz ii) Phase margin 650 iii) Slew rate 200 V/s c) What is the settling time for this OPAMP? d) e) f) Cadence layout for OPAMP Spectre simulation of circuit extracted from the layout. Also calculate the following parameters for your OPAMP: DC gain, Bode plot for AC gain and phase, CMRR plot, PSRR plot, input and output voltage ranges, power consumption, and input referred offset voltage.

g) Configure your opamp to function as a unity-gain buffer. Characterize unity-gain buffer design for maximum bandwidth possible.

Ques 30. Design a telescopic OPAMP given in figure 9.8(a) of Razavi:

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios and spectre simulation of circuit for the following specifications. i) Open loop gain (DC gain) 90 dB ii) UGB 500 MHz b) What is the input offset voltage for this opamp? c) Use AC analysis to measure low-frequency gain and phase margin of the opamp. Does the low-frequency gain agree with the DC gain? d) Cadence layout for OPAMP e) Spectre simulation of the circuit extracted from the layout f) Also calculate the following parameters for your OPAMP: CMRR plot, PSRR plot, slew rate, input and output voltage ranges and power consumption. g) Configure your opamp to function as a unity-gain buffer. Characterize unity-gain buffer design for maximum bandwidth possible.

Ques 31. Design a fully differential folded Cascode single stage opamp as shown below

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

b) c) d) e) f)

g)

and spectre simulation of circuit for the following specifications. i) Open loop gain(DC gain) 70 dB ii) UGB 300 MHz iii) Phase margin 550 Show a biasing circuitry to bias all the voltages in your design (except the input). What is the settling time for this OPAMP? Cadence layout for OPAMP Spectre simulation of the circuit extracted from the layout Also calculate the following parameters for your OPAMP: CMRR plot, PSRR plot, Bode plot for AC gain, slew rate, input and output voltage ranges, input offset voltage and power consumption. Configure your opamp to function as a unity-gain buffer. Characterize unity-gain buffer design for maximum bandwidth possible.

Ques 32. Design a telescopic opamp as shown in figure below

a)

Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios and spectre simulation of circuit for the following specifications. i) Open loop gain(DC gain) 80 dB ii) UGB 300 MHz

iii) Output voltage swing 3V Show a biasing circuitry to bias all the voltages in your design (except the input). c) What is the settling time for this OPAMP? d) Cadence layout for OPAMP e) Spectre simulation of the circuit extracted from the layout f) Also calculate the following parameters for your OPAMP: CMRR plot, PSRR plot, Bode plot for AC gain and phase margin, slew rate, ICMR, input offset voltage and power consumption. g) Configure your opamp to function as a unity-gain buffer. Characterize unity-gain buffer design for maximum bandwidth possible. b)

Ques 33. To achieve high swing in telescopic opamp a student removed the tail current source but at cost of common-mode rejection and power-supply rejection.

a) b)

Design a high swing telescopic opamp. Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios and spectre simulation of circuit for the following specifications.

i) ii)

Open loop gain(DC gain) 75 dB UGB 600 MHz

iii) Output voltage swing 4V iv) v) c) d) e) f) g) h) CMRR 90 dB PSRR 100 dB

Show a biasing circuitry to bias all the voltages in your design (except the input). What is the input offset voltage for this opamp? Cadence layout for OPAMP Spectre simulation of the circuit extracted from the layout Also calculate the following parameters for your OPAMP: Bode plot for AC gain and phase margin, slew rate, ICMR and power consumption. Configure your opamp to function as a unity-gain buffer. Characterize unity-gain buffer design for maximum bandwidth possible.

Ques 34. Design a fully differential two stage OPAMP (Telescopic + gain stage) for the following specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios and spectre simulation of circuit for the following specifications. i) ii) iii) iv) v) vi) b) c) d) e) f) DC gain 80 dB UGB 300 MHz Phase margin 500 Output voltage swing 3V 3 dB frequency 6 KHz CMRR 100dB

Show a biasing circuitry to bias all the voltages in your design (except the input). What is the input offset voltage for this opamp? Cadence layout for OPAMP Spectre simulation of the circuit extracted from the layout Also calculate the following parameters for your OPAMP: PSRR plot, Bode plot for AC gain and phase margin, slew rate, settling time, ICMR and power consumption.

g) Configure your opamp to function as a as an integrator. Characterize as an integrator as an integrator design for maximum bandwidth possible. . (Can choose any value of capacitor and resistor)

Ques 35. Design a fully differential two stage OPAMP (Telescopic + gain stage) for the following specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios and spectre simulation of circuit for the following specifications. i) ii) iii) iv) v) vi) b) c) d) e) f) UGB 500 MHz Phase margin 650 Slew rate 20V/ns Settling time 20ns PSRR 120dB Power dissipation 5mW

Show a biasing circuitry to bias all the voltages in your design (except the input). What is the input offset voltage for this opamp? Cadence layout for OPAMP Spectre simulation of the circuit extracted from the layout Also calculate the following parameters for your OPAMP: CMRR plot, Bode plot for AC gain and phase margin, DC gain and ICMR.

g) Configure your opamp to function as a unity-gain buffer. Characterize unity-gain buffer design for maximum bandwidth possible.

Ques 36. Design a fully differential two stage OPAMP (Telescopic + gain stage) for the following specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios and spectre simulation of circuit for the following specifications. i) ii) UGB 800 MHz Phase margin 600

iii) iv) vi) b) c) d) e) f)

Slew rate 50V/ns DC gain 100dB ICMR 0.9V to 2.2V

Show a biasing circuitry to bias all the voltages in your design (except the input). What is the input offset voltage for this opamp? Cadence layout for OPAMP Spectre simulation of the circuit extracted from the layout Also calculate the following parameters for your OPAMP: CMRR plot, Bode plot for AC gain and phase margin, and power dissipation. Measure the closed loop gain of your OPAMP in inverting amplifier of gain 10. (Can choose any values of Rf and Rin)

g)

Ques 37. Design a two-stage CMOS OPAMP as shown in figure below

a)

Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios and spectre simulation of circuit for the following specifications. i) Open loop gain(DC gain) 90 dB ii) UGB 300 MHz iii) Phase margin 550 iv) Output Swing 4.5V Show a biasing circuitry to bias all the voltages in your design (except the input). What is the settling time for this OPAMP? Cadence layout for OPAMP Spectre simulation of the circuit extracted from the layout Also calculate the following parameters for your OPAMP: CMRR plot, PSRR plot, Bode plot for AC gain, slew rate, ICMR, input offset voltage and power consumption.

b)

c) d) e) f)

g) Configure your opamp to function as a differentiator.. Characterize differentiator design for maximum bandwidth possible.

2, 37. RC Phase-Shift Oscillator Generate a 5MHz signal Settling time = 50us THD <= 2% Rmax = 50k (Max resistance that can be used in the design) Current Sink of 5uA

Suggested Topology: 3-stage OTA with Rail-Rail swing

3.

Report Format

Every group has to submit a report in the following format: Page 0: This will be the cover page and should include the choice of assignment, your name(s) and id number(s) and your tutorial instructors name. Page 1: Give circuit diagram and the design specs only. Page 2: Calculations/Graph Readings (for calculation you can use maximum of 3 pages). Page 3: Schematic and Layout Simulations at all corners in a single table. Page 4: Graph for DC Analysis, AC Analysis, Transient Analysis or any other if you have done. Page 5: Noise Simulation result. Page 6: Any other simulation results that you feel are pertinent to your design. Page 7: Conclusions and Explanation (if you haven't been able to meet any specs. or not following the guidelines). For OpAmps/OTAs the following performance metrics must be reported: Differential Low Frequency Gain Unity Gain Bandwidth, Phase Margin, Gain Margin Power Dissipation 3-db Bandwidth CMRR vs frequency PSRR vs frequency ICMR, OCMR, Output Swing Step response in Unity Feedback Configuration

For current and voltage reference, the results must be reported across all PVT variations. You should also submit a soft copy of DETAILED report of your assignment to IC on 5th April 2011.