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Presented by:
David Divins
Senior Staff Field Applications Engineer
International Rectifier
ddivins1@irf.com
Agenda
Package Die
Applications
Solenoid drivers
Motor drive
Lighting ballast
DC/DC converters
Switch model power supplies
Class D amplifiers
Simulation Tools and Methods
Method
Implementing model in the hardware description
language
Implementing model using equations and macro
modeling
library ieee; use ieee.std_logic_1164.all;
use ieee.electrical_systems.all;
V
+
entity comparator is Vds
port ( terminal a : electrical;
signal d : out std_ulogic ); A
+
end entity comparator; Source V dr Drain
Id
---------------------------------------------------------------- vs. 10
Vgs irfr9024
10
+
Rdson V
constant ref_voltage : real := 5.0; Equations
10
quantity vin across a; 10
Vdst EQU
begin PWR
FCT_ABS1 Tj
10 601.26m K/W 2.01 K/W
117.73m K/W
comparator_behavior : process is dr
RTH3
begin
if vin > ref_voltage / 2.0 then
PWR Abs H
RTH1 RTH2
d <= '1' after 5 ns; Probe 1.38m Ws/K Θ
else CTH3
H1 211.98u Ws/K
d <= '0' after 5 ns; CTH2 32.33m Ws/K T1 Ta aC
end if; PWR
wait on vin'above(ref_voltage / 2.0); CTH1
end process comparator_behavior;
Thermometer Voltmeter
Heat Ammeter
Methods of Estimating Die Temperature
Temperature
Rise Calculated Case
Ambient
Junction Case to Ambient Temperature
Rise Not calculated
Methods of Estimating Die Temperature
1.00k
Gate Voltage IRF28... 100.00
W
IRF28... 100.00
C
10.05 500.00 Bus.I [A]
A
5.00 Vgs.V ..
-50.00m 0
0 2.00m 4.00m 50.00
0 200.00m
25.00
0 25.00m 50.00m72.28m -20.00n
0 2.00m 4.35m
IRF2804S_7P_Therm Parameters
Bus
IRF2804S_7P_Therm
Vbus V Vds1 Name Value Gate Voltage vs. Ig
trig 1.00m
Vds2 + 30.60 10.05
+ 20.00
Ipk 200.00
Vgs + I1 D1 Vgs.V ..
(V)
0 Load_...
(V)
Vds1....
Load Voltage Load Current
-2.44 167.65
27.80 192.00
0 200.00m 8.00u 500.00u 1.00m
N0009.V A
10.00
1.50u
0 200.00m 100.00 Experiment Table
A
RunNo Ig Load_current.MAX Tj.MAX FET Junction Temp Rise vs. Gate Current
Tj
1.00 10.00u 167.68 366.02 366.25
368.00 2.00 16.68u 174.47 314.35
3.00 27.83u 179.20 271.71 300.00
300.00 -20.00n
4.00 46.42u 182.85 207.12
0 100.00m 200.00m 5.00 77.43u 185.65 156.68
C
25.00
0 100.00m 200.00m
Methods of Estimating Die Temperature
Rdson vs. Temperature curve External Node Designations * Node 1 -> Drain * Node
2 -> Gate * Node 3 -> Source M1 9 7 8 8 MM L=100u
W=100u .MODEL MM NMOS LEVEL=1 IS=1e-32
Thermal Impedance Curve with thermal RC ladder network
+VTO=3.74133 LAMBDA=0.00250986 KP=514.947
+CGSO=7.17952e-05 CGDO=1.60578e-08 RS 8 3
0.00282867 D1 3 1 MD .MODEL MD D IS=1.89845e-
10 RS=0.00218742 N=1.20398 BV=40 +IBV=0.00025
EG=1.2 XTI=1.85712 TT=2.00014e-05
+CJO=5.42237e-09 VJ=2.67939 M=0.566441 FC=0.1
RDS 3 1 1e+06 RD 9 1 0.000681391 RG 2 7 3.16781
D2 4 5 MD1 * Default values used in MD1: * RS=0
EG=1.11 XTI=3.0 TT=0 * BV=infinite IBV=1mA
.MODEL MD1 D IS=1e-32 N=50 +CJO=3.13813e-09
VJ=0.970446 M=0.823421 FC=1e-08 D3 0 5 MD2 *
Default values used in MD2: * EG=1.11 XTI=3.0 TT=0
CJO=0 * BV=infinite IBV=1mA .MODEL MD2 D IS=1e-
10 N=0.4 RS=3e-06 RL 5 10 1 FI2 7 9 VFI2 -1 VFI2 4
0 0 EV16 10 0 9 7 1 CAP 11 10 7.84089e-09 FI1 7 9
VFI1 -1 VFI1 11 6 0 RCAP 6 10 1 D4 0 6 MD3 *
Default values used in MD3: * EG=1.11 XTI=3.0 TT=0
CJO=0 * RS=0 BV=infinite IBV=1mA .MODEL MD3 D
Rdson=F(Tj)
Vth=F(Tj)
Model Generation
Ladder Network
A thermal RC network used to model the dynamic
thermal behavior of the package + mounting
system.
117.73m K/W
RTH3
CTH1
The ladder network can be synthesized from the thermal impedance curve
or is given by the MOSFET manufacturer
Model Generation
dRdson(Tj )
= Rdson(25C ) * (2 * a * Tj + b)
dTj
P = Id * Vds
Putting it together
Drain dr
+ Vdst
irf2804s7p
+ Vds
Vth irf2804s7p1 V V Tj 10
Ta 10
Gate
PWR 10
Source
305.073m K/W
Tj 0.195105 K/W
PWR_abs Ta aC
PWR 3.808m Ws/K 26.941m Ws/K
CTH1 CTH2
Equations
EQU
dt:=Tj.T-Ta
Tj:=Tj.T-273.15
if(Vds.V<0.1) {Rdson25:=abs(Vds.V/dr.I)} else {dr:=1m}
if(Vds.V<0.1) {dr:=(7.41u*Tj+3.519m)*dt*Rdson25} else {dr:=1u}
PWR:=PWR_abs.VAL
Vth:=-7m*(Tj-25)
Model Generation
Final model
25C Spice model
Added voltage source Vth in gate implements
Vth(Tj)
dr implements dRdson = Rdson(25C ) * (2 * a * Tj + b) * (Tj − 25)
Vds and the current in dr are used to calculate
Rdson25C
Vdst and the current in dr is used to calculate the
total power
PWR_abs is used to insure that the thermal network
is driven with positive power.
Example Application
Simulation Schematic
Vbus
108 V
PWR_FET
+
W
R1
Vcc
1k Ohm
24 V IRFP4232
IRFP4232_Therm
Ig
PVI1050N
Vop1
A1
Case N0052
Von1 A
C1
Vop2
A2
STATE1 STATE2 Heatsink
C2 Von2
S1 PVI1050N
TRANS1 +
Vgs
V
R2
C1
400u F 10 Ohm
Example Application
Assumptions
Tambient=25C
Heak sink is modeled as just a thermal resistor
C1 & R2 represent a load system i.e. power
supply
Ig, Vgs, PWR_FET, States 1 & 2, Trans1 and S1
are measurements, input stimulus and ideal
switch
Example Application
Gate Voltage, Junction Temperature, Power and Current
Results 15
MOSFET Current
10 (A)
1k MOSFET Power
(W)]
500
15 Gate Voltage
10 (V)
50