FAST FOURIER TRANSFORM

FOURIER TRANSFORM is a mathematical operation to convert the function or signal from time domain to frequency domain, There are two type of FOURIER TRANSFORM one for analogue signal and the other called discrete FOURIER TRANSFORM (DFT) for digital or discrete signal, The DFT has many application, like in a filtering process to remove the noise from voice signal for example The DFT is defined by the formula

Example: if we have this signal x=[2 2 -2 -2] and we want to convert it from time domain to frequency domain:

Y=[0 4-4i 0 4+4i]

 Fast Fourier transform (FFT) is a fast algorithms efficiently to compute the discrete Fourier transform (DFT). The most important part in FFT is the butter fly:

Where WN is

 To explain FFT let give example of FFT for Four point:

We can build 4 points FFT by using four butter fly As the following

 As the same idea we can build FFT for 8 point By using four 4 points FFT

Design FFT 4 point in FPGA by using VHDL language

We can design FFT in FPGA ,for many application like in filtering or any other application

The design of 4-Points FFT done as the following

We insert a discrete signal of 4 points Each input point is 4 bits, and each point has maximum value +7 and minimum value -7 We insert these points by using 4-switch, the points insert one point after another and to obtain 4 points by using serial to parallel block(I will explain it later) Then we insert these 4 points to Butterfly blocks , this block give us 4 points but in frequency domain Each point in the frequency domain has two part ,real part and imaginary part each part is 6 bits Then output these points to group of LEDs(6 LEDs) By using serial to parallel block ,these points will exit one point after another, first real part exit and second the imaginary part

The program of 4-Points FFT

The program contain 3 subroutine(component) The components is:1.ser2par: it convert 4 to 24 bits. 2.Butterfly :the butterfly is done by using IP-core or without using the IP-core . 3.par2ser : it convert 48 to 8 bits, and display these 8 bits by using 8 LED

The summary

The summary when using IP-core

General block diagram design of FFT in FPGA kit

RTL of design

The simulation of program

The code of butterfly

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH. ALL; use IEEE.STD_LOGIC_UNSIGNED. ALL entity butter is Port ( Xr0: in std_logic_vector (5 downto 0); Xi0: in std_logic_vector (5 downto 0); Xr1: in std_logic_vector (5 downto 0); Xi1: in std_logic_vector (5 downto 0); wi: in std_logic; yr0: out std_logic_vector (5 downto 0); yi0: out std_logic_vector (5 downto 0);

yr1: out std_logic_vector (5 downto 0); yi1: out std_logic_vector (5 downto 0)); end butter; architecture Behavioral of butter is signal s:std_logic_vector (5 downto 0); begin s<=wi&wi&wi&wi&wi&wi; yr0<=xr0+( xr1 and(not s))+(Xi1 and s); yi0<=xi0+(((not(xr1))+1)and s)+( xi1 and(not s)); yr1<=xr0+(((not(xr1))+1)and(not s))+(((not(xi1))+1)and s); yi1<=(xr1 and s)+xi0+( xi1 and(not s)); end Behavioral;

The code of 4 to 24 bits

entity ser2par is Port ( ck,rst:in std_logic; xxx : in std_logic_vector (3 downto 0); y0 : out std_logic_vector (5 downto 0); y1 : out std_logic_vector (5 downto 0); y2 : out std_logic_vector (5 downto 0); y3 : out std_logic_vector (5 downto 0)); end ser2par; begin process(ck,rst) variable count:integer RANGE 0 TO 6:=0; begin architecture Behavioral of ser2par is

if(rst='1')then count:=0; elsIF (ck'EVENT AND ck='1') THEN CASE count IS WHEN 0 => y0 <= "00"&xxx; WHEN 1 => y1 <= "00"&xxx; WHEN 2 => y2 <= "00"&xxx; WHEN 3 => y3 <= "00"&xxx; WHEN OTHERS => NULL; END CASE; if(count<4)then count:=count+1; end if; end if; end process; end Behavioral;

The code of 48 to 6 bits

entity par2ser is Port ( ck,rst,sn:in std_logic; x0 : in std_logic_vector (5 downto 0); x1 : in std_logic_vector (5 downto 0); x2 : in std_logic_vector (5 downto 0); x3 : in std_logic_vector (5 downto 0); x4 : in std_logic_vector (5 downto 0); x5 : in std_logic_vector (5 downto 0); x6 : in std_logic_vector (5 downto 0); x7 : in std_logic_vector (5 downto 0); yy : out std_logic_vector (7 downto 0)); end par2ser; architecture Behavioral of par2ser is

begin process(ck,rst) variable count:integer RANGE 0 TO 8:=0; begin if(rst='1')then count:=0; yy<="00000000"; elsIF (ck'EVENT AND ck='1' )THEN CASE count IS WHEN 0 => yy <= "01"&x0; WHEN 1 => yy <= "10"&x1; WHEN 2 => yy <= "01"&x2; WHEN 3 => yy <= "10"&x3; WHEN 4 => yy <= "01"&x4; WHEN 5 => yy <= "10"&x5; WHEN 6 => yy <= "01"&x6; WHEN 7 => yy <= "10"&x7; WHEN OTHERS => NULL; END CASE; if(count<8) then count:=count+1; end if;end if;end process;end Behavioral

The code of main program

entity mainn is Port ( clk,rsst,clk2,rsst2 : in STD_LOGIC; x : in STD_LOGIC_VECTOR (3 downto 0); y : out STD_LOGIC_VECTOR (7 downto 0)); end mainn; ------------------------------------------------------------------------------------------------------architecture Behavioral of mainn is component ser2par is Port (ck,rst:in STD_LOGIC; xxx : in STD_LOGIC_VECTOR (3 downto 0); y0 : out STD_LOGIC_VECTOR (5 downto 0); y1 : out STD_LOGIC_VECTOR (5 downto 0); y2 : out STD_LOGIC_VECTOR (5 downto 0); y3 : out STD_LOGIC_VECTOR (5 downto 0)); end component ser2par;

component butter is Port ( Xr0: in STD_LOGIC_VECTOR (5 downto 0); Xi0: in STD_LOGIC_VECTOR (5 downto 0); Xr1: in STD_LOGIC_VECTOR (5 downto 0); Xi1: in STD_LOGIC_VECTOR (5 downto 0);
wi: in STD_LOGIC; yr0: out STD_LOGIC_VECTOR (5 downto 0); yi0: out STD_LOGIC_VECTOR (5 downto 0); yr1: out STD_LOGIC_VECTOR (5 downto 0); yi1: out STD_LOGIC_VECTOR (5 downto 0)); end component butter; --------------------------------------------------------------------------------------------------------------------------------component par2ser is Port ( ck,rst,sn:in std_logic; x0 : in STD_LOGIC_VECTOR (5 downto 0); x1 : in STD_LOGIC_VECTOR (5 downto 0); x2 : in STD_LOGIC_VECTOR (5 downto 0); x3 : in STD_LOGIC_VECTOR (5 downto 0); x4 : in STD_LOGIC_VECTOR (5 downto 0); x5 : in STD_LOGIC_VECTOR (5 downto 0); x6 : in STD_LOGIC_VECTOR (5 downto 0); x7 : in STD_LOGIC_VECTOR (5 downto 0); yy : out STD_LOGIC_VECTOR (7 downto 0)); end component par2ser;

signal x0, x1, x2, x3,fe0,fe1,fo0,fo1,fei0,fei1,foi0,foi1: STD_LOGIC_VECTOR (5 downto 0); signal yyr0,yyi0, yyr1,yyi1,yyr2,yyi2, yyr3,yyi3: STD_LOGIC_VECTOR (5 downto 0); begin ------------------------------------------------------------------------------------------------------U0: ser2par port map (clk,rsst,x,x0,x1,x2,x3); ------------------------------------------------------------------------------------------------------U1: butter port map (x0,"000000",x2 ,"000000",'0',fe0,fei0,fe1,fei1); U2: butter port map (x1,"000000",x3 ,"000000",'0',fo0,foi0,fo1,foi1); U3: butter port map (fe0,fei0 ,fo0 ,foi0 ,'0',yyr0,yyi0,yyr2,yyi2); U4: butter port map (fe1,fei1 ,fo1 ,foi1 ,'1',yyr1,yyi1,yyr3,yyi3); ------------------------------------------------------------------------------------------------------U6: par2ser port map (clk2,rsst2,yyr0,yyi0, yyr1,yyi1,yyr2,yyi2, yr3,yyi3,y); ------------------------------------------------------------------------------------------------------end Behavioral;