1/24/2012

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BJT DC Biasing
EE 21 Fundamentals of Electronics
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Analysis of Transistor Circuits
As previously mentioned, transistor is not some
magical device with efficiency > 100%

The improved output AC power level is the result of
energy transfer from applied DC supplies.

AC and DC response of a transistor amplifier system is
taken into consideration

Superposition theorem is applied
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DC Analysis of Transistor Circuits
NPN transistors are to be used in the
configurations

PNP transistors change analysis simply by
reversing all current directions and voltage
polarities

Capacitors are open at DC; capacitors are
chosen such that they have near-zero
reactance at frequencies of interest.
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Important relationships
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B E
B C
BE
I I
I I
V V
) 1 (
7 . 0
+ =
=
=
|
|
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Basic Transistor Configurations
Fixed bias
Emitter-stabilized bias
Voltage-divider bias
Feedback bias
Miscellaneous configurations
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Fixed Bias
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R
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Equivalent Ckt (DC analysis)
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R
C
R
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DC Analysis of Fixed bias
INPUT (B-E) LOOP:
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0 =
BE B B CC
V R I V
B
BE CC
B
R
V V
I

=
E
E

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Fixed Bias: Output Loop
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R
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DC Analysis of Fixed Bias
OUTPUT (C-E) LOOP:




The bottom equation is the equation of your
loadline.

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0 =
CE C C CC
V R I V
C C CC CE
R I V V =
E
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Reviewing the subscripted
voltage notation
V
CE
= V
C
V
E
.
V
BE
= V
B
V
E
.

But in the fixed bias circuit, the emitter terminal
is directly connected to ground, thus V
E
= 0,

Therefore, V
CE
= V
C
V
BE
= V
B
.
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Example: Fixed-bias circuit
For the fixed bias
circuit, determine:
a. Base current I
B
b. Q-point coordinates
c. V
B
and V
C
d. V
BC
e. Interpret the value
of V
BC
.

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Loadline and Q-point
The equation is called the
loadline, defined by the load resistance Rc.

It is a line relating the output voltage V
CE
and
the output current I
C
.

At a certain DC bias, a transistor circuit has a
Q-point (operating point), with coordinates
(V
CEQ
, I
CQ
).
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C C CC CE
R I V V =
E
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Transistor Saturation
A transistor in saturation = distorted signal*
Current is theoretically maximum if V
CE
= 0.
i.e.


Taking R
CE
as theoretical short, the loadline
equation for I
Csat
is given by
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O = = = 0
0
CSat C
CE
CE
I I
V
R
C
CC
CSat
R
V
I =
E
E

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Transistor Cutoff
The loadline equation also gives us the value
of the transistor cutoff, where I
C
= 0.


Taking R
CE
as theoretical open circuit, the
loadline equation gives the expression for
V
CEcutoff
:



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O = = =
0
CECutoff
C
CE
CE
V
I
V
R
CC CECutoff
V V =
E
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Loadline plotting
The two points (V
CEcutoff
, 0) and (0, I
Csat
) are the
two intercepts of the loadline.

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Loadline Variations: Rc
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Loadline Variations: Vcc
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Emitter-Stabilized Bias Circuit
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DC Analysis of Emitter-Stabilized Bias
INPUT (B-E) LOOP:


but I
E
= I
B
(+1), therefore
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0 =
E E BE B B CC
R I V R I V
E B
BE CC
B
R R
V V
I
) 1 ( + +

=
|
0 ) 1 ( = +
E B BE B B CC
R I V R I V |
E
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DC Analysis of Emitter-Stabilized Bias
OUTPUT (C-E) LOOP:


letting I
C
be approximately equal to I
E
,





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0 =
E E CE C C CC
R I V R I V
) (
E C C CC CE
R R I V V + =
0 =
E C CE C C CC
R I V R I V
E
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Notes:
V
E
- emitter-ground voltage

V
C
collector-ground voltage:


V
B
base-ground voltage




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C C CC E CE C
R I V V V V = + =
E C E E E
R I R I V = =
E BE B
V V V + =
E
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Example: Emitter-Stabilized Bias
For the network shown,
determine:
1. Base current
2. Q-point coordinates
3. Vc, V
E
, and V
B
4. V
BC
5. Interpret V
BC
.
6. Plot the loadline and
Q-point of the circuit.
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Home/Dorm/etc. work
Repeat examples 1 (fixed bias) and 2 (emitter-
stabilized) for =100.

Plot the corresponding loadlines and Q-points
and compare them with what we solved in
class.
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1/24/2012
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Voltage-Divider Bias Circuit
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DC Analysis of Voltage-Divider Bias
Two methods of analysis:
Exact: method is always useable, requires
Thvenins theorem on the input side of the
network

Approximate: especially useful for designing VD
circuits, however, it can only be used upon
meeting a required design criteria.


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Voltage-Divider Bias: Exact Analysis
Use Thvenins
theorem on the
input side of the
network:

We need Thvenin
resistance and
voltage to construct
TEC for the input
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Input Side Equivalence
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|
|
.
|

\
|
+
= =
=
2 1
2
2
2 1
//
R R
R
V V E
R R R
CC R TH
TH
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Equivalent circuit with TEC @ Input
The voltage-divider
circuit can now be
analyzed in the
same manner as the
emitter-stabilized
bias configuration.
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DC Analysis of Voltage-Divider Bias
INPUT (B-E) LOOP:


again, let I
E
= I
B
(+1), therefore
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0 =
E E BE TH B TH
R I V R I E
E TH
BE TH
B
R R
V E
I
) 1 ( + +

=
|
0 ) 1 ( = +
E B BE TH B TH
R I V R I E |
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DC Analysis of Voltage-Divider Bias
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OUTPUT (C-E) LOOP:


letting I
C
be approximately equal to I
E
,





0 =
E E CE C C CC
R I V R I V
) (
E C C CC CE
R R I V V + =
0 =
E C CE C C CC
R I V R I V
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Voltage Divider Approximate Analysis
Base-ground resistance, denoted as Ri, is much
larger when reflected to the input loop
Accepting this, then Ri>>R
2
for the voltage div
Thus, I
B
<<I
2
R
1
series w/ R
2
.
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Voltage Divider Approximate Analysis
With this assumption, VDR can be applied:



Condition for allowing approximate analysis:


This is known as the design criteria


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|
|
.
|

\
|
+
=
2 1
2
R R
R
V V
CC B
2
10R R
E
= |
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Voltage Divider Approximate Analysis
The following calculations trace the circuit to
get the needed quantities:


At output:



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BE B E
V V V =
) (
E C C CC CE
R R I V V + =
0 =
E C CE C C CC
R I V R I V
C
E
E
E
I
R
V
I = =
E
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Voltage Divider Approximate Analysis
With the approximate solution,

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BE B E
V V V =
BE
CC
E
V
R R
R V
V
+
=
2 1
2
E
BE
CC
C E
R
V
R R
R V
I I

+
= =
2 1
2
E
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Example: Voltage Divider Bias
Solve the circuit
using exact and
approximate
methods, and
compare the values
of V
CE
and I
C
.
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Voltage Feedback Bias
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DC Analysis of Voltage Feedback
First we note that

assume I
B
very small, such that


The base-emitter loop is as follows:


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B C C
I I I | = = '
B C C
I I I + = '
0 ' =
E E BE B B C C CC
R I V R I R I V
E
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DC Analysis of Voltage Feedback
Substituting the following relations:
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( )
E C B
BE CC
B
R R R
V V
I
+ +

=
|
B C C
I I I | = = '
C E
I I ~
0 =
E B BE B B C B CC
R I V R I R I V | |
E
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DC Analysis of Voltage Feedback
C.E. Loop:


substituting and isolating V
CE


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0 ' =
E E CE C C CC
R I V R I V
E C C
I I I = = '
) (
E C C CC CE
R R I V V + =
E
E

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Example: Voltage Feedback Bias
For the
configuration below,
determine I
C
and I
E
.
Repeat for =135.
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Miscellaneous Bias Configurations
Configurations not falling under the four
common circuits discussed
Procedure for analysis, though, is the same:
Use the input side of the circuit to find an
expression for the input current (aka controlling
current)
Find the load-line using the output side of the
circuit
Circuit simplification (such as Thvnins thm) may
be applied if necessary.

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Example 1: Common-base circuit
For the common-base circuit, determine the
voltage VCB and the current IB. Assume =1.
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Example 2: Common-collector configuration
Determine V
CE
and I
E
.
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Transistor Network Design
Circuit design: Use appropriate relationships
such as ohms law & doubly-subscripted
voltage calculations.
For voltage-divider circuit networks, the
approximate analysis is used (recall design
criteria).
If multiple resistors are unknown, the
relationship is a good place to
start.
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CC E
V V
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1
=
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Example 3:
Voltage-Divider Circuit Design
Design a voltage divider circuit with the
following requirements:
Biasing voltage Vcc = 20 Volts
= 80
Q-point coordinates: (8 V, 10 mA)

What quantities are unknown?
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