Report.. PFD

ABSTRACT
Blind zone in a phase-frequency detector (PFD) reduces the input detection range and aggravates cycle slips. This brief analyzes the blind zone in latch-based PFDs and proposes a technique that removes the blind zone caused by the precharge time of the internal nodes. With the proposed technique, the PFD achieves a small blind zone close to the limit imposed by process-voltagetemperature variations. The comparison between the proposed design and previous works is presented. Fabricated in a 130-nm CMOS technology, the measured blind zone is 61 ps, which is smaller than that of the existing topologies by almost 100 ps.
Semester: II
Branch: VLSI AND EMBEDDED SYSTEMS
Phase Frequency Detector With Minimal Blind Zone for Fast Frequency Acquisition
1. INTRODUCTION
CHARGE-pump-based phase-locked loops (PLLs) have been widely used in many high-speed designs, such as high-speed microprocessors or communication systems, for their low-complexity zero-steady-state phase error and infinite pulling range. This type of PLL often includes a tri-state phase frequency detector (PFD) to monitor the phase and frequency differences between its two inputs and transfers the information to the charge pump generating the voltage signal that controls the frequency of the voltage-controlled oscillator. The tri-state PFDs are usually built with memory elements, and thus, they need a reset signal to clear the memory elements. Several tri-state PFD architecture have been there including precharge-type PFD[1] ncPFD[2] and latch based PFD [3][5].Among the published PFD topologies, the latch-based PFD is the most commonly used one for its high operation speed, low power consumption, wide input range, and independence to the input duty cycle[3]. One of the issues of the PFD/charge-pumpbased PLL is the dead zone, which is the minimum pulsewidth of the PFD output that is needed to turn on the charge pump completely. To mitigate the dead-zone issue, the reset signal inside the tristate PFD can be designed to trigger pulses with a constant width at the PFD outputs when the phases of the inputs are aligned. However, since the circuits cannot work during the reset process, a blind zone, where the PFD cannot react to any transitions on the input signals, is inherent in the circuits. If the phase difference falls into the blind zone during the frequency acquisition, the PFD delivers incorrect phase information to the charge pump and shifts the toward the opposite direction, which aggravates cycle slips and elongates the frequency pull-in time, as proven in [5]-[7].
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The increased chance of cycle slips adversely affects the PLL frequency acquisition time and is undesirable in systems that require fast frequency transition, such as the multiband orthogonal frequency-division multiplexing system. The chance that the phase difference falls into the blind zone is effectively random, and in practice, the most effective way to reduce the probability of having a blind zone event is decreasing the blind zone [8]. Nonetheless, the charge pump, which uses transistors with channel lengths much longer than the minimum available length to guarantee a good current matching, high output impedance, and low leakage current, decides the width of the dead-zone cancellation pulse. Consequently, the required pulsewidth does not shrink with the scaling of CMOS technology. With increasing input frequency, the fixed reset pulsewidth becomes a greater portion of the total period, and design techniques are needed to reduce the blind zone while maintaining the same reset pulsewidth [9]. The most widely known technique is adding a delay cell [4],[5].. Here, we show that the precharging time for the internal parasitic capacitances is equally or more responsible for the blind zone and propose a PFD that mitigates the precharging issue using two extra transistors. This approach reduces the blind zone close to the theoretical limit imposed by PVT variations.
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2.BLIND ZONE EFFECT AND CANCELLATION

When the phase difference between the two inputs is close to 2, the rising edge of the leading phase can fall into the reset region. During reset process, the PFD cannot detect the leading signal, so it treats the following lagged signal as the leading one and generates reversed phase information. This is called the blind zone since the PFD is blind in that region. Because of this effect, the phase comparison range of the PFD reduces to 2 , where is the length of the blind zone normalized to 2. The solid line in Fig.2.1 shows the inputoutput characteristic of a latch-based PFD with blind zone. In general, the width of the reset pulse is about several hundred picoseconds, depending on the settling time of the charge pump current.
Fig:2.1:Typical Characteristic of PFDs
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It is worth considering the relation between the blind zone and the hang-up effect. The hang-up effect is caused by the periodic property of the phase detector, which contains two zero-crossing points in the characteristic waveform in 2 phase shift [10],[11] .The second zero-crossing point is a reversed unstable point and can trap the phase-locking Toc H Institute of Science & Technology process for a while, which prolongs the phase acquisition time. An ideal sequential PFD
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Project Title :Phase Frequency Detector With Minimal Blind Zone for Fast Frequency Acquisition
Fig:2.2 Schematic of PFD[4]
To ensure a proper operation, the added delay TD must be smaller than the reset time Tres in all conditions. If TD > Tres, the input clock pulse that triggers the reset would activate the output after the reset ends, which makes the PFD fail.
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The dashed line in Fig. 2.1 shows the characteristic of the PFD with the added delay
Semester: II
cells. When the phase difference enters the blind zone, the leading phase is Blind Zone SYSTEMS With Minimal delayed by for to this approach, the delay cells, and the output has a constant pulse width. According Fast Frequency
Acquisition
Branch: VLSI AND EMBEDDED
Phase Frequency Detector
the blind zone becomes Tres TD, which can be very close to zero if TD is close to Tres. However, in practice, the blind zone consists of two major portions, i.e., the reset Since the input directly drives MN2, once the input signal goes low, the Fig. 2.3. process Tres and precharge time of the internal nodes Tchp, as depicted in pull-down path is cut off, and the partially charged node T1 pulls node U1 high, which causes an undesired transition at the output, as shown in Fig. 2.4.
Fig 2.3:Timing Diagram of Blind zone
When Tres is reduced to several hundred picoseconds, the necessary precharge time occupies a large portion of the blind zone and cannot be ignored. To understand this, let us take the upper branch circuit shown in Fig. 2 as an example. If the delayed signal after the reset does not provide enough time to charge the internal nodes, the voltage at node
Fig 2.4 Erroneous output from the PFD (when the charging time is not long enough.)
T1 will be not high enough to switch off the transistor MP3 completely.
The same problem also exists in the lower branch circuit. Therefore, the blind zone is actually Tres TD + Tchp rather than just Tres TD.
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Fig 2.5 Length of the blind zone versus the added delay cell.
Fig.2.5 shows the effect of Tchp in simulation. The length of the blind zone is 100 ps larger than the reset pulse without the delay cell. With the increasing delay time, the length of the blind zone reduces, but even for a delay of 150 ps, the blind zone is still 136 ps. The charging time of the internal nodes in the PFD is responsible for the remaining portion of the blind zone.
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We propose a PFD that can alleviate the limitation of Tchp, as shown in Fig.2.6.The modified PFD combines the high-speed PFD proposed in [3] with a delay cell and two extra transistors. The two extra transistors MP7 and MP8 are added to turn on the pull-up paths at the falling edges of the inputs. Comparing the operating waveforms in Figs.2.4 and 2.7 explains the role of the two extra transistors. Without MP7 and MP8, the halfcharged node T1 pulls node U1 high at the falling edge of the inputs and causes an undesired transition at the output.
Fig 2.6 Schematic of the proposed PFD.
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Fig.2.7 Waveform of proposed PFD
The added MP7 and MP8 pull T1 to high immediately at the falling edges of the inputs and prevent the output from erroneously changing states. Note that MP7 and MP8 do not affect the function of the delay cells because the delay cells are mainly designed to delay the rising edges of the input, where the phase relationship is compared with, whereas the two added transistors are used to remove the delay at the falling edges of the input, where the partially charged nodes could cause problem.
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Fig 2.8 Simulated blind zone of three different PFDs.
Fig. 2.8 shows the widths of the blind zone for three different PFDs in simulation, including a conventional latch-based PFD, the one with a delay cell in [4] and the proposed PFD. For a fair comparison, the simulations are done in the typical process corner at room temperature (27 C) condition. The reset pulsewidth is set to 160 ps, and the difference between the reset pulse and the delay time is set to 48 ps for the PFDs.
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Project Title Phase Frequency Detector With Minimal Blind Zone for Fast Frequency Acquisition
The figure shows that the length of the blind zone of the conventional PFD is 251 ps. Adding the delay cell reduces the blind zone to 155.6 ps, which is still much larger than . The proposed design shrinks the blind zone by another 103 ps, and the resulting blind zone, i.e., 52.2 ps, is only 4.2 ps larger than , which demonstrates that the blind zone is almost only determined by . We note that the value of must be set large enough to guarantee a correct operation in different process corners and temperatures, and hence, the minimum value of the blind zone is determined by the PVT variations. The improvement of the proposed PFD can be evaluated by the gain attenuation factor of the PFDs. The gain attenuation factor is introduced in [6] to calculate the average gain reduction of the PFD caused by the blind zone in high-speed operation. The equation for the factor is repeated as = 1 2( TD) T2D
(1)
where is the normalized width of the blind zone, and TD is the delay of the delay cell normalized to one clock cycle.
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The two added transistors MP7 and MP8 also increase the maximum operating frequency because of the finite precharge time Tchp. To see this, one can compare the charging time Tct, as shown in Figs. 2.4 and 2. 7. Without transistor MP7 and MP8, the maximum Tct is equal to Tck/2 TD, where Tck is the period of the input signal. When the input frequency increases to several gigahertzes, Tct might be smaller than Tchp, preventing T1 and T2 from being pulled to a high-enough level.
Fig 2.9 simulated phase characteristic waveform of the PFDs and the average Kpfd.
Fig. 2.9 shows the phase characteristic waveforms and the corresponding gain attenuation factors of the three PFDs when the input frequency is set to 1.6 GHz. As can be seen in the figure, since the three PFDs have the same circuit delay and reset pulsewidth, the phase characteristic curves bend down almost at the same position, but because of the reduced charging time, the blind zone of the proposed PFD shrinks, which leads to the lowest gain reduction. Reducing the blind zone leads to a faster frequency acquisition time and consequently, the proposed design is suitable for the applications that require fast frequency switching.
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Fig 2.10 Simulated phase characteristic of the PFDs and the waveform of node T1 when the input frequency is set to 2.7 GHz.
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The half charged voltage on T1 and T2 extends the reset pulse and reduces the operating speed. Adding transistors MP7 and MP8 mitigates this limitation since Tct is always equal to Tck/2. Fig. 2.10 shows the phase characteristic of the PFDs and the corresponding voltage waveform of the node T1 when the input frequency is set to 2.7GHz. For the proposed PFD, T1 is still a full-swing wave, whereas, for the design in [4] the T1 node drops low and results in an erroneous behavior.
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3:MEASUREMENT
The proposed PFD has been verified experimentally with a test chip. The test chip integrates an integer-N PLL that generates the carrier frequency for an ultrawideband transceiver. The chip is fabricated in a 130-nm CMOS technology. Fig. 3.1 shows the microphotograph of the PFD.
Fig 3.1 Microphotograph of the test chip.
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Fig. 3.2 shows the test setup for the blind zone measurement. To measure the width of the blind zone, an external programmable delay line (SY100EP196V) is employed to control the phase difference between the inputs of the PFD.
Fig 3.2 Block diagram of the PFD blind zone test setup.
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The phase delay IC provides a maximum 10-ns phase shift with a 10-ps incremental step. By applying a bias voltage at the VCO control voltage, the output frequency of the divider is set to provide a frequency of 124.8 MHz for the PFD measurement. The phase delay IC takes the output of the frequency divider as a signal source and generates a delayed version of the signal that is fed back to the PFD. Since the inputs of the PFD have exactly the same frequency, the output current of the charge pump depends only on the phase differences. Note that, when entering the blind zone, the PFD output instantly jumps to a very small value with inverse polarity, which changes the output current of the charge pump abruptly. Therefore, the edge of the blind zone can be estimated by measuring the average voltage at the output of the charge pump. Because of the unknown delay from the inputs of the test chip to the PFD, we cannot directly control the arbitrary phase differences at the input of the PFD. Moreover, once the PFD enters its blind zone, the phase difference automatically shifts by 2 and becomes aligned, so we cannot shift the phase monotonically to check the width of the blind zone. For the reasons, we have to scan the phase difference over 2 to find the aligned point and approach the }2 phase difference points from the right side (the reference clock lags the feedback clock) and from the left side (the reference clock leads the feedback clock) in sequence to measure the gap between the two points where the PFD output changes instantly. The gap represents the total blind zone in 4 phase shift. Fig.3.3 shows the measured average voltage versus the normalized phase difference.
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Fig 3.3 Measured blind zone of the proposed PFD.
The total width of the blind zone is 122 ps in a 4 phase shift, which is equivalent to 61 ps per cycle. Even after considering the 10-ps phase step limitation, which introduces a 5 ps uncertainty, the measured blind zone agrees well with the analytical and simulation results.
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3.1 Comparison PFD performance comparison (simulated)

Parameter (Units) high speed & Fast settling low power PLL PFD 162 221 2.17 165 156 2.5 296 Proposed PFD
Reset pulse (ps) Blind zone (ps) Maximum frequency (GHz)
156 61 2.94 496
Power consumption 325 @ 128MHz (W)
Table-3.1
Table 3.1 compares the simulated performance of the proposed PFD with previously known architectures. All of the designs use the same transistor sizes and clock waveforms. The simulation is done in typical corner with 1.2-V power supply. The proposed design has the shortest blind zone close to the limit imposed by PVT variations but with higher power consumption.
Semester: II
3.2 Applications
After nearly 70 years since its invention, phase locking continues to find new applications in electronics, communication and instrumentation. Comparing with the power consumption of a typical PLL, which is usually up to tens of milliwatt, the 171-W power penalty would be insignificant for most applications. The proposed scheme finds wide application, especially in frequency sensitive circuits like that of spread spectrum modulation/demodulation, frequency synthesis, frequency multiplication, FM detection, skew reduction, jitter reduction.
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4.CONCLUSION& FUTURE SCOPE

The reset mechanism in the PFD creates the blind zone, which reduces the input detection range, degrades the average PFD gain, and aggravates the cycle-slip effect, hindering fast PLL acquisition. Because the reset pulse width does not shrink with the scaling of CMOS technology, mitigating the blind zone issue requires a circuit-topologylevel approach. The widely adopted compensation technique using input delay cells only partially addresses the blind zone issue, failing to eliminate the blind zone caused by the nonnegligible precharging time for internal parasitic. In this brief, we have presented a modified PFD that significantly reduces the precharging time. The proposed technique allows reducing the blind zone by more than 100 ps, compared with the widely adopted topology having only delay cells. Fabricated in a 130-nm CMOS technology, the measured blind zone is 61 ps, which is close to the limit imposed by PVT variations. It is desirable, and the future lies on further decreasing the blind zone from 100ps ,but should be at a lower power consumption
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5.REFERENCES
. [1] H. Kondoh, H. Notani, T. Yoshimura, H. Shibata, and Y. Matsuda, A 1.5-V 250-MHz to 3.0-V 622-MHz operation CMOS phase-locked loop with precharge type phase-frequency detector, IEICE Trans. Electron., vol. E78-C, no. 4, pp. 381388, Apr. 1995. [2] H. Johansson, A simple precharged CMOS phase frequency detector, IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 295299, Feb. 1998. [3] W.-H. Lee, J.-D. Cho, and S.-D. Lee, A high speed and low power phasefrequency detector and charge-pump, in Proc. Asia South Pacic Des. Autom. Conf., Jan. 1999, vol. 1, pp. 269272. [4] G.-Y. Tak, S.-B. Hyun, T. Y. Kang, B. G. Choi, and S. S. Park, A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications, IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 16711679, Aug. 2005. [5] M. Mansuri, D. Liu, and C.-K. Yang, Fast frequency acquisition phasefrequency detectors for Gsamples/s phase-locked loops, IEEE J. SolidState Circuits, vol. 37, no. 10, pp. 13311334, Oct. 2002. [6] R. Chen and Z.-Y. Yang, Modeling the high-frequency degradation of phase/frequency detectors, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 5, pp. 394398, May 2010. [7]F.M.Gardner, Phaselock Techniques, 3rd ed. New York: WileyInterscience, 2005
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[8] C. Toumazou, G. S. Moschytz, and B. Gilbert, Trade-Offs in Analog Circuit Design: The Designers Companion. New York: SpringerVerlag, 2004. [9] K. Arshak, O. Abubaker, and E. Jafer, Design and simulation difference types CMOS phase frequency detector for high speed and low jitter PLL, in Proc. 5th IEEE Int. Caracas Conf. Devices, Circuits Syst.,Nov.35, 2004, vol. 1, pp. 188191. [10] F. Gardner, Hangup in phase-lock loops, IEEE Trans. Commun., vol. COM-25, no. 10, pp. 12101214, Oct. 1977. [11] F. Gardner, Equivocation as a cause of PLL hangup, IEEE Trans. Commun., vol. COM-30, no. 10, pp. 22422243, Oct. 1982. [12] W. Hu, L. Chunglen, and X. Wang, Fast frequency acquisition phasefrequency detector with zero blind zone in PLL, Electron. Lett., vol. 43,
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Report.. PFD

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ABSTRACT

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Toc H Institute of Science & Technology Arakkunnam 682 313

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2.BLIND ZONE EFFECT AND CANCELLATION

Fig:2.1:Typical Characteristic of PFDs

Toc H Institute of Science & Technology Arakkunnam 682 313

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Fig:2.2 Schematic of PFD[4]

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Phase Frequency Detector

Fig 2.3:Timing Diagram of Blind zone

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Fig 2.6 Schematic of the proposed PFD.

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Fig.2.7 Waveform of proposed PFD

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Fig 2.8 Simulated blind zone of three different PFDs.

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Fig 3.1 Microphotograph of the test chip.

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Fig 3.3 Measured blind zone of the proposed PFD.

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3.1 Comparison PFD performance comparison (simulated)

Reset pulse (ps) Blind zone (ps) Maximum frequency (GHz)

156 61 2.94 496

Power consumption 325 @ 128MHz (W)

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4.CONCLUSION& FUTURE SCOPE

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Toc H Institute of Science & Technology Arakkunnam 682 313

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Toc H Institute of Science & Technology Arakkunnam 682 313