LOW-POWER SYSTEMS-ON-CHIP

Complementary pass-transistor energy recovery logic for low-power applications

R.C. Chang, P.-C. Hung and I.-H. Wang Abstract: In the paper, a low-power adiabatic logic called complementary pass-transistor energy recovery logic (CPERL) is proposed. It utilises the bootstrapping technique to achieve efcient power saving and eliminates any nonadiabatic losses on the charge-steering devices. A scheme is used to recover part of the energy trapped in the bootstrapping nodes. A single CPERL gate requires only one phase power clock. The energy dissipation between CPERL and other logic circuits is compared by simulation. Simulation results show that a CPERL 10-stage inverter chain only consumes 48.8% of energy dissipated in conventional CMOS at 125 MHz. Operation of an 8-bit CPERL carry lookahead adder designed using the TSMC 0.35 mm 1P4M CMOS technology has been veried. Therefore, system-on-chip (SoC) and portable computing applications can be realised using CPERL circuits.

Introduction

Reducing power consumption has become an important issue in integrated circuit design owing to the strong demand for low-power system-on-chip (SoC) and portable electronic equipments with state-of-the-art computational power and reliability. Adiabatic logic (or so-called energy recovery logic) is a design style to reduce power consumption. Adiabatic switching can circumvent the CV2 dissipated energy barrier, generated by operating CMOS circuits conventionally [1]. The energy dissipated in adiabatic circuits can be divided into two kinds: adiabatic loss and nonadiabatic loss [2]. An adiabatic circuit cannot avoid adiabatic loss. Adiabatic logic can usually reduce only part of the nonadiabatic loss. Several adiabatic logic architectures have been presented for low-power VLSI design [217]. Most use diodes or diode-like devices for precharge, which cause unavoidable energy loss due to the voltage drop across the diodes [3]. ECRL [3], PAL [4], PAL-2N [5], ADCPL [6] and CAL [7] were proposed to eliminate the precharge diodes, but they suffer from a closed recovery path. An energy-efcient charge-steering device is the key component in adiabatic circuits. For full energy recovery, the path between the power-clock supply and an output node may not be closed during charging or discharging. To ensure this condition, a retractile cascade timing scheme is required [8]. The bootstrapping technique is an approach to form a retractile cascade timing scheme without generating complex clock phases. This technique precharges the charge-steering transistor gate high and makes the transistor turn on as the power-clock supply begins to ramp high.
# IEE, 2002 IEE Proceedings online no. 20020447 DOI: 10.1049/ip-cdt:20020447 Paper rst received 15th October 2001 and in revised form 20th March 2002 The authors are with the Department of Electrical Engineering, National Chung-Hsing University, Taichung, Taiwan, Republic of China
146

Effective bootstrapping makes the switch transistor gate voltage rise high enough above the highest applied clock voltage to keep the channel conductance high [9]. Kim et al. proposed an NMOS energy recovery logic (NERL) [10]. NERL exhibits low-energy consumption due to efcient energy transfer and recovery using bootstrapping. Fig. 1 shows an NERL inverter. Its energy dissipation can be written as [10] ENERL Cboot Vdd Vth 1

where Cboot is the capacitance of the bootstrapping node, Vdd is the peak value of the power supply and Vth is the threshold voltage of the isolation transistors M5 and M6. A new adiabatic logic called complementary passtransistor energy recovery logic (CPERL) is described in this paper. It uses a complementary pass-transistor logic tree (CPL) as the logic-evaluating tree and bootstrapping technique. CPERL is diode free and is a dual-rail logic family. A single CPERL gate requires only one phase power clock and cascaded CPERL circuits operate with a two-phase nonoverlapping supply clock. Energy is recovered in the recovery phase of the power clock. A pipeline structure can be directly implemented without any specic latch. 2 Complementary pass-transistor energy recovery logic 2.1 CPERL gates A CPERL gate is established in a differential structure and uses only NMOS transistors. Fig. 2 shows the circuit schematic diagram of the basic CPERL inverter. A CPERL gate consists of two parts: charge-discharge circuit and logic function. The charge-discharge part (M1M6) uses bootstrapping for full energy recovery. M1 and M2 act as bootstrapping NMOS transistors. Transistors M3M6 are used to discharge bootstrapping nodes for correct operation. The logic function part (M9M12) uses a complementary pass-transistor for generating proper logic value. Different logic can be acquired by changing this part
IEE Proc.-Comput. Digit. Tech., Vol. 149, No. 4, July 2002

Fig. 4 Cascaded inverters of CPERL using 2-phase power-clock supply

Fig. 1

Schematic diagram of the NERL inverter

Fig. 2

Schematic diagram of the CPERL inverter

with a different logic tree. The logic trees of basic gates such as AND, XOR, AND-OR are shown in Fig. 3. Fig. 4 shows the diagram of the CPERL inverter chain. Two nonoverlapping power-clock supplies (j1 and j2)

with 180 phase difference are used. The waveforms of the power-clock can be trapezoidal or triangular. A triangular waveform is used here for convenience. Fig. 5 shows the timing diagram of the CPERL inverter chain. IN(j1) in this gure means that the input signal IN is following the phase of j1 . When j1 rises, the authors assume IN which phase is no difference with j1 also rises, and INbar remains low. The transistors M9 and M11 turn on. BN1 is precharged to Vdd 7 Vth (Vth is the threshold voltage of the NMOS) and BN2 is still at low voltage. When the j1 and IN ramps down, M9 and M11 turn off, the bootstrapping nodes are isolated from the input and BN1 stores a high-voltage datum. j2 , which is used to transfer charge from power-clock supply then through turned-on transistor M1, ramps from 0 to Vdd . At the same time, BN1 is bootstrapped to a voltage higher than Vdd , due to the gate-to-channel capacitance of transistor M1, and turns on M1. Power-clock supply j2 charges the output node OUT in an adiabatic manner to Vdd , and drives the next stage in the phase of j2 . When j2 ramps down, OUT also ramps down and the charge stored on it is recovered to supply through the entire discharge process. The energy on the output node is fully recovered but not on the bootstrapping node. The following describes the bootstrapping nodes discharge process that saves the trapped charge.

Fig. 3 Logic trees of complementary pass-transistor using in CPERL gates

a AND b XOR c AND-OR
IEE Proc.-Comput. Digit. Tech., Vol. 149, No. 4, July 2002

Fig. 5

Timing diagram of the CPERL inverter chain

147

If the balanced voltage is lower than Vth , its voltage level remains the same. Thus, there is charge saved at most as Qsaved Vth Cshare 2

where Cshare is the total node capacitance participated in the charge-sharing process. It can be seen that the current I ows through the logic part of stage 2 due to chargesharing. This bootstrapping node discharge process is nonadiabatic. However, a portion of energy is saved from the energy dissipation in (1). 3
Fig. 6 Bootstrapping node discharge process

Circuit design and simulation results

2.2 Charge recycle in CPERL Consider the CPERL cascaded inverter chain given in Fig. 4. The Figure also shows the phase arrangement of the cascaded CPERL inverter chain. The bootstrapping node discharge process comprises two successive stages. This process is illustrated in Fig. 6. Only half of the circuit is shown for simplicity. The waveforms of the node voltages in Fig. 6 are shown in Fig. 7. During period t1 , it is assumed that node A is charged to high following j2 and BN2 is charged to Vdd 7 Vth . Then j2 ramps down and the logic part as the isolation switch of stage 2 turns off. Charge is trapped in BN2. During period t3 , j2 rises again. If A is low and A is high, M10 of stage 2 will turn on. The transistor M3 of stage 1 must turn on. Current will ow through M10 of stage 2, and M3 of stage 1 due to voltage drop. This chargesharing process will stop when the nodes reach a balanced voltage. The diode-connected transistor M5 of stage 1 adjusts the voltage in the following way: If the balanced voltage is higher than Vth , M5 of stage 1 will turn on until the balanced voltage is lower than Vth.

The schematic diagram of an 8-bit CPERL carry lookahead adder (CLA) is shown in Fig. 8. Four kinds of CPERL gates (AND, XOR, AND-OR and buffer) are needed in this adder design. The basic cell, depicted as a rectangle, consists of one AND gate and one AND-OR gate. Each stage of this CLA is driven by one phase power-clock lagging 180 of input signal. The amount of clock lines driven by power-clock supply generator is reduced. However, if the inputs are driven by conventional CMOS, the charge-discharge part of the propagate-and-generate signals (PG) generator must be constructed using the circuit given in Fig. 9, which can convert level signals to adiabatic pulses. The logic function part cannot be taken out from CPERL to form a simplied buffer, because CPERL needs a logic function part to act as isolation switches. To compare the power dissipation with conventional CMOS, NERL and the proposed logic, the authors simulated those circuits with HSPICE. Device models available for the TSMC 0.35 mm 1P4M CMOS technology were used for simulation. The peak voltage of the power-clock supply is 3.3 V. Bootstrapping NMOS transistor sizes were chosen to be large enough for correct bootstrapping function. The other transistors are chosen with the smallest size.

Fig. 7
148

Timing waveforms of node voltage during the discharge procedure

IEE Proc.-Comput. Digit. Tech., Vol. 149, No. 4, July 2002

Fig. 8

Schematic diagram of an 8-bit CPERL CLA

The W=L ratio of transistors M5 and M6 in Fig. 2 can be larger for higher operation frequency. An ideal powerclock generator is used in this simulation. Fig. 10 shows the power consumption against frequency of the 10-stage inverter chain of three different kinds of logic. The output load is 0.1 pF. In the Figure, it can be seen that the NERL dissipated 67% of energy dissipated in conventional CMOS at 125 MHz. The CPERL takes a further step in reducing the power dissipation to 48.8%. Table 1 lists the percentage of power dissipation of adiabatic inverter chains to conventional CMOS.

Fig. 11 gives a comparison of the power dissipation against operation frequency of the 8-bit CLAs. The result shows that CPERL can be more energy efcient than the NERL and conventional CMOS. At 125 MHz, conventional CMOS CLA, NERL CLA and CPERL CLA

Fig. 9

Charge-discharge part of PG generator

Fig. 10 chains

Power consumption against frequency for the inverter

149

IEE Proc.-Comput. Digit. Tech., Vol. 149, No. 4, July 2002

Table 1: Percentage of power dissipation for adiabatic inverter chains to conventional CMOS
10-stage inverter chain at 125 MHz Power dissipation, mW Percentage to CMOS CMOS 185.6 100% NERL 124.7 67.2% CPERL 90.52 48.8%

Fig. 12 Layout of an 8-bit CPERL CLA Fig. 11 Power consumption against frequency for 8-bit CLAs

consume 0.868 mW, 0.256 mW and 0.137 mW, respectively. Thus, CPERL CLA can save 84.2% of energy of CMOS CLA. An 8-bit CPERL CLA was designed using the TSMC 0.35 mm 1P4M CMOS technology. The layout of the 8-bit

CPERL CLA is shown in Fig. 12. The waveforms of postlayout simulation of the 8-bit CPERL CLA are shown in Fig. 13. A counting sequence A8 . . . A1 00000000, 00000001, 00000010, . . . , 11111111 and B8 . . . B1 00000001 is assigned as the test patterns. The output results are Cout.S8.S1 000000001, 0000000010, 000000011, . . . , 100000000. The post-layout simulation results show

Fig. 13
150

Waveforms of post-layout simulation of an 8-bit CPERL CLA

IEE Proc.-Comput. Digit. Tech., Vol. 149, No. 4, July 2002

that this circuit can operate at 100 MHz and its function is still correct. 4 Conclusion

A CPERL for low-power applications is presented. It facilitates efcient energy recovery and low-power consumption using the bootstrapping technique to obtain efcient energy utilisation and reduce the nonadiabatic energy loss dissipated in NERL. In the inverter-chain case, simulation results show that CPERL has higher energy efciency than NERL. NERL dissipates 67.2% of the conventional CMOS power and CPERL dissipates only 48.8%. In the CLA case, NERL saves 71% of the conventional CMOS power and CPERL saves up to 84.2%. The authors also designed an 8-bit CLA with CPERL using the TSMC 0.35 mm 1P4M CMOS technology. The operation of this CLA has been veried. 5 Acknowledgment

This work was supported by the National Science Council of Taiwan, under grant number NSC90-2215-E-005-002, and also by the Meng-Yao Chip Center. 6 References

1 ATHAS, W., SVENSSON, L., KOLLER, J.G., TZARTZANIS, N., and CHOU, E.Y.-C.: Low-power digital systems based on adiabaticswitching principles, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 1994, 2, (4), pp. 398407 2 LIM, J., KIM, D.G., and CHAE, S.I.: nMOS reversible energy recovery logic for ultra-low-energy applications, IEEE J. Solid-State Circuits, 2000, 35, (6), pp. 865875

3 MOON, Y., and JEONG, D.K.: An efcient charge recovery logic, IEEE J. Solid-State Circuits, 1996, 31, (4), pp. 514522 4 OKLOBDZIJA, V.G., and MAKSIMOVIC, D.: Pass-transistor adiabatic logic using single power-clock supply, IEEE Trans. Circuit Syst. II Analog. Digit. Signal Process., 1997, 44, (10), pp. 842846 5 LIU, F., and LAU, K.T.: Pass-transistor adiabatic logic with NMOS pull-down conguration, Electron. Lett., 1998, 34, (8), pp. 739741 6 LO, C.-K., and CHAN, P.C.H.: An adiabatic differential logic for lowpower digital systems, IEEE Trans. Circuits and Systems II Analog. Digit. Signal Process., 1999, 46, (9), pp. 12451250 7 MAKSIMOVIC, D., OKLOBDZIJA, V.G., NIKOLIC, B., and CURRENT, K.W.: Clocked CMOS adiabatic logic with integrated single-phase power-clock supply, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2000, 8, (4), pp. 460463 8 DENKER, J.S.: A review of adiabatic computing. IEEE Symposium Low Power Electronics Digest of Technical Papers, October 1994, pp. 9497 9 TZARTZANIS, N., and ATHAS, W.: Clock-powered CMOS: A hybrid adiabatic logic style for power-efcient computing. 20th Anniversary Conference on Advanced Research in VLSI, 1999, pp. 137151 10 KIM, C., YOO, S.-M., and KANG, S.-M.: Low-power adiabatic computing with nmos energy recovery logic, Electron. Lett., 2000, 36, (16), pp. 13491350 11 SUVAKOVIC, D., and SALAMA, C.: Two phase non-overlapping clock adiabatic differential cascode voltage switch logic (ADCVSL). ISSCC Digest of Tech. Papers, 2000, pp. 364365 12 KNAPP, M.C., KINDLMANN, P.J., and PAPAEFTHYMIOU, M.C.: Implementing and evaluating adiabatic arithmetic units. Proc. IEEE Custom Integrated Circuits Conference, 1996, pp. 115118 13 DE, W.K., and MEINDL, J.D.: Complementary adiabatic and fully adiabatic MOS logic families for gigascale integration. Proceedings of the International Solid-State Circuits Conf., 1996, San Francisco, CA, USA, pp. 298299 14 NG, K.W., and LAU, K.T.: A novel adiabatic register le design, J. Circuits Syst.Comput., 2000, 10, (1 & 2), pp. 6776 15 DICKINSON, A.G., and DENKER, J.S.: Adiabatic dynamic logic, IEEE J. Solid-State Circuits, 1995, 30, (3), pp. 311315 16 LAW, C.F., ROFAIL, S.S., and YEO, K.S.: A low-power circuit implementation for partial-product addition using pass-transistor logic, IEE Proc., Circuits, Devices Syst., 1999, 146, (3), pp. 124129 17 SOUDRIS, D., PAVLIDIS, V., and THANAILAKIS, A.: Designing low-power energy recovery adders based on pass transistor logic. 8th IEEE International Conference on Electronics, circuits and systems, 2001, 2, pp. 777780

IEE Proc.-Comput. Digit. Tech., Vol. 149, No. 4, July 2002

151