Complementary MetalOxideSemiconductor

(CMOS) is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS sensor), data converters, and highly integrated transceivers for many types of communication. Frank Wanlass patented CMOS in 1967. CMOS is also sometimes referred to as complementary-symmetry metaloxide semiconductor (or COS-MOS). The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn when the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic. CMOS also allows a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most used technology to be implemented in VLSI chips.

Twin-tub CMOS process

A twin-tub process is a logical extension of p-well and n-well approaches. The process starts with a substrate of high resistivity n-type material and then both p-well and n-well regions are created. This process it is possible to preserve the performance of n-transistors without compromising p-transistors. Doping can be controlled easily and latch-up is also achieved as the twin-tub process allows separate optimization of n and p-transistors. An inverter arrangement with twintub is shown figure. The twin-tub CMOS technology provides the basic for separate optimization of ptype and n-type transistor making it possible for threshold voltage, body effect and gain associated with n and p-devices to be independently optimized.

N-WELL PROCESS: The n-well CMOS process starts with a moderately doped (with impurity concentration typically less than 1015 cm-3) p-type silicon substrate. Then, an initial oxide layer is grown on the entire surface. The first lithographic mask defines the n-well region. Donor atoms, usually phosphorus, are implanted through this window in the oxide. Once the nwell is created, the active areas of the nMOS and pMOS transistors can be defined. Figures 2.5 through 2.10 illustrate the significant milestones that occur during the fabrication process of a CMOS inverter.

Following the creation of the n-well region, a thick field oxide is grown in the areas surrounding the transistor active regions, and a thin gate oxide is grown on top of the active regions. The thickness and the quality of the gate oxide are two of the most critical fabrication parameters, since they strongly affect the operational characteristics of the MOS transistor, as well as its long-term reliability The polysilicon layer is deposited using chemical vapor deposition (CVD) and patterned by dry (plasma) etching. The created polysilicon lines will function as the gate electrodes of the nMOS and the pMOS transistors and their interconnects. Also, the polysilicon gates act as self-aligned masks for the source and drain implantations that follow this step. Using a set of two masks, the n+ and p+ regions are implanted into the substrate and into the n- well, respectively. Also, the ohmic contacts to the substrate and to the n-well are implanted in this process step. An insulating silicon dioxide layer is deposited over the entire wafer using CVD. Then, the contacts are defined and etched away to expose the silicon or polysilicon contact windows. These contact windows are necessary to complete the circuit interconnections using the metal layer, which is patterned in the next step.

Metal (aluminum) is deposited over the entire chip surface using metal evaporation, and the metal lines are patterned through etching. Since the wafer surface is non-planar, the quality and the integrity of the metal lines created in this step are very critical and are ultimately essential for circuit reliability. The composite layout and the resulting cross-sectional view of the chip, showing one nMOS and one pMOS transistor (built-in n-well), the polysilicon and metal interconnections. The final step is to deposit the passivation layer (for protection) over the chip, except for wire-bonding pad areas. The patterning process by the use of a succession of masks and process steps is conceptually summarized in Fig. 2.11. It is seen that a series of masking steps must be sequentially performed for the desired patterns to be created on the wafer surface. An example of the end result of this sequence is shown as a crosssection on the right.

P-WELL PROCESS: The substrate is N-type. The N-channel device is built into a P-type well within the parent N-type substrate. The P-channel device is built directly on the substrate. Steps 1: P-well on N-substrate N-type substrate. Oxidation, and mask (MASK 1) to create P-well (4-5m deep). P-well doping. P-well acts as a substrate for nMOS device. The two areas are isolated using thick field oxide.

Step 2: Polysilicon Gate Formation Remove P-well definition oxide. Grow thick field oxide Pattern (MASK 2) to expose nMOS and pMOS active region. Grow thin layer of SiO2 gate oxide, over the entire chip surface. Deposit polysilicon on top of gate oxide to form gate structure. Pattern poly on gate oxide (MASK 3)

nMOS P+ Source/Drain diffusion-self-aligned to Poly gate implant P+ nMOS S/D region (MASK 4)

pMOS N+ Source/Drain diffusion-self-aligned to poly gate implant N+ pMOS S/D regions (MASK 5 often the inverse of MASK 4)

pMOS N+ Source/Drain diffusion, contact holes and metallization Oxide and pattern for contact holes (MASK 6) Deposit metal and pattern (MASK 7) Passivation oxide and pattern bonding pads (MASK 8) P-well acts as substrate for nMOS devices. Two separate substrates: requires two separate substrate connections. Definition of substrate connection areas can be included in MASK 4/MASK 5