2011

VLSI DESIGN LAB

Prof. Vijayarani katkam S.L.N. Engineering College, Raichur.

2011-12

VLSI LAB

VII Sem EC

SLN COLLEGE OF ENGINEERING

DEPARTMENT OF

Electronics and Communication Engineering

E&CE Dept,SLNCE

VLSI LAB

VII Sem EC

VLSI LABORATORY MANUAL (06ESL77)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

E&CE Dept,SLNCE

VLSI LAB
Subject Code : 06ECL77 No. of Practical Hrs/Week : 03 Total no. of Practical Hrs. : 42 IA Marks Exam Hours Exam Marks

VII Sem EC
: 25 : 03 : 50

EXPERIMENTS LIST (ACCORDING TO VTU SYLLABUS)

PART - A DIGITAL DESIGN

ASIC-DIGITAL DESIGN FLOW

1. Write Verilog Code for the following circuits and their Test Bench for verification, observe the waveform and synthesise the code with technological library with given Constraints*. Do the initial timing verification with gate level simulation.

i. ii. iii. iv. v. vi. vii. viii.

An inverter A Buffer Transmission Gate Basic/universal gates Flip flop -RS, D, JK, MS, T Serial & Parallel adder 4-bit counter [Synchronous and Asynchronous counter] Successive approximation register [SAR]

* An appropriate constraint should be given

PART - B

E&CE Dept,SLNCE

VLSI LAB
ANALOG DESIGN

VII Sem EC

Analog Design Flow 1. Design an Inverter with given specifications*, completing the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design e. Verify & Optimize for Time, Power and Area to the given constraint***

2. Design the following circuits with given specifications*, completing the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design. i) A Single Stage differential amplifier ii) Common source and Common Drain amplifier

E&CE Dept,SLNCE

VLSI LAB VII Sem EC 3. Design an op-amp with given specification* using given differential amplifier Common source and Common Drain amplifier in library** and completing the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii). AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design. 4. Design a 4 bit R-2R based DAC for the given specification and completing the design flow mentioned using given op-amp in the library**. a. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design

5. For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and verify the functionality by completing ASIC Design FLOW.

INDEX 6 E&CE Dept,SLNCE

VLSI LAB SL.NO 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5

NAME OF THE EXPERIMENT AN INVERTER A BUFFER TRANSMISSION GATE BASIC/UNVERISAL GATES FLIP-FLOPS SR, D, JK & T SERIAL & PARALLEL ADDER 4 BIT COUNTERS (SYNCHRONOUS & ASYNCHRONOUS )

VII Sem EC PAGE NO

Successive approximation register [SAR]

ADDITIONAL EXPERIMENTS RING COUNTER JHONSON COUNTER HALF ADDER &FULL ADDER PART-B AN INVERTER SINGLE STAGE AMPLIFIER COMMON SOURCE AMPLIFIER COMMON DRAIN AMPLIFIER 4-BIT R2R BASED ON DAC

PART A DIGITAL DESIGN

7 E&CE Dept,SLNCE

VLSI LAB

VII Sem EC

It is one of most popular software tool used to synthesize VHDL code. This tool Includes many steps. To make user feel comfortable with the tool the steps are given below: Double click on Project navigator. (Assumed icon is present on desktop). Select NEW PROJECT in FILE MENU. Enter following details as per your convenience Project name : sample Project location : C:\example Top level module : HDL In NEW PROJECT dropdown Dialog box, Choose your appropriate device specification. Example is given below: Device family : Spartan2 Device : xc2s200 Package : PQ208 TOP Level Module : HDL Synthesis Tool : XST Simulation : Modelsim / others Generate sim lang : VHDL In source window right click on specification, select new source Enter the following details Entity: sample Architecture : Behavioral Enter the input and output port and modes. This will create sample.VHDL source file. Click Next and finish the initial Project preparation. Double click on synthesis. If error occurs edit and correct VHDL code. Double click on Lunch modelsim (or any equivalent simulator if you are using) for functional simulation of your design.

EXPERIMENT NO.1
8 E&CE Dept,SLNCE

VLSI LAB WRITE VERILOG CODE TO REALIZE AN INVERTER AIM: Simulation and realization of an inverter. LOGIC SYMBOL & TRUTH TABLE
Symbol

VII Sem EC

Truth Table A 0 Q 1 0

Inverter or NOT Gate

Boolean Expression Q = not A

VERILOG CODE
module inv (A,Q); input A; output Q; assign Q=~A; endmodule

E&CE Dept,SLNCE

VLSI LAB

VII Sem EC

EXPERIMENT NO.2
WRITE VERILOG CODE TO REALIZE A BUFFER AIM: Simulation and realization of an tristate buffer. LOGIC SYMBOL & TRUTH TABLE
Symbol En 1 1 0
Tri-state Buffer

Truth Table X 0 1 0 1 Y 0 1 Hi-Z Hi-Z

Read as Output = Input if Enable is e

Symbol En 0 0 1
Tri-state Buffer

Truth Table X 0 1 0 1 Y 0 1 Hi-Z Hi-Z

Read as Output = Input if Enable is NOT equal to "1"

module buff0(x,en,y); input x,en; output y; reg y; always@(x,en) begin if(en==0) y=x; else y=1'bz; end endmodule

module buff1(x,en,y); input x,en; output y; reg y; always@(x,en) begin if(en) y=x; else y=1'bz; end endmodule
10 E&CE Dept,SLNCE

VLSI LAB

VII Sem EC

module buffnotif0(x,en,y); input x,en; output y; reg y; always@(x,en) begin if(en==0) y=~(x); else y=1'bz; end endmodule

module bufnot0(x,en,y); input x,en; output y; reg y; always@(x,en) begin if(en==0) y=~(x); else y=1'bz; end endmodule

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E&CE Dept,SLNCE

VLSI LAB

VII Sem EC

EXPERIMENT NO. 3
WRITE VERILOG CODE TO REALIZE TRANSMISSION GATE AIM: Simulation and realization of transmission gates.

Logic symbol a dir enb module trans(dir,enb, a,b); input dir,enb; inout [7:0] a,b; wire [7:0]a,b; assign a=(enb==1'b0 && dir==1'b1)?b:8'hz; assign b=(enb==1'b0 && dir==1'b0)?a:8'hz; endmodule trans b

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E&CE Dept,SLNCE

VLSI LAB

VII Sem EC

EXPERIMENT NO. 4
WRITE VERILOG CODE TO REALIZE ALL LOGIC GATES AIM: Simulation and realization of all logic gates. Truth table with symbols

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E&CE Dept,SLNCE

VLSI LAB LOGIC SYMBOLS c a b LOGIC GATES e f g h i d

VII Sem EC

Truth table Basic gates: a 0 0 1 1 b 0 1 0 1 c 0 0 0 1 d 0 1 1 1 e 1 1 0 0 f 1 1 1 0 g 1 0 0 0 h 0 1 1 0 i 1 0 0 1

VERILOG CODE module allgate ( a, b, y ); input a,b; output [1:6] y; assign y[1]= a & b; assign y[2]= a | b, assign y[3]= ~a , assign y[4]= ~(a & b), assign y[5]= ~(a | b), assign y[6]= a ^ b; endmodule Procedure to view output on TEST BENCH

RESULT: The logic gates design have been realized and simulated using VERILOG codes.

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E&CE Dept,SLNCE

VLSI LAB

VII Sem EC

EXPERIMENT NO.5
AIM: Develop the VERILOG code for the following flipflop: T, D, SR, JK. T FLIPFLOP

T CLK Truth table

T 0 1 X X

T ff

Q Qb

Clk 1 1 No +ve edge X

q q qb Previous state 0

VERILOG CODE

module tff(t,clk, q,qb); input t, clk; output q,qb; reg q; always@(posedge clk) begin q=~t; end assign qb=~q; endmodule

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E&CE Dept,SLNCE

VLSI LAB

VII Sem EC

Rising edge Output D FLIPFLOP Logic symbol d q clk D FF qb

VERILOG CODE

module dff(d,clk, q,qb); input d,clk; output q,qb; reg q,qb; always@(posedge clk) begin q=d; assign qb=~q; end endmodule Truth table
clk X 1 1 d 1 1 0 q 1 1 0 qb 0 0 1

Output at rising edge

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E&CE Dept,SLNCE

VLSI LAB SR FLIPFLOP Logic symbol

VII Sem EC

Truth table
Clk s r 1 0 0 1 0 1 1 1 0 VERILOG CODE 1 1 1 q Q 0 1 Z qb Qbprevious 1 0 X clk S Qb R Sr ff

srff using case:

Srff using if-else: module srff(s,r,clk, q,qb); input s,r,clk; output q,qb; reg q,qb; always@(posedge clk) begin if(s==0&&r==0) q=q; else if(s==0&&r==1) q=1'b0; else if(s==1&&r==0) q=1'b1; else if(s==1&&r==1) q=1'bZ; end assign qb=~q; endmodule

module srff(sr, clk, q,qb); input [1:0] sr; input clk; output q,qb; reg q,qb; always@(posedge clk) begin case (sr) 2'b00:q=q; 2'b01:q=1'b0; 2'b10:q=1'b1; 2'b11:q=1'bZ; endcase end assign qb=~q; endmodule

S output

JK FLIPFLOP 17 E&CE Dept,SLNCE

VLSI LAB Logic symbol

VII Sem EC

Truth table
Clk 1 Q Qb Previou state s 1 1 Jk_ff 0 using 1 case:0 1 1 0 1 0 1 1 1 Qb Q module jkff(jk, clk, q,qb); J 0 K 0 j Qb k

clk

jk_ff using if-else: module jk_ff(j,k,clk, q,qb); input j,k,clk; output q,qb; reg q,qb; always@(posedge clk) begin if(j==0&&k==0) q=q; else if(j==0&&k==1) q=1'b0; else if(j==1&&k==0) q=1'b1; else if(j==1&&k==1) q=~q; end assign qb=~q; endmodule

input [1:0] jk; input clk; output q,qb; reg q,qb; always@(posedge clk) begin case (jk) 2'b00:q=q; 2'b01:q=1'b0; 2'b10:q=1'b1; 2'b11:q=~q; endcase end assign qb=~q; endmodule

Output(when input 00 and rising edge) RESULT: Flip-flop operations have been realized and simulated using VERILOG codes

EXPERIMENT NO.6
18 E&CE Dept,SLNCE

VLSI LAB

VII Sem EC

Aim :write a verilog code for serial and parallel adder

6@:serial adder Module serialadder(a,b,clk,reset, en,result); input a,b,clk,reset,en; output [3:0] result; reg [3:0]y; reg carry; always@(posedge clk) begin if(reset==1) begin y=4'b0; carry=1'b0; end else if(en) begin y[3]=y[2]; y[2]=y[1]; y[1]=y[0]; {carry, y[0]}=a+b+carry; end end assign result=y; endmodule

6,b:parallel adder

module paralleladder(a,b,c,y); input [3:0]a,b; output [4:0]y; input c; assign y=a+b+c; endmodule

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E&CE Dept,SLNCE

VLSI LAB

VII Sem EC

a[3:0] a b clk en reset

Serial adder

b[3:0] result[3:0] C

Parallel adder

y[4:0]

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E&CE Dept,SLNCE

VLSI LAB

VII Sem EC

EXPERIMENT NO.7
AIM: Design 4 bit Binary counter( Synchronous and Asynchronous ).

BINARY UP COUNTER(Synchronous & Asynchronous)

Logic symbol clk rst Binary counter qout(3 to 0)

Truth table
Clk X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rst 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Qout 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

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E&CE Dept,SLNCE

VLSI LAB synchronous asynchronous

VII Sem EC

module synup(clk,rst, cout); input clk,rst; output [3:0]cout; reg [3:0]temp; always @(posedge clk) begin if (rst) temp =4'b0000; else temp=temp+1; end assign cout=temp; endmodule

module asynup(clk,rst, cout); input clk,rst; output [3:0]cout; reg [3:0]temp; always @(posedge rst or posedge clk) begin if (rst) temp =4'b0000; else temp=temp+1; end assign cout=temp; endmodule

Output 0000 BINARY DOWN COUNTER(Synchronous & Asynchronous) Logic symbol clk rst Binary counter cout(3 to 0)

Output 1111

Truth table
Clk Rst 22 cout E&CE Dept,SLNCE

VLSI LAB X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 synchronous

VII Sem EC 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 asynchronous

module syndown(clk,rst, cout); input clk,rst; output [3:0]cout; reg [3:0]temp; always @(posedge clk) begin if (rst) temp =4'b1111; else temp=temp-1; end assign cout=temp; endmodule

module asyndown(clk,rst, cout); input clk,rst; output [3:0]cout; reg [3:0]temp; always @(posedge rst or posedge clk) begin if (rst) temp =4'b1111; else temp=temp-1; end assign cout=temp; endmodule

BCD UP COUNTER(SYNC & ASYNC)

Logic symbol clk rst Bcd counter count(3 downto 0)

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E&CE Dept,SLNCE

VLSI LAB

VII Sem EC

Truth table
Rst 1 0 0 0 0 0 0 0 0 0 Clk X 1 1 1 1 1 1 1 1 1 Count(q) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

Synchronous module bcdup(clk,rst, count); input clk,rst; output [3:0] count; reg[3:0]temp; always@(posedge clk) begin if(rst==1) temp=4'b0000; else temp=temp+1; if(temp>4'b1001) temp=4'b0000; end assign count=temp; endmodule

asynchronous module bcdup(clk,rst, count); input clk,rst; output [3:0] count; reg[3:0]temp; always@(posedge clk or posedge rst) begin if(rst==1) temp=4'b0000; else temp=temp+1; if(temp>4'b1001) temp=4'b0000; end assign count=temp; endmodule

BCD DOWN COUNTER(SYNC & ASYNC)

Logic symbol 24 E&CE Dept,SLNCE

VLSI LAB clk rst Bcd counter count(3 downto 0)

VII Sem EC

Truth table
Rst 1 0 0 0 0 0 0 0 0 0 Clk X 1 1 1 1 1 1 1 1 1 Count(q) 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000

Synchronous module bcddown(clk,rst, count); input clk,rst; output [3:0] count; reg[3:0]temp; always@(posedge clk) begin if(rst==1) temp=4'b1001; else temp=temp-1; if(temp>=4'b1001) temp=4'b1001; end assign count=temp; endmodule

asynchronous module bcddown(clk,rst, count); input clk,rst; output [3:0] count; reg[3:0]temp; always@(posedge clk or posedge rst) begin if(rst==1) temp=4'b1001; else temp=temp-1; if(temp>=4'b1001) temp=4'b1001; end assign count=temp; endmodule

RESULT: Asynchronous and Synchronous counters have been realized and simulated using VERILOG codes.

ADDITIONAL EXPERIMENTS
25 E&CE Dept,SLNCE

VLSI LAB

VII Sem EC

EXPERIMENT NO.9&10
Aim:write a verilog code for Ring & Johnson counter TRUTH TABLE

clk
CLK RESET COUT RING X 1 0001 1 0 1000 1 0 0100 1 0 0010 1 0 0001 1 0 1000 1 0 0100 1 0 0010 1 0 0001 COUT JOHNSON 0000 0001 0011 0111 1111 1110 1100 1000 0000

reset

Ring & Johnson counter

module ring (clk,rst, cout); input clk,rst; output [3:0]cout; reg [3:0]q; assign cout=q; always @(posedge clk) begin if (rst==1) q=4b0001; else q={q[0], q[3:1]}; end endmodule

module johnson(clk,rst, cout); input clk,rst; output [3:0] cout; reg [3:0] q; assign cout=q; always@(posedge clk) begin if(rst==1) q=4'b0; else q={~q[0],q[3:1]}; end endmodule

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E&CE Dept,SLNCE

VLSI LAB

VII Sem EC

EXPERIMENT NO.11,@
AIM: Write a HDL code to describe the functions of Half adder, an (a) HALF ADDER TRUTH TABLE BASIC GATES INPUTS A 0 0 1 1 B 0 1 0 1 OUTPUTS S 0 1 1 0 C 0 0 0 1

BOOLEAN EXPRESSIONS: S=A B C=A B VERILOG CODE module ha ( a, b, s, c) input a, b; output s, c; assign s= a ^ b; assign c= a & b; endmodule

EXPERIMENT NO.11 ,b
AIM: Write VERILOG code to describe the functions of a full Adder Logic symbol: a b c FULL ADDER Sum

Cout

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E&CE Dept,SLNCE

VLSI LAB

VII Sem EC

Truth table
INPUTS a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 cin 0 1 0 1 0 1 0 1 OUTPUTS SUM 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1

VERILOG CODE module fa (x,y,z,cout,sum); input x,y,z; output cout,sum; wire P1,P2,P3; xor (x,y,p1); and (x,y,p2); xor (p1,z,sum); and (p1,z,p3); or (p2,p3,cout); endmodule

Sum output carryoutput RESULT: Full adder have been realized and simulated

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E&CE Dept,SLNCE