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University of Florida

EEL 3701 -- Spring 2011 ECE Dept., Dr. Gugel LAB 2: Logic Design and Quartus II
Part II. Pre-lab: 1. Using the same logic equation as before, select the activation levels (signal definitions) to create a circuit that will have the minimum number of gates possible. Draw this design on paper first and try different combinations of signal definitions to get the minimal circuit design. Note3: As in the earlier design, implement the equation as it is. DO NOT transform or minimize the equation. You are only allowed to select the activation levels to minimize the design. 2. Enter & simulate your new design in Quartus. For simulation, create a waveform/vector file (.vwf) as before and use the timing simulator. 3. Create a voltage table from the circuit and using your new signal definitions create a logic truth table. Verify your logic truth table matches the logic equation shown in Part I. Note4: You are allowed to use any gate that you have in your tool box. Note5: Use the gates in the primitives/logic library which are equivalent to the gates you used in your design. Part I and Part II. In-lab: 1. Show your TA your pre-lab work for both Parts I and II. For full credit, you must be able to explain your work. You must have this work completed before lab or you will not be allowed in lab! 2. Email your designs to your TA. The subject line MUST include the lab number, section number and your name in the following order: Lab1 2960 Jose Cuervo. You name must also be inside the design file. Email only the schematic capture files for Parts I and II. 3. Build your circuits from Part I and Part II on your breadboard. Attach switches to the inputs and LEDs as needed to the outputs

Objectives: To understand the operation of Quartus II as a digital design and simulation tool. To learn how to realize a digital design with discrete components (ICs, LEDs, switches, and resistors). Materials: Hardware (ICs, LED's, etc.) your lab kit you received in Lab #1. Pinout documentation for all TTL devices you will be using in lab. The Quartus II tutorial. Go through the basic tutorials outside of lab. Part I. Pre-lab: 1. Download and install the Quartus II software. Perform the Quartus II tutorial. 2. Given the following logic equation: Z = (A+B) * (C + D) Signal Definitions are A.H, B.L ,C.H, D.L and Z.L. Draw (on paper) a circuit diagram implementing Z, using the minimum number of gates. Use only the following types of gates: 7400, 7402, 7404. Note1: Implement the equation as it is. DO NOT transform or minimize the equation. 3. Create a logic truth table for the logic equation. 4. Create a voltage table for the logic equation. 5. Enter the design into Quartus II using the Graphics Editor. Note2: Use the gates in the primitives/logic library which are equivalent to the gates you used in your design. For example, 7400 is equivalent to both the nand2 and bor2. 7402 is equivalent to nor2 and band2. 7404 is equivalent to not. 6. Create a waveform/vector file (.vwf file) and perform a timing simulation (not a functional simulation) of the design. Question: is the Quartus II simulation a logic simulation or voltage simulation?

University of Florida

EEL 3701 -- Spring 2011 ECE Dept., Dr. Gugel LAB 2: Logic Design and Quartus II In-lab Quiz Details:
After completing Parts I & II, you will be given an unknown function (similar to the one given in the pre-lab section). (a) Draw (on paper) a circuit diagram implementing the function, using the minimum number of gates. (b) Create a logic table for the new equation. (c) Create a voltage table for the equation. (d) Enter the design into Quartus II using the Graphics Editor. (e) Create a .vwf file and perform a timing simulation of the design. (f) Wire up the new design and verify that it functions as expected in Quartus.

4. Demonstrate to your TA the operation of the circuits by switching through various inputs and comparing the hardware results to those obtained in the pre-lab simulations.

Point Break Down: Pre-lab Part I. Truth Table, Voltage Table, Circuit & Simulation results. 10% Pre-lab Part II. Truth Table, Voltage Table, Circuit & Simulation results. 10% In-lab Part I Demo. breadboarded circuit functional demonstration. 10% In-lab Part II Demo. breadboarded circuit functional demonstration. 10% Final In Lab Quiz, 60% Total: - Truth Table, Voltage Table, paper circuit design. 10% - Quartus circuit design & simulation for Logic Equation given in Lab. 20% - Breadboard circuit construction & functional demonstration for Logic Equation given in Lab. 30%

Final Notes: You should wire Pre-Lab Parts I & II at home before attending lab. Otherwise, you will not have enough time to finish lab. All inputs must come from switches and all outputs must go to LEDs. Upon leaving lab, all breadboard circuits must be removed from your breadboard such that the breadboard is completely blank. Time permitting, finish building your CPLD break-out board at the end of lab.

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