The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, December 6-9,2004

MODIFIED EULER PATH RULE FOR MOS LAYOUT MINIMIZATION

Shun- Wen Cheng
tku, Taipei, Taiwan

Kou-Hsing Cneng
National Central University

swcheng@ieee.org

Taiwan

Abstract- Get minimal layout areas without diffusion breaks and then keep good electrical characteristics are useful for IC design. This work changes the viewpoint of constructing Euler path on IC circuit and puts some basic layout ideas into systematic approach. The study provides another way to constructing the Euler Path on MOS circuits. The proposed method produces a more compact layout with less parasitic capacitance and contact.
D

Index Term - Layout minimization, optimal layout, Euler

path, diffusion break, series-parallel graph, fully customer design, CMOS, VLSI design.
Figure 1. A NMOS circuit and its corresponding

hypergraph.

1. INTRODUCTION
An Euler Path in a graph is defined as a path through all nodes in the graph, such that each edge in the edge is only visited once [I], [9]. In many CMOS designs, the basic building blocks are complex MOS gates with many transistors under the Euler Path rule. The circuit diagrams for the complex gates arise from Boolean formulas either by handcraft design or with the aid of a silicon complier.

Figure 2. Transistor chain

Uehara and van Cleemput formulate an optimization problem on sets of series-parallel graphs that captures an important aspect of the layout optimization, the minimization of their width [8]. Figure 1 shows a NMOS schematic of a function. It has the optimal electrical characteristics in all the feasible structures. The output terminal only connects one transistor of the circuit, the parasitic capacitance of the terminal is reduced to minimum; the ground source connects three transistors; and the internal nodes and their parasitic capacitance are reduced to minimum [9].

Figure 3. Transistor chains wt merge terminals. ih

In the layout style, consider the NMOS schematic is arranged in a row, with the channel terminals of adjacent transistors facing each other, as displayed in Fig. 2. Chaining the sources and drains of neighboring transistors when they are electrically equivalent can minimize the width of each cell. If the two diffusion areas are not electrically equivalent, then a break in the diffusion is required. As shown in Fig. 3, this break would cause the width of the cell to increase.

Conventionally the goal of +is step is to find an ordering of the transistor gates such that a minimum number of diffusion breaks are needed [PI. Engineers also can reorder the signal to eliminate the breaks in some cases [2], [3], [5]. But the good electrical characteristics often lose at the time. This study discusses how to get a minimal layout area without diffusion breaks but keep good electrical characteristics. The paper is organized as follows. Section 2 briefly introduces the basic concept of series-parallel graph. Then an improved simplification method is given and discussed in Section 3. Finally conclude the major findings and outline the future work.

0-7803-8660-4/04/$20.0002004 IEEE

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GI

G2

(a)

23 Q
(b)GlaG2

(c) G2 a GI (d) GI n G2 (=G2 n GI)

Figure 4. Series-Parailel Graph

Q
G1

G2 la) ,, @)GI aG2 (c) G2 a GI (d) GI A G2 (=GZ n G I ) Figure 5. Constructing Euler path by adding a duplicated connection on the neighbor edge of the circle. (T. Lengauer and R. Muller, 1988 [4].)

s y

@ ._

GI

G2
(b) GI a G2 (c) G2 (r GI (d) GI A G2 (- G2 n GI) figure 6. Constructing Euler path by adding a duplicated connection on the circle

(a)

II. Series-Parallel Graph

The author concerns on series-parallel network, because the series connection implementing logicalAND and the parallel connection implementing logicalOR, correspond to Boolean function. As shown in .Fig. 4(a), GI and G2 are two basic principal types of seriesparallel graph. They have no Euler Path. Fig. (b), (c) and (d) are modular graphs of GI and G2. In a related

paper of 1988 T. Lengauer and R. Muller [4], they proposed that if the network contains n separations, implies n duplications is necessary, Fig. 5 depicts their constructing styles. It shows that we can constmct an Euler path by adding a duplicated connection on the neighbor edge of the circle. Figure 6 displays altemative route to construct an Euler path. It adds a duplicated connection on the circle. This method is often seen in the textbooks of discrete mathematics [I].

542

B D

Q@ (0 3
D D
GI
G2

(a)

(b) GI a GZ (c)G2aGI (d) GI n G2 (= GZ n GI) Figure 7. First number the Series-Parallel Graph.

G1

G2
(a)

(b) GI a G2 (c) G2 o GI (d) G I n G2 (= G2 n GI) Figure 8. The proposed unique simplificationmethod for MOS network.

?
BA
AC

I . IMPROVED D AN SI~~PLIFICATION METHOD

A B C
D E F G

Maybe the traditional ideas of discrete mathematics limit the viewpoint of layout minimization problem. The concepts of the proposed method are shown in Fig. 7 and Fig. 8.Number the circuit first, and then expand the circle to eliminate the separation. The logic significance of Fig. 7 and Fig. 8 on MOS transistor network is equivalent. As shown in Fig. 8, this is another choice of constructing an Euler path. The proposed concept is expanding the circle, not only adding. The rest part of deduction is continuously using any previous methods [2], [3], [4],.[5], [ 6 ] ,[8]. The layout of Figure 9 is small than Fig. 3. Compare Fig. 9 with Fig. IO, the transistor count is same. Both they have no diffusion break, both they contain one more transistor, and both they have three transistors to connect the ground source. But Fig. 10 has a more compact layout with less parasitic capacitance and contact.

Figure 9. Transistor chain with duplicated transistors [4]

BA

AC

Figure 10. The proposed method keeps good electrical characteristicsand gets a minimal layout.

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(a) Conventional schematic. @) The proposed schematic. Figure 11. The basic unit of Series-Parallel Graph.

Figure 14. Second level simplification hom Fig.

W.
The layout comparisons are shown in Table 1, they present all the layout of the proposed schematic are less than the conventional ones. Due to small parasitic capacitances between poly gates, the propagation delay is smaller than conventional circuit. If the width size of MOS is quite large, gate bending may further reduce the layout size [7]. The size rule of the minimum space between two poly gates on diffision influences the size of the proposed layout.

(a) Conventional layout. @)The proposed layout. Figure 12. Layout comparisc by TSMC 0 . 6 ~CMOS 1 process

IV.CONCLUDING REMARK
Figure 14 displays the second level simplification; its worth needs to further analysis. This work changes the viewpoint of constructing Euler path on IC circuit and puts some basic layout ideas into systematic approach. The method makes a more compact layout with less parasitic capacitance and contact. The study provides another way to constructing the Euler Path on MOS circuits.

......... .

.................

... ....:

.................

~~

...............................

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(a) Convenlional layout. @)The proposed layout. Figure 13. Layout companson by UMC O.5um CMOS process
[I]

REFERENCES
J.L. Moll, A. Kandel and T.P. Baker,Discrete Mathematics for Compufer Scienfisfs & Mnthemoficians. 2nd Ed., Reading:
Rsntiss-Hall, 1987.

I Conventional layout I
TSMC 0 . 6 ~ 7.9pmx3.55pm IP3M CMOS (= 28.045 pm) * . ,

Proposed layout 8.4pmx2.8pm (= 2x52 P)

pa--+=

TSMC 0.35P 4.95pmx2.15pm .. .. . .. , (= 10.6425 pm)

TSMC 0,25w 3.55px1.47pm IPSM (= 5.2185 pm)
prOEeSs

5.6pX1.7~ (=9.52 pm) 3.86pnX1.27pm (=4.9022 pm)

Table 1. Layout comparison

Figure 11 shows the correspond circuit of basic unit of series-parallel graph. Fig. 12 and Fig. 13 are their layout of TSMC 0.6pm lP3M CMOS process and UMC 0 . 5 2P2M CMOS process, respectively. The ~ conventional layout needs four contacts, and the proposed layout needs three contacts only.

[2] A. Gupta, S.-C. Tle and J.P. Hayes, XPRESS:A Cell Layout Generator with lntcgrald Transistor Folding, io Pmc. European D e r i p & Test ConJ, pp. 393-400, 1996. [3] Y.-I. Kwon and C.-M. Kyung, An Algorithm for Optimal Layouts of CMOS Complex Logic Modules, in Proc. IEEE Int% Symp on Cirnriu and Sysfem, 01.5, pp. 3126-3129, June 1991. [4] T. Lcogauer and R. Muller, Linear Algorithms for Optimizing the Layout of Dynamic CMOS Cells, IEEE Trans. Circuits andSysfem,vol. 35, pp. 27y285. March 1988. [SI Robm L. Madasz and John P. H a p , Layoul Minimirolion o f CMOS Cells. Reading:Kluwer Academic Publishem, 1992. [6] T. Nakagaki, S. Yamada and K. Fukunaga, Fsst Optimal Algorithm for lhe CMOS Functional Cell Layout Based on Transistor Re~rdaiog, h e . IEEE Int,l. Symp. Cirnrifs and in Sysfem, vo1.5, pp. 2116-2119, May 1992. Hindmarsh, Layout Optimization of [7] M.R. TheiBinger and R.D. Planar CMOS Cells Regarding Width-to-Height Trade-off, in h o c . Europeon Design Automfion Conference, pp.4&53, Scp. 1994. [8] T. Uchara and W.M. van Cleemput, Optimal Layout of CMOS Functional Array, IEEE Trans Compufers,vol. c-30, pp.305314,May 1981. f [9] N.H.E. Wcstc and K. Eshraghian, Principle o CMOS VLSI Design.2nd Ed., Reading: AddisobWcsley, 1993.

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