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Introduction to VLSI Design

CMOS VLSI Design

Introduction
Why is designing digital ICs different today than it was before? Will it change in future?

CMOS VLSI Design

The First Computer

The Babbage Difference Engine (1832) 25,000 parts cost: 17,470


4 CMOS VLSI Design

ENIAC - The first electronic computer (1946)

CMOS VLSI Design

The First Integrated Circuits


Bipolar logic 1960s

ECL 3-input Gate Motorola 1966


6 CMOS VLSI Design

Intel 4004 Micro-Processor


1971 1000 transistors 1 MHz operation

CMOS VLSI Design

Intel Pentium (IV) microprocessor

CMOS VLSI Design

Transistor Counts
K 1,000,000 100,000 10,000 1,000 100 10 1 1975
9

1 Billion Transistors

i486 i386 80286 8086

Pentium III Pentium II Pentium Pro Pentium

Source: Intel

1980

1985 1990

1995 2000
Projected

2005 2010

CMOS VLSI Design

Courtesy, Intel

Moores Law
In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months

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CMOS VLSI Design

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LOG2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975

Electronics, April 19, 1965.

Moores Law

CMOS VLSI Design

Design Abstraction Levels


SYSTEM

MODULE + GATE

CIRCUIT

DEVICE G S n+ D n+

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CMOS VLSI Design

Fabrication and Layout

CMOS VLSI Design

Slide 13

Die Cost
Single die

Wafer

Going up to 12 (30cm)
14 From http://www.amd.com CMOS VLSI Design

Yield
No. of good chips per wafer Y= 100% Total number of chips per wafer Wafer cost Die cost = Dies per wafer Die yield
(wafer diameter/2)2 wafer diameter Dies per wafer = die area 2 die area

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CMOS VLSI Design

Silicon Lattice
Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors
Si Si Si Si Si Si Si Si Si

Fabrication and Layout

CMOS VLSI Design

Slide 16

Dopants
Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type)
Si Si Si Si Si Si Si Si Si Si Si B Si Si Si

+ -

As Si

Si

Fabrication and Layout

CMOS VLSI Design

Slide 17

p-n Junctions
A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction

p-type anode

n-type cathode

Fabrication and Layout

CMOS VLSI Design

Slide 18

nMOS Transistor

Fabrication and Layout

CMOS VLSI Design

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MOS Structure

Fabrication and Layout

CMOS VLSI Design

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MOS Structure

Fabrication and Layout

CMOS VLSI Design

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nMOS Operation
Step 1: Apply Gate Voltage SiO2 Insulator (Glass) Source Gate 5 volts Drain

holes

electrons P electrons to be transmitted Step 2: Excess electrons surface in channel, holes are repelled.

Step 3: Channel becomes saturated with electrons. Electrons in source are able to flow across channel to Drain. Figure 2

CMOS VLSI Design

Image courtesy of me. =o)

nMOS Operation
Body is commonly tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF
Source Gate Drain Polysilicon SiO2 0 n+ p n+ S bulk Si D

Fabrication and Layout

CMOS VLSI Design

Slide 23

nMOS Operation
When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON
Source Gate Drain Polysilicon SiO2 1 n+ p n+ S bulk Si D

Fabrication and Layout

CMOS VLSI Design

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Operation

Fabrication and Layout

CMOS VLSI Design

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Band Diagram

Fabrication and Layout

CMOS VLSI Design

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Fabrication and Layout

CMOS VLSI Design

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Some Definitions

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CMOS VLSI Design

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Fabrication and Layout

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Basic Equations

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CMOS VLSI Design

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Fabrication and Layout

CMOS VLSI Design

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Current Equation

Fabrication and Layout

CMOS VLSI Design

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Current Equation

Fabrication and Layout

CMOS VLSI Design

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Fabrication and Layout

CMOS VLSI Design

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Fabrication and Layout

CMOS VLSI Design

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Fabrication and Layout

CMOS VLSI Design

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Fabrication and Layout

CMOS VLSI Design

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Fabrication and Layout

CMOS VLSI Design

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Linear Region

Fabrication and Layout

CMOS VLSI Design

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