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Introduction
Why is designing digital ICs different today than it was before? Will it change in future?
Transistor Counts
K 1,000,000 100,000 10,000 1,000 100 10 1 1975
9
1 Billion Transistors
Source: Intel
1980
1985 1990
1995 2000
Projected
2005 2010
Courtesy, Intel
Moores Law
In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months
10
11
LOG2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975
Moores Law
MODULE + GATE
CIRCUIT
DEVICE G S n+ D n+
12
Slide 13
Die Cost
Single die
Wafer
Going up to 12 (30cm)
14 From http://www.amd.com CMOS VLSI Design
Yield
No. of good chips per wafer Y= 100% Total number of chips per wafer Wafer cost Die cost = Dies per wafer Die yield
(wafer diameter/2)2 wafer diameter Dies per wafer = die area 2 die area
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Silicon Lattice
Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors
Si Si Si Si Si Si Si Si Si
Slide 16
Dopants
Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type)
Si Si Si Si Si Si Si Si Si Si Si B Si Si Si
+ -
As Si
Si
Slide 17
p-n Junctions
A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction
p-type anode
n-type cathode
Slide 18
nMOS Transistor
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MOS Structure
Slide 20
MOS Structure
Slide 21
nMOS Operation
Step 1: Apply Gate Voltage SiO2 Insulator (Glass) Source Gate 5 volts Drain
holes
electrons P electrons to be transmitted Step 2: Excess electrons surface in channel, holes are repelled.
Step 3: Channel becomes saturated with electrons. Electrons in source are able to flow across channel to Drain. Figure 2
nMOS Operation
Body is commonly tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF
Source Gate Drain Polysilicon SiO2 0 n+ p n+ S bulk Si D
Slide 23
nMOS Operation
When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON
Source Gate Drain Polysilicon SiO2 1 n+ p n+ S bulk Si D
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Operation
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Band Diagram
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Some Definitions
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Basic Equations
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Current Equation
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Current Equation
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Linear Region
Slide 40