Exhibit A

Case 5:05-cv-00334-RMW Document 2543-2 Filed 11/14/2008 Page 1 of 106
EXHIBIT A
SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY REGARDING
VALIDITY IN LIGHT OF THE BENNETT AND NOVAK REFERENCES
SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

Rambus Inc. v. Hynix Semiconductor et al
N.D. Cal. Case Nos. C 05-00334 RMW, C 05-002298 RMW, C 06-00244 RMW.
1. I have been asked to expand upon the opinions offered in my original invalidity
report regarding the Bennett and Novak references. My opinions are set forth below.
Bennett
2. The Bennett patent (U.S. Patent No. 4,734,909) is titled “Versatile Interconnection
Bus” and describes in great detail (in 254 sheets of figures and 280 columns of text) a method of
implementing bused interconnections among various components of a computer system. In order
to allow many disparate types of components to be interconnected, Bennett describes a
complicated interface between the components. To ensure a high degree of flexibility, Bennett
provides for a configuration register as part of the interface. Bennett, Col. 15:24-38; Fig. 3. That
register allows eight parameters – such as, for example, whether certain signal lines are
multiplexed or not, and the number of bits in a data word – to be varied.
3. Bennett does not disclose putting its interface on a memory chip. Mr.
McAlexander cites to some references in Bennett to memory, and other references stating that
some of the components discussed in Bennett can be implemented as VLSIC devices, but, despite
Bennett’s length and detail, there is no express statement that Bennett intended its interface to be
placed on memory chips.
4. In fact, a person of skill in the art would understand that Bennett did not intend for
its interface to be placed on memory chips. First, Mr. McAlexander’s argument suggests that
Bennett discloses that all of the components connected to its Versatile Bus may be implemented
as single-chip, VLSIC devices containing the Bennett interface. This is clearly incorrect. For
example, Bennett refers to a “large memory” that may contain “up to up to 232 addresses of 32 bit
words.” Bennett, Col. 95:58-59. This corresponds to 128 Gigabits of memory, far more than can
be placed on a single chip even today. In the 1982 timeframe, when the Bennett application was

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filed, larger memory chips typically contained only 64 Kilobits of memory. It would have taken
over 2 million of such chips to total 128 Gigabits and could only have been achieved with
thousands of memory cards filling a medium-sized room. No person of skill in the art would
have considered trying to implement this amount of memory on a single chip. Plainly, Bennett
intended its “large memory” to consist of multiple memory cards containing multiple
conventional DRAM chips per card. These cards would then require separate bus interface chips
containing the Bennett interface in order to connect to the Versatile Bus.
5. Likewise, a person of skill in the art would understand that the other memories
referred to in Bennett also are intended to consist of memory cards with multiple conventional
memory chips and requiring separate bus interface chips. In its Background section, Bennett
makes clear that it does not intend for its complex interface to be used on certain components,
such as memory chips. According to Bennett, “[a]n efficient interconnect system cannot saddle
simple interconnects with the coordination overhead required for the complex ones.” Bennett,
Col. 8:10-12. A person of skill would have understood Bennett’s reference to “simple
interconnects” to refer to components, such as the memory chips of the day, with a small number
of pins available for interconnecting with other devices. Bennett did not intend, and it would have
made little sense, to “saddle” memory chips with the complex Bennett interface.
6. In fact, Bennett points out that “a VLSIC chip has on the order of 100 pins” and
stresses the importance of “pin efficiency.” Bennett, Col. 66:65-66. Bennett recognizes that pins
are a “precious resource,” Bennett, Col. 7:25-26. In the 1982 time-frame, memory chips had on
the order of 16 pins. A person of skill in the art, reading Bennett, would have understood that
Bennett was not contemplating a manifold increase in the number of pins on a memory chip in
order to add an unnecessary, complex interface.

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7. Bennett discloses that 24 pins are required simply to connect components
containing the Bennett interface to the “maintenance processor” used to initialize the interface, for
example, by shifting values into the configuration register. Bennett, Col. 117:64 – Col. 118:13.
Thus, if the Bennett interface were placed on a memory chip, just these initialization tasks would
have required more than doubling the number of pins on the device.
8. In addition to the pins required for initialization, the Bennett interface requires pins
for the connection to the Versatile Bus. Bennett describes in this regard, a “modest thirty-seven
pin requirement.” Bennett, Col. 36:62-63. A person of skill in the art would never have referred
to this number of pins as “modest” in relation to a memory chip.
9. Thus, when Bennett refers to “memory,” a person of skill in the art would have
understood that Bennett was referring to memory cards containing standard memory chips of the
day. Separate chips incorporating the Bennett interface would then be used to connect the
memory cards to the Versatile Bus. Bennett states that “[m]emories and memory subsystems
must be selected to provide the operations needed in a specific design,” Bennett, Col. 91:2-4,
contemplating that the memory would simply be “selected” from existing options.
10. The memory cards with multiple memory chips, combined with separate bus
interface chips, of Bennett do not constitute integrated circuit devices, synchronous memory
devices, synchronous semiconductor memory devices, or synchronous dynamic random access
memory devices within the meaning of Rambus’s patent claims. The Court has construed
“integrated circuit device” as being a single chip. The Court has also indicated that when
“memory device” is modified as above, it also refers to a single chip. Claim Construction Order
at 35 (“These claims are drawn to ‘a method of operation of a synchronous memory device’ and
‘a method of operation of a synchronous dynamic random access memory device.’ These
additional limits on the scope of ‘memory device’ ameliorate fears that Rambus’s claims could

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read on a ‘tape recorder’ while also demonstrating that Rambus knew how to limit its claims to a
single chip when it wished to do so.”)
11. In addition, the memory cards with multiple memory chips, combined with
separate bus interface chips, of Bennett do not constitute “memory devices” within the meaning of
Rambus’s patent claims. I understand that Rambus has moved for reconsideration of the Court’s
ruling that a “memory device” need not be a single chip. Even if the Court does not reconsider its
earlier ruling, I do not interpret the Court’s opinion as holding that any assemblage of chips would
be a “memory device” so long as some of those chips were memory chips. I do not believe that a
person of skill in the art would consider the combination of multiple memory chips with a
separate bus interface chip to be a single “memory device.” Indeed, I note that in the course of
prosecuting its patents, Rambus made clear that such a combination did not constitute a memory
device. In a July 23, 1999 Amendment filed during the prosecution of U.S. Patent No. 6,034,918,
Rambus distinguished prior art by noting that in the prior art it was a bus interface unit that
received the clock signal and data length transfer information, not the memory devices. Ex. 1 at
10-11.
12. Mr. McAlexander asserts that Bennett discloses a programmable register that
allows the user to set the time delay between the receipt of a read or write command and the
output or input of the corresponding data (features that have been referred to as programmable
read latency and programmable write latency). I disagree. The eight parameters that can be
adjusted in Bennett’s configuration register are shown in Figure 3. Those parameters do not
include the time delay between the receipt of a read or write command and the output or input of
the corresponding data. Thus, this time delay cannot be set in the Bennett interface.
13. Moreover, Bennett makes clear that the values in the configuration register do not
determine the actual configuration of the device. Bennett states that the values in the

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configuration register establish a ceiling on the various configurations that the device must
support, but the device must also support all configurations with lower values for the eight
parameters. Bennett, Col. 37:66 – Col. 38:3 (“The design rule for Versatile Bus interface logics is
that any value may be chosen for each primitive [i.e. parameter in the configuration register], but
then all smaller values for that primitive must also be supported. With this rule, it is always
possible to find a value for each primitive that is supported by all the chips that are to be used
together . . . .”); Bennett, Col. 78:51-55 (“[T]o assure that any chip can be connected to any other
chip using a Versatile Bus configuration, the chip design must support any configuration whose
configuration digits are all equal to or less than the corresponding chosen configuration digits . . . .
“) Thus, the actual configuration of the device will depend not just on the values in its
configuration register, but also the values in the configuration registers of the other components in
the system. Therefore, the values in the configuration register of the interface to the memory
devices do not alone determine the actual configuration of the device.
14. Mr. McAlexander asserts that Bennett does disclose programmable read and write
latency because Bennett allows the user to determine, via the configuration register, whether
certain signal lines are multiplexed or not. Even if the values in the configuration register actually
determined the configuration of the device, which, as I discuss above, is not the case, this still
would not amount to programmable read or write latency. While it is true that, as a general
matter, multiplexing involves a trade-off between number of pins and speed – the more
multiplexing, the smaller the number of pins, but the slower the speed due to the sharing of signal
lines for multiple types of information (see Bennett, Col. 12:62-64) – there is no set correlation
between the degree of multiplexing and the response time to a read or write command and Bennett
discloses no such correlation.

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15. For example, in the example given in Col. 79:4-10, the eight bits of the
configuration register are set to the preferred embodiment of 55255355. This means that the first
parameter (“GROUP LINES”) of the configuration register shown in Figure 3 of Bennett
(parameters are listed in the row near the top) is set to configuration digit 5; the second parameter
(“NO. OF GROUPS”) is also set to configuration digit 5; the third parameter (“ARB. CHOICES”)
is set to configuration digit 2; and so forth. The first column in Figure 3 lists the “configuration
digits.” In the 55255355 example, the sixth parameter (“WAIT LINES”) is set to configuration
digit “3”, which corresponds to one WAIT line. But, as discussed above, the device must support
all possible configurations with smaller values of the configuration digits. For example, despite
the values in the configuration register, the actual configuration of the device may be 42252255 –
with a “2” in the sixth configuration bit corresponding to zero wait lines according to Figure 3.
Thus, even though the value in the register does not change, the device may end up being
configured differently in different systems based on the other devices with which it is required to
interact.
16. Mr. McAlexander points to Figures 25a and 25b in Bennett as allegedly disclosing
programmable read and write latency. In Figure 25a, the WAIT signals in Bennett are
multiplexed with the DATA signals. In Figure 25b, the WAIT signals are not multiplexed with
the DATA signals, allowing faster operation because the WAIT and DATA signals can be sent
simultaneously. But, as I note above, the objective in Bennett in these examples is to adjust the
amount of multiplexing, not the latency, and the timing shown is just an example, as Bennett
points out: “In order to simplify presentation of timing concepts all Arbitration, Slave
Identification/Function, and Data activities are assumed to be but one cycle.” Bennett, Col.
85:17-19 (referring to figures 25a through 25h). While Figure 25a and 25b do show a one clock
cycle difference between the beginning of the operation and the data, one cycle is simply an

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example. There is no value stored in the configuration register of Bennett, or anywhere else, that
mandates a one cycle difference between the two configurations.
17. Moreover, the possibility of asserting a WAIT signal results in additional
uncertainty in the timing of responses in the Bennett system. The WAIT signal is the way that
slave devices (like memories) “inform a requesting bus-owning master device of their individual
or collective incapacity to immediately receive data within the instant communication transaction .
. . . In other words, in a simplistic sense wait means ‘abort’ or ‘try again after a time.’” Bennett,
Col. 16:53-58. The possible assertion of a WAIT signal is yet another reason why there is no set
time between a read or write command and the output or input of the corresponding data in
Bennett.
18. Mr. McAlexander lists various other figures in Bennett which he asserts show
programmable read and/or write latency. However, none do for the same reasons that I discuss
above. For example, Mr. McAlexander cites the configurations shown in figures 32 and 33. In
these configurations, the timing of the data relative to the transmission of the operation does not
vary – in both figures, the data appears on the next cycle. But this again is just an example, and
Bennett never suggests that this timing corresponds to some programmed value or is in any way
set, via the configuration register or otherwise. Bennett never suggests that the timing of the data
relative to the transmission of the operation is consistent from one transaction to the next.
19. Bennett also makes clear that there is no set time between request and response
when reading from a “large memory.” Such a read operation requires two transactions, command
and response, with an indeterminate amount of time in between. Bennett, Col. 94:37 – 95:24.
The timing of the memory’s response depends on indeterminate factors such as, for example,
arbitration with other components for control of the bus. Id.

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20. Mr. McAlexander also opines that Bennett discloses variable block size, pointing
to the Block Read and Block Write operations. Bennett, Col. 91:54-68. The description makes
clear, however, that no block size information is transmitted in Bennett within the meaning of
Rambus’s patent claims. The Court has construed “block size information” as “information that
specifies the total amount of data that is to be transferred on the bus in response to a transaction
request.” This plainly means that the block size information must be transmitted prior to the data
so that it can specify the amount of data “to be transferred.” No such information is transmitted in
Bennett. Rather, block transfers are implemented using a “BUSY” signal that is active during a
Block Read or Block Write operation; “Dropping the BUSY line to inactive terminates the
transaction.” Bennett, Col. 91:59-61. Mr. McAlexander equates Bennett’s BUSY signal with
block size information, but it is quite different. In particular, it is not received prior to the transfer
of data and does not specify the amount of data to be transferred: Since the BUSY signal simply
transitions to cut off the transfer, reading the value of this signal provides no information about
how much data will be transferred. Indeed, Bennett itself makes clear that no block size
information is provided. Bennett, Col. 61:54-58 (“[B]lock data transfer transpires under the same
BEGIN and BUSY control signals as the transmission of a single word – no special information
transmission (such as block length) or control protocol is ever involved.”) (emphasis added).
21. In fact, Mr. McAlexander has previously acknowledged that a signal analogous to
the BUSY signal in Bennett is not “block size information” within the meaning of Rambus’s
patent claims. In his report regarding alleged “alternatives” to Rambus’s inventions, Mr.
McAlexander opined that one such alternative was the use of a “burst terminate” signal which he
described as “a dedicated signal input to indicate or command at will the termination of an
otherwise fixed-length burst in progress, thereby achieving variable-length bursts on-the-fly
without requiring the programmable feature.” Ex. 2 (McAlexander Conduct Report) at 29. This

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is a description of the Bennett BUSY signal which, by going inactive, signals the termination of
the burst in progress. Thus, Mr. McAlexander acknowledged that such a burst terminate feature
was not covered by Rambus’s patent claims but, instead, was an alternative to them.
22. While Mr. McAlexander does not appear to so opine, I note that, in the
Manufacturers’ motion for summary judgment of anticipation based on Bennett, they have
asserted that there is an additional disclosure of variable block size in Bennett. In particular, they
point to configuration bits 18-23 in the Bennett configuration register shown in Figure 3 which
correspond to the seventh and eighth configuration parameters and determine the number of data
lines and the number of bits per data word. As an initial matter, as discussed above, the values in
the register do not determine the actual configuration of the device but only provide a ceiling.
Moreover, even if the values in the register did determine the device configuration, they would
only determine the number of bits per data word, and the number of clock cycles it will take to
transmit a single word (based on the number of data lines); they would not determine the number
of data words to be transmitted and, therefore, would not determine the total amount of data to be
transmitted as required by block size information. Again, Bennett itself makes this clear: “The
seventh configuration dimension [namely, bits 18-23 in the configuration register] is the format –
the partionment in pins times cycles as equals bits – of data words and is not the amount thereof.”
Bennett, Col. 17:29-31 (emphasis added).
23. Bennett does not disclose a set register request or an operation code specifying that
a value be stored in a register. A “set register request” has been construed as “one or more bits to
specify that a value be stored in a programmable register,” and an “operation code” as “one or
more bits to specify a type of action.” Mr. McAlexander points to various references in Bennett to
values being loaded into the configuration register, but is unable to identify “one or more bits”
directing that the values be loaded as required. In fact, Bennett makes clear that values are not

9
loaded into the register in response to one or more bits. Bennett explains that, in order to set the
configuration register, certain signal lines must be held at given voltage levels for an extended
period of time; specifically, the SCAN/SET ENABLE signal must be held low, the SCAN/SET
SELECT signal must be held low, and the SEL LOOP D signal must be held high. Bennett, Col.
125:46-56. While these voltage levels are maintained, SET DATA is used to serially shift in each
of the 28 bits in the configuration register. Id. The voltage levels of the control signals must be
held throughout this operation. If the specified voltage levels on SCAN/SET ENABLE,
SCAN/SET SELECT, and SEL LOOP D were transmitted to the device, but those voltages were
not maintained as required, then no values would be loaded into the configuration register. This
demonstrates that if the values on those signal lines at a particular point in time are interpreted as
bits, those bits are insufficient to specify that values be loaded into the configuration register.
Novak
24. The Novak patent (U.S. Patent No. 4,663,735) is directed to a Video RAM, or
VRAM. This chip has one portion which is simply a conventional asynchronous DRAM that
allows for the usual asynchronous DRAM operations. However, appended to the DRAM portion
is a shift register, allowing for the serial input and output of data. See Novak, Col. 4:36 – 5:12.
25. The Court has construed “external clock signal” as “a periodic signal from a source
external to the device to provide timing information.” Novak does not disclose an external clock
signal. Mr. McAlexander identifies the signal Φ in Novak as such a clock signal, but Novak
makes clear that Φ is not a clock signal, because it is active only when required for inputting data
into or outputting data from the shift register. Figure 4 of Novak shows that Φ is inactive both
before and after data transmission. A person of skill in the art would not consider such a signal a
“periodic signal” as required by the Court’s claim construction. The Manufacturers agree,
generally taking the position that signals having limited sequences of repetitive transitioning, such

10
as the data strobes in their products, are not external clock signals. For example, Nanya’s non-
infringement expert, Dr. Bagherzadeh, states at paragraph 104 of his report that “[t]he DQ strobe
is not a clock signal, because the DQ strobe is not a continuously periodic signal. It achieves
periodicity for the duration of read or write command, providing edge alignment with read data
and centered with respect to write data.”
26. I understand that the Manufacturers argue that whether Novak discloses an external
clock signal is governed by the Court’s holding in Hynix I that a signal also named Φ in a different
patent, U.S. Patent No. 4,330,852 to Redwine, is an external clock signal. This is incorrect.
Novak and Redwine have different specifications and certain portions of the Redwine
specification that the Court relied on in holding that Φ was an external clock signal for purposes
of Redwine are not present in Novak.
27. In Hynix I, Hynix argued that the Φ signal in Redwine actually runs periodically at
all times, but is “gated (internally on the device) by the CS\ signal.” Order Denying Hynix’s
Motion for Summary Judgment of Invalidity, 2/28/06, at 4-5 (quoting the declaration of Hynix’s
expert David Taylor). The argument was based on a portion of Figure 3 of Redwine which
showed the Φ signal being input to a transistor that is controlled by the CS signal. The Court
accepted Hynix’s argument in holding that the CS signal acts as gate for Φ and that Φ is an
external clock signal. Hynix’s argument and the Court’s holding cannot be translated to Novak
because Novak does not disclose a CS signal. Nor is there any figure in Novak similar to the
portion of Figure 3 in Redwine on which the Court relied in holding that the CS\ signal acts as a
gate for Φ.
28. It is also my opinion that Redwine does not disclose an external clock signal. As I
noted above, Figure 3 of Redwine shows Φ as an input to the transistor controlled by CS. (While
the word “input” appears under Φ in Figure 3, this is not a different signal name, but is just

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specifying that Φ is an input. This is made clear by Figure 1 which shows Φ as an input, but does
not add the word “input.”) That is, the figure shows that, if CS – chip select – is high, the chip at
issue is selected and Φ will pass through the transistor and be received by the chip. But CS cannot
affect whether Φ runs continuously or not, because Φ is input to the transistor. In other words, the
Φ signal exists and runs continuously or not before the transistor controlled by CS could have any
effect on it. As shown in Figure 2 of Redwine, Φ does not run continuously, but only while data
is being input or output from the shift register. The CS signal is used, as the name implies, to
select one or more of the VRAMs in a system with multiple VRAMs – that is, it allows Φ onto
only those VRAMs, and hence to shift data into or out of the shift registers of only those VRAMs,
that are intended to be involved in a given serial read or write operation.
29. Novak also fails to disclose a “write request,” which the Court has construed as “a
series of bits used to request a write of data to a memory device.” Likewise, Novak fails to
disclose an “operation code,” which the Court has construed as “one or more bits to specify a type
of action.” Mr. McAlexander opines that the values of the TR\ and W\ signals disclose both a
write request and an operation code specifying a read or write operation (though, elsewhere, he
opines that it is the values of TR\, W\, and RAS\ that specify the operation code) because those
signals are used to specify serial read and serial write operations in Novak. Novak, however,
shows that for a serial write operation Φ must toggle to load the data into the shift register, after
which TR\ must transition to a low level, followed by W\ transitioning to a low level, followed by
RAS\ transitioning to a low level. Fig. Novak, 4a, 4b, 4e; Col. 6:50-54. For a serial read
operation, W\ must be held high, while TR\ transitions to a low level, followed by RAS\
transitioning to a low level, followed by Φ toggling to output the data. Novak, Fig. 4a, 4b, 4d; Col
6:54-67; Col. 8:21-36. Thus, serial write and read operations in Novak cannot be specified simply
by a code consisting of a series of bits, because it is not simply the values of the relevant control

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signals at a particular point in time that specify the operations. Rather, the control signals must
transition in the correct order and be held for the required time periods. In a synchronous system,
like that described in the patents-in-suit, the signals transmitting the operation code are “sampled”
– that is, their values are obtained at a discrete point in time – resulting in a code of 0s and 1s
specifying a particular operation. Examining the states of the signal lines in Novak will likewise
yield a series of 0s and 1s, but those values alone do not specify a particular operation. As an
example, suppose one were to examine the state of W\, TR\, and RAS\ and determine that they
were all low, corresponding to the series of bits 0,0,0. It is possible that a serial write operation
had been specified, if in fact, TR\ had transitioned low first, followed by W\ and then RAS\. But,
if the signals had reached their states of 0,0,0 in a different order, they would not specify a serial
write operation. Thus, there is no way to tell simply by looking at the bits, namely the states of
the control signals at a particular time, whether a serial write operation had been specified.
30. I understand that the Manufacturers again argue that the Court’s holding in Hynix I
that the W signal in Redwine constitutes an operation code requires a finding that Novak also
discloses an operation code. Mot. at 11-12. I disagree. Different control signals are involved in
specifying read and write operations in Novak than in Redwine. Here, Mr. McAlexander asserts
that it is either the TR\ and W\ signals that constitute an operation code, or, at other times, that it is
those signals as well as the RAS\ signal. By contrast, Hynix argued in Hynix I that the W\ signal
alone constituted an operation code. Indeed, Redwine does not even disclose the TR\ signal that
Mr. McAlexander asserts is a necessary part of what he identifies as the operation code in Novak.
As I noted above, since it is not only the states of W\, TR\ and RAS\ at a given time, but also their
relative times of transitioning, that specify a serial read or write operation in Novak, they cannot
constitute an operation code. The Court’s conclusion in Redwine, which involved only a single

13
signal and, therefore, did not raise the issue of relative times of transitioning, does not apply to
Novak.
31. In addition, it is my opinion that the W\ signal in Redwine does not constitute an
operation code. The W\ signal in Redwine does not suffice to specify a serial read or write
operation. Rather, as shown in Figure 2 of Redwine, to specify a write operation, for example,
RAS\ must transition low, after W\ transitions low, and while W\ is being held low. The states of
RAS\ and W\ at a given time, which could be interpreted as bits, are not by themselves sufficient
to specify a serial or write operation because, as noted, the relative transition times must also
satisfy certain conditions that are not captured by the bits alone. Thus, Redwine does not disclose
an operation code.
32. Novak does not disclose sampling or receiving an operation code synchronously
with respect to an external clock signal. As I discuss above, Novak does not disclose an external
clock signal or an operation code, but even if Φ were an external clock signal, and TR\ and W\ did
constitute an operation code, Novak would still not disclose this claim element.
33. As an initial matter, Novak does not disclose “sampling” control signals such as
TR\ and W\ at all. These signals are sensed rather than sampled. That is, rather than the values of
the control signals being obtained at discrete points in time as required for sampling, the control
signals must be continuously held and sensed, as shown in the timing diagram in Figure 4 and as
described in Novak’s written description. See, e.g., Novak, Col. 8:32-34 (“For a serial read
operation, TR\ goes to active-low and the W\ signal is held high during the period seen in Fig. 4b
. . . .”) (emphasis added).
34. Moreover, the Court has construed “synchronously with respect to” as “having a
known timing relationship with respect to,” but there is no known relationship disclosed in Novak
between Φ and control signals such as W\ and TR\. To the contrary, Novak makes clear that there

14
can be no such known timing relationship because Figure 4 indicates that W\ and TR\ transition at
times when Φ is not even active. Even during the time that Φ is active, Figure 4 shows no timing
relationship between the transitions of the control signals and Φ.
35. Mr. McAlexander asserts that a person of skill the art would know that W\, TR\,
and Φ are generated in relation to a system clock and so must have a known timing relationship.
There is no such disclosure in Novak. Nor is there any reason that Φ, which is generated to
correspond to the data input needs of a video display, could not be generated independently from
the control signals.
36. For similar reasons, Novak does not disclose sampling block size information
synchronously with respect to an external clock. Mr. McAlexander opines that the signals A6 and
A7 in Novak constitute block size information. I disagree, as I discuss below. But, even if A6
and A7 did constitute block size information and even if Φ were an external clock signal, there is
no disclosure in Novak of a known timing relationship between A6 and A7 and Φ. According to
Mr. McAlexander, A6 and A7 are sampled when the CAS\ signal goes low, but, as I discuss
above, there is no known timing relationship between Φ and control signals like CAS\, so this
does not establish a known timing relationship between A6 and A7 and Φ.
37. Novak does not disclose inputting or sampling data in response to a write request
or an operation code. As I discussed above, Novak does not disclose a write request or an
operation code. However, even if the TR\ and W\ signals did constitute a write request or
operation code designating a write operation as Mr. McAlexander asserts, Novak still would not
disclose inputting data or sampling data in response to those signals. A serial write operation in
Novak, as shown in the timing diagram of Figure 4, begins with up to 256 bits being input into the
shift register. It is this part of the operation that Mr. McAlexander associates with inputting or
sampling the data using the Φ signal. Only after the data has been loaded into the shift register do

15
TR\ and W\ (as well as RAS\) transition, directing the memory device to transfer the data in the
shift register into the memory array. See Fig. 4a, 4b, and 4e (showing the transitions on the
control lines designating a write operation on 4a and 4b occurring after the data has been loaded
into the shift register on 4e). Since the transitions that the Manufacturers identify with the write
request or operation code occur after what the Manufacturers identify with the input or sampling
of data, it is clear that the sampling cannot have been “in response to” the write request or
operation code.
38. Novak does not disclose a synchronous memory device. The Court has construed
“synchronous memory device” as “a memory device that receives an external clock signal which
governs the timing of the response to a transaction request.” The Court has also construed a
“transaction request” as “a series of bits used to request performance of a transaction with a
memory device.” As I discuss above, Novak does not disclose an external clock signal. In
addition, Novak does not disclose a transaction request for the same reasons that it does not
disclose a write request or an operation code. It follows that Novak does not disclose a
synchronous memory device.
39. Moreover, even if the Φ signal could be considered to be an external clock, and
even if the serial read and write operations identified by Mr. McAlexander could be considered
transaction requests, Novak still would not disclose a synchronous memory device. As I noted
above, a VRAM such as that disclosed in Novak is simply a conventional asynchronous DRAM
with an added shift register. In particular, the control signals in Novak – RAS\, CAS\, W\, and
TR\ – are received asynchronously and are not governed by Φ. For a serial write operation, as I
discuss above, the transitions of the control signals that Mr. McAlexander identifies with the write
request are received after Φ has been used to load data into the shift register and has become
inactive; Φ could not possibly “govern” the response to these control signals. For a serial read

16
operation, the transitions of the control signals that Mr. McAlexander identifies with a read
request occur before Φ has become active, and so Φ cannot determine the length of time between
those transitions and the output of data from the shift register. Thus, Φ cannot govern the timing
of the response to a serial read or write operation as Mr. McAlexander asserts.
40. I note also that a person of ordinary skill in the art would not consider a VRAM
such as that disclosed in Novak to be a synchronous memory device. When, later on, a memory
device was introduced that was specially suited for video applications and that did receive control
signals synchronously with respect to a clock, it was called a synchronous VRAM or SVRAM.
Ex. 3 (excerpt of definitions from JEDEC Standard 21-C, Release 9). Of course, this would make
no sense if the prior VRAMs had already been considered to be synchronous memory devices.
41. Novak does not disclose block size information, construed as “information that
specifies the total amount of data that is to be transferred on the bus in response to a transaction
request.” Novak discloses a 256-bit shift register which is divided into four 64-bit parts. Novak,
Col. 7:3-5. There are also four “taps” that are used to select “whether one, two, three, or all four
64-bit shift registers are accessed.” Novak, Col. 7:16-17. Novak makes clear that the ability to
access only a subset of the shift register is not provided so that the amount of data transferred can
be set, but in order to make it easier to reach certain bits stored in the shift register. Since the data
in the shift register must be shifted in or out in order, by dividing the shift register into four 64-bit
portions and allowing the user to tap into the one of interest, “any bit of data may be accessed in
64 shifts or less, rather than 256 shifts.” Novak, Col. 7:38-40.
42. The two bits that the Manufacturers identify with block size information select the
tap:
[I]f the two bits are both 0, then all 256 bits in the shift register may
be shifted out. If the two bits are 01, then 192 bits, starting at bit 64,
may be shifted out. If the two bits are 10, then 128 bits, starting at
bit 128 may be shifted out. The two bit code 11 selects the last 64

17
bits starting at bit number 192 and then these last 64 bits may be
shifted out.
Novak, Col. 7:48-54. That is, the two bits identify the starting point for data transfer in the shift
register, but do not specify how much data is to be transferred beginning at that point. For
example, if the two bits are 01, then we know that the data transfer starts at bit 64 of the shift
register, but whether one bit, or two bits, or 192 bits are transferred beginning at that point is not
specified. As Novak states, in that circumstance “192 bits, starting at bit 64, may be shifted out.”
Novak, Col. 7:50-51 (emphasis added). In other words, 192 bits is the maximum that may be
shifted out starting at that point of the shift register; Novak does not specify the actual amount to
be shifted out.
43. Moreover, the construction of “block size information” requires that the amount of
data specified be transferred on the bus. The “bus” at issue is the set of signal lines that connect
the memory controller to the memory devices. In Novak, this corresponds to the “address/data
bus” combined with the “control bus” in Figure 1, the controller corresponding to the
“microcomputer chip.” But, in Novak, data output from the shift register is not transferred on the
bus. Rather, it is transferred on a separate signal line that connects directly to the video display or
CRT tube. Novak, Fig. 1; Col. 4:2-6.
44. Novak does not disclose sampling data, in response to an operation code, after a
predetermined number of clock cycles of the external clock, or after a delay time transpires. Mr.
McAlexander opines that these limitations are satisfied because, when data is being read from the
Novak shift register at the same time that new data is being written into the shift register, a person
of skill in the art would know that the data could not start to be written into the shift register until
at least one-half clock cycle from the start of reading data from the shift register. It is this one-
half clock cycle that Mr. McAlexander associates with “a predetermined number of clock cycles”
and a “delay time.” Mr. McAlexander is, however, focused on the wrong time interval. The

18
Rambus patent claims containing the limitations at issue, such as the claims of the ’051 patent and
the claims of the ’037 patent, require that there be a predetermined number of clock cycles or a
delay time between when an operation code specifying a write operation is transmitted and when
the corresponding data is input, not between the respective starts of reading and writing data.
There could not be any such a predetermined number of clock cycles or delay time in Novak: As
I discuss above, the transitions of control signals that Mr. McAlexander associates with an
operation code for a write operation occur after what he interprets as the sampling of data (the
loading of data into the shift register).
45. Novak does not disclose precharge information. The Court has construed
“precharge information” as “one or more bits indicating whether the sense amplifiers and/or bit
lines (or a portion of the sense amplifiers and/or bit lines) should be precharged.” Mr.
McAlexander opines that the RAS\ signal in Novak constitutes the precharge information because
precharging is performed when the RAS\ signal goes high. RAS\ does not, however, constitute a
“bit” of information contained in an operation code because, as discussed above, the control
signals in Novak must transition in a particular order and be sensed over extended periods of time
for the device to operate correctly.
46. Even if RAS\ were a bit, however, Mr. McAlexander’s position is that RAS\ going
high signals the end of a read or write operation, after which precharging is always performed.
This is, in fact, the way that many conventional, asynchronous DRAMs operated, but RAS\
cannot constitute precharge information in this scenario. Precharge information under the Court’s
construction must convey “whether” to precharge; that is, precharge information must allow for
precharging or not depending on the content of the information. The Court’s construction of
precharge information is carried over from Hynix I, where the Court made this clear:
[T]he precharge information does not simply convey a value

representing the establishment of a pre-defined voltage state [i.e.

19
precharging]. Instead it conveys whether the device should

precharge the “sense amps (and hence the bit lines)” (’263 patent,
cl. 10 l. 43), or not precharge the sense amps so that they can retain
the data to be sensed on the next read (’263 patent, cl. 10, ll 25-30).
. . . [T]he court finds that the specification implies “precharge
information” as information relating specifically to whether or not a
component of the device should be precharged.
Hynix I Claim Construction Order at 23 (emphasis added).
47. Mr. McAlexander also notes that Novak discloses a refresh operation in
conjunction with a serial read or write, which necessarily includes precharging. This is not a
separate argument – it would be the RAS\ signal going high at the end of the operation that would
precede precharging.
48. Even if the RAS\ signal going high could constitute precharge information, Novak
still would not disclose precharge information being transmitted as part of an operation code
specifying a read or write operation, as required by some of Rambus’s claims. Nor would Novak
disclose an operation code that specifies a read or write operation and further specifies that sense
amplifiers be precharged, as required by other Rambus claims. This is because, as I discuss
above, the serial read and write operations described in Novak are specified by RAS\going low
after appropriate transitions of the TR\ and W\ signals. RAS\ must then be held low during the
duration of the operation, and, finally, transition to a high voltage to signal the end of the
operation, after which precharging occurs. As I discuss above, I do not believe that these various
transitions of the control signals can be characterized as an “operation code,” but, even if they
could, it is RAS\ going low that is part of specifying the serial read or write operation. Even under
Mr. McAlexander’s argument regarding operation codes, RAS\ later going high could not be part
of the operation code specifying the read or write operation – it is a later transition of RAS\ that
specifies the end of the operation.

20
o u " , /, l//.2008
SUPPLEMENTALEXPERTREPORTOF ROBERTJ. MURPHY

2l
Exhibit 1
IN THE UNITED STATES PATENT AND TRADEMARK OFFICE

(Case No. P043D2C2C)
In the Application of: 1

1 I* o/R&
FARMWALD ET AL. )
)
Group
Art Unit: 2818 -\ /.&fly
Serial No: 09/252,997 1 c ,{\ cf;/h
) Before
Filed: FEBRUARY 19, 1999 ) Examiner: T. Nguyen
1
Title: METHOD OF OPERATING A MEMORY )
HAVING A VARIABLE DATA OUTPUT 1
LENGTH AND A PROGRAMMABLE REGISTER )
Assistant Commissioner for Patents

Washington, DC 20231
-4
0
AMENDMENT 1u &50
a&Ifl
O r 0
*
zx- mz
:cn
Dear Sir: P, rn
r = r J
In response to the Office Action mailed July 16, 1999,Sdirfdly
c3
amend the above-referenced application as follows: .=I
:-
Please delete the Abstract of the Disclosure and substitute
the attached Abstract of the Disclosure.
SPECIFICATION:
-______-_ - - _ _ I L
On page 1, line 8, insert --This application is a continuation
of Application No. 09/196,199, filed on November 20, 1998 (still
pending), which is a continuation of Application No. 08/798,520,
Page 1
,, ,,1 filed on February 10, 1997 (now U.S. Patent 5,841,580); which is a
I .
\ '.
(0
P
,',-
'
division of Application No. 08/448,657, filed May 24, 1995 (now
U.S. Patent 5,638,334); which is a division of Application No.
08/222,646, filed on March 31, 1994 (now U.S. Patent 5,513,327);
which is a continuation of Application No. 07/954,945, filed on
September 30, 1992 (now U.S. Patent 5,319,755); which is a
continuation of Application No. 07/510,898, filed on April 18, 1990
(now abandoned) . - - - - __ -
On page 11, line 14, insert - Figure 16 is a block diagram
63 representation of a set of internal registers within each device
illustrated in Figure 2.-- . .--

I
On page $4/line 3, replace "Each" with --With reference to
Figure 16, each--.
On page k'line 4, after flregistersfl

insert --170--.
On page l d l i n e 5, after the first occurrence of llregisterll
insert --171--.
On page 1 d i n e 5, after the second occurrence of Ilregisterll
insert --174--.
,
On page 1 d n e 6, after the first occurrence of tlregisterll
insert --175--.
On page 3P.fiine 8, after Ilregistersl' insert --172--.
On page d i n e 10, after "registersI1insert --173--.
17, after Ifregister"insert --171--.
Page 2
On page 1 4 , f t e r t h e first occurrence of I 1 r e g i s t e r s 1 l
i n s e r t --173--.
On page line 20, after the second occurrence of

rc
l l r e g i s t e r s l li n s e r t - - 1 7 5 - - .
On page 1 4 ,
insert --172--.
/i ine 20, a f t e r the third o c c u r r e n c e of llregistersll
/
O n page 1 4 p e 2 2 , a f t e r l 1 r e g i s t e r s l 1i n s e r t - - 1 7 3 - - .
On page 2 1 / l i n e 15, a f t e r l l r e g i s t e r s " i n s e r t - - 1 7 3 - - .
On page 35 / f i n e 25, a f t e r I1registers" i n s e r t - - 1 7 0 - - .

1
On page 3 6 d i n e 1 0 , a f t e r l l r e g i s t e r s " i n s e r t - - 1 7 3 - - .
On page 3,/i1ne 12, after "registers" insert --172--.
On page 3 d i n e 1 5 , a f t e r " r e g i s t e r l l i n s e r t - - 1 7 1 - - .
On page 3 9 n e 2 3 , a f t e r t h e second occurrence of "register1I
insert --171--.
O n page 3/1ine 25, a f t e r l l r e g i s t e r l li n s e r t - - 1 7 3 - - .
O n page 3 9 , A i n e 6 , a f t e r l l r e g i s t e r l l i n s e r t - - 1 7 3 - - .
v
:-
Please add new F i g u r e 1 6 , a t t a c h e d h e r e t o .
Page 3
i:
3
#3. (Amended) The method of claim further including:
-' a \
' providing second block size information to the memory device,
1
/ 3 wherein the second block size information defines a second amount

4 of data to be input -euc ' e from the bus in response
5 to a write request; and
6 issuing the second write request to the memory device, wherein
7 in response to the second write request, the memory device inputs
8 the amount of data corresponding to the second block size
9 information from the bus synchronously with respect to the external
10 clock signal.
~~ __ ._~~ ._.__ _~ .-
\ J C '1
I
8. (Amended) A method of operation of a synchronous memory
2 device, wherein the memory device includes a plurality of memory

3 cells, the method of ogeration of the memory device comprises
4 [comprising]:
6 receiving first block size information L,

\
7 wherein the first block size information defines a first amount of

8 data to be output by the v- ice onto a bus in response to a
9 read [or write] request;
10 receiving a first read request fiom the bus controller; and
11 outputting the first amount of data corresponding to the first
12 block size information, in response to the first read request, onto
13 the bus synchronously with respect to [an] Lhe external clock
14 signal.
Page 5
2 \ 'receiving a second read request , and

\ 3\ outputting the first amount of data corresponding to the first
I
I' 4 block size information, in response to the second read request,

5 onto the bus synchronously with respect to the external clock
6 signal.
2 on further d e-- f e
3 qe to a write request,
4 & me- further including:

5 receiving a first write request 3, and
6 inputting the first amount of data corresponding to the first
7 block size information, in response to the first write request,
8 from the bus synchronously with respect to the external clock
9 signal.
ad'
1
2
%. (Amended) The method of claim & further including:
receiving second block size information, wherein the second
3 block size information defines a second amount of data to be input
4 from the bus in response to a write request; and
5 receiving the second write request from the bus controller;
6 inputting the amount of data corresponding to the second block
7 size information, in response to the second write request, from the
8 bus synchronously with respect to the external clock signal.
__._- -
- __
~- - -. -- . .. --
.~ - ..
c-
I
I ..., //
1
' / Page 6
- __
1 A method of operation of a synchronous memory
t k1
6 2 device+ wherein the memory device includes a plurality of memory
3 cells and a time delay register, the method of operation o f the
I
4 memory device comprises:

5 storing a value in the time delay register, the value being
6 representative of a number of external clock cycles
7 after which the memory device responds to a read request;
8 receiving an external clock signal wherein the external clock
9 signal has a fixed frequency;
10 receiving block size information from a bus controller,
11 wherein the block size information defines a first amount of data.
12 to be output by the memory device onto the bus in response to a
13 read request;
14 receiving a first read request from Lhe bus controller;
15 outputting the first amount of data corresponding to the block
16 size information onto the bus in response to the first read
17 request, [;
18 receiving a second read request;
19 outputting the first amount of data corresponding to the block
20 size information onto the bus in response to the second read
21 request; and]
22 wherein the memory device outputs the data synchronously with
23 respect to the external clock signal, during a plurality of clock
24 cycles of the external clock signal and in accordance with the
25 value stored in the time delay register.
- ___ __ - -- ._ - - __
Page 7
- _ . ___ __ - -
1 The method of claim f u r t h e r g :

I ,
recezvln~ a second read reques-a bIl8 coaroller

3 wherein the block size information and the second read request are
4 included in the same request;
5
a
9
10
REMARKS
This Amendment seeks to place this application in condition
for allowance. Several of the pending claims have been amended in
order to more fully and/or definitely claim Applicants' invention.
The specification has been amended to identify the continuation or
related U.S. application data upon which priority is claimed. A
new Abstract of the Disclosure is presented to more fully reflect
the invention claimed herein. Finally, the drawings have been
amended (i.e., added new Figure 16) to more fully illustrate the
features of the claimed invention (See, 37 C.F.R. §1.83(a)) and the
specification has been amended to correspond to new Figure 16. No
new matter has been added.
Page 8
Office A c t i ~ n
In the Office Action mailed July 16, 1999, claims 151-157,
161-163, 165, 168-173, 177-179 and 181 were rejected as being

anticipated by Jackson (U.S. Patent 4,315,308; hereinafter
I'Jackson" or "the Jackson patent"). Several of the claims were
objected to as being dependent upon the rejected claims. Finally,
-
claims 184-188 were found to be allowable.
Jackson discloses a system including a microprocessor 200, a

bus interface unit 201, and peripheral units (e.g., memory) . '
Microprocessor 200 is connected to bus interface unit 201, via
interface lines, i.e., clock line CLK A, ACD bus 214, ISA 215, and
ISB 216. (Jackson, Fig. 1 and col. 4, lines 33-44). Bus interface
unit 201 is connected to the peripheral units. (Jackson, Fig. 1 and
6). Microprocessor 200 communicates with the peripheral units by
means of bus interface unit 201. (Jackson, Fig.1, and col. 4, lines
33-37). In this regard, the bus interface unit 201 provides
interface control of data transfers between the microprocessor 200
and the peripheral units (Jackson, col. 4, lines 16-21), and, in
particular, includes circuitry/means to:
(1) receive and decode instructions (e.g., a read data from
memory instruction as well as data length transfer information)
fromthe microprocessor 200; (See, e.g., Jackson, col. 8, lines 46-
60 and Figs. 6 and 7);
( 2 ) control the memory by asserting the proper control signals

in conjunction with generating and applying address signals
Page 9
necessary to provide the requested number of bytes of data

corresponding to the data length transfer information (i.e.,bits
10, 11 and 12 in the control specification), (See, e.g., Jackson,
col. 8, line 58 to col. 9, line 15, and Figs. 3 and 6);

(3) fetch and buffer data returned from the memory or memory
module in response to the read data instruction, (Jackson, col. 6,
lines 8-12; col. 8, lines 6 5 - 6 8 ; and col. 9, line 3 7 - 4 0 ) ; and
( 4 ) transfer that data to the microprocessor 200 using control
signal ISB to synchronize that transfer relative to clock signal

CLKA. (See, e.g., Jackson, col. 6, lines 8-12; col. 9, line 3 7 - 4 4 ;
and Fig. 7 ) .'
Although Jackson does not describe the memory or memory

modules in any detail, it is most likely that the memory devices,
and modules containing those devices, were standard, off-the-shelf
components. That is, standard, off-the-shelf memory devices and
standard-off-the-shelfmemory modules incorporating such devices,
for example, memory devices like those described in the Kung et
al., U.S. Patent 4,449,207, Voss, U.S. Patent 4 , 6 4 6 , 2 7 9 and Hardee
et al., U.S. Patent 5 , 0 7 7 , 6 9 3 . These memory devices employ such
signals as OE\, C S \ , RAS\, CAS\ and address signals.
Thus, neither the microprocessor 200 nor the bus interface
unit 201 in Jackson provide data length transfer information to the
memory devices or to the memory devices on the memory modules.
It should be noted that claims 3, 4, 7 and 8 of the Jackson

patent also describe the means of, and functions performed by, the
bus interface unit. (Col. 11, lines 3 - 2 7 and Col. 1 2 , lines 2 9 - 5 5 .
Page 10
Rather, the bus interface unit 201 receives and decodes that
information, and, based thereon, generates and applies the
addresses and control signals (i.e.,OE\, RAS\, CAS\) necessary to
obtain the number of bytes of data defined by data length transfer
information. (See, e.g., Jackson, col 8, lines 57-62; col. 9, lines
1-15 and Figs. 6 and 7).
Moreover, it appears that the memory devices or memory modules

employed in Jackson do not receive the clock signal (CLK A ) nor do
they provide data synchronously with respect to that clock signal.
Instead, the bus interface unit 201 fetches the data returned from
the memory, buffers and aligns that data, and then transfers it to
the microprocessor 200, using control signal ISB to synchronize
data transfer relative to CLK A. (See, e . g . , Jackson, col. 6 , lines
8-12; col. 8, lines 65-68; col. 9, line 37-44 and Fig. 7).
151
Amended claim 151 is a method of controlling a synchronous

memory device. Amended claim 151 requires, among other things, the
memory device to be provided first block size information. The
first block size information defines a first amount of data to be
output by the memory device onto a bus in response to a read
request. In addition, claim 151 further requires the memory device
to output the first amount of data corresponding to the first block
size information, in response to a read request, onto the bus
synchronously with respect to an external clock signal.
As mentioned above, the data length transfer information in
Jackson is not provided to the memory devices. Instead, the bus
Page 11
interface unit 201 receives and decodes that information, and,

based thereon, generates the addresses and control signals
necessary to obtain the amount of data defined by data length
transfer information.
Further, the memory devices employed in Jackson did not
provide data synchronously with respect to the external clock
signal. Rather, bus interface unit 201 buffers the data and gates
that data to the microprocessor 200 - - using control signal ISB to
synchronize data transfer relative to clock signal CLK A.
Thus, for at l e a s t those reasons, Jackson does not anticipate
amended claim 151 or the claims which depend therefrom (i.e.,
claims 152-157, 161-163, and 165).
168
Amended claim 168 is a method of operation of a synchronous

memory device. The method requires, among other things, the memory
device to receive first block size information from a bus
controller. Like in claim 151, the first block size information
defines a first amount of data to be output by the memory device
onto a bus in response to a read request.
The method also requires, the memory device to output the
first amount of data corresponding to the first block size
information, in response to the first read request, onto the bus
synchronously with respect to the external clock signal. In claim
168, the memory device receives the external clock signal.
For reasons similar to those mentioned above with respect to

claim 151, the memory devices in Jackson do not receive data length
Page 12
transfer information. Further, the memory devices in Jackson do

not receive the clock signal (CLK A) nor do they provide data
synchronously with respect to the clock signal CLK A.
Thus, for at l e a s t those reasons, Jackson does not anticipate
amended claim 168 or the claims which depend therefrom (i.e., 169-
173, 177-179, and 181).
Amendment to the Specification

The specification has been amended to identify the
continuation or related U.S. application data of this application.
No new matter has been added. In short, this application is a
continuation of Application No. 09/196,199, filed on November 20,
1998 (still pending), which is a continuation of Application No.
08/798,520, filed on February 10, 1997 (now U.S. Patent 5,841,580);

which is a division of Application No. 08/448,657, filed May 24,
1995 (now U.S. Patent 5,638,334); which is a division of
Application No. 08/222,646, filed on March 31, 1994 (now U.S.
Patent 5,513,327); which is a continuation of Application No.
07/954,945, filed on September 30, 1992 (now U.S. Patent
5,319,755);which is a continuation of Application No. 07/510,898,
filed on April 18, 1990 (now abandoned). As such, the instant
application is entitled to an April 18, 1990 priority date.
Moreover, the specification has been amended to correspond to
new Figure 16 - - as is discussed immediately below. No new matter
has been added.
Page 13
Amendment to the Drawings
New Figure 16, attached hereto, is added to illustrate, among

other things, access-time register(s) 173. Figure 16 illustrates
one embodiment of the internal registers within each device
illustrated in Figure 2. Support may be found in the specification
at page 14, lines 3-21 and page 53 lines 4-21. No new matter has
been added.
The specification has been amended to correspond to new Figure
16. No new matter has been added.
By way of note, the amendment to the drawings and the
corresponding amendment of the specification is similar to the
amendment made in the application leading to U.S. Patent 5,841,580.
The I580 patent is the parent of the instant application.
Abstract of the Disclosure

A new Abstract of the Disclosure is attached hereto. No new
matter has been added.
Draftperson's Objections
The Draftperson's objections to the drawings are noted.
Applicants request that these objections be held in abeyance until
this application is found to be in condition for allowance.
Information Disclosure Statements
In compliance with the duty of disclosure set forth in 37

C.F.R. §1.56, Applicants submitted on June 11, 1999, a modified
Form PTO-1449, including a copy of the documents cited therein.
Page 14
(See copy of stamped Postcard receipt, attached hereto). It

appears from the Office Action Summary, that the Examiner has not
yet received Applicants' June 11 Information Disclosure Statement.
A copy of that Information Disclosure Statement is attached hereto.
In addition, Applicants submit herewith a third Information
Disclosure Statement. The fee as prescribed in 37 C.F.R. S1.17(p)
accompanies this Statement. (See, 37 C.F.R. §1.97(c)).
As stated in the Information Disclosure Statements, it is
believed that the Examiner may find the documents cited in the Form
PTO-1449 material to the patentability of one or more of the claims
in the above-referenced application. As such, it is respectfully

requested that the Examiner make his consideration of the documents
cited in the Form PTO-1449 formally of record with the next Action.
CONCLUSION
Applicants respectfully request entry of the foregoing
amendment. Applicants submit that all of the claims present
patentable subject matter which definitely set forth the novel and
unobvious features of Applicants' invention. Applicants
respectfully request reconsideration and allowance of all claims.
It is noted that should a telephone interview expedite the
prosecution in any way, the Examiner is invited to contact Neil
Steinberg at 703-787-9636.
Date: July 23, 1999

Neil A. Stkinberg
Reg. No. 34,735
703-787-9636
Page 15
ABSTRACT OF THE DISCLOSURE
A method of controlling a memory device is disclosed wherein
the memory device includes a plurality of memory cells. The method
comprises providing first block size information to the memory

-1, device, wherein the first ‘block size information defines a first
amount of data to be output onto a bus in response to a read
request. The method further includes issuing a first read request
to the memory device, wherein in response to the first read
request, the memory device outputs the first amount of data
corresponding to the first block size information onto the bus
synchronously with respect to an external clock signal. In one
preferred embodiment, the method may include providing a code which
is representative of a number of clock cycles of the first and
second external clock which are to transpire before data is output
by the memory device onto the bus. The memory device stores the
code in a programmable register on the memory device. In this
preferred embodiment, the first amount of data corresponding to the
first block size information is output after the number of clock
cycles of the external clock transpire.

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Case 5:05-cv-00334-RMW Document 2543-2 Filed 11/14/2008 Page 1 of 106

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY REGARDING

VALIDITY IN LIGHT OF THE BENNETT AND NOVAK REFERENCES

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

implementing bused interconnections among various components of a computer system. In order

to allow many disparate types of components to be interconnected, Bennett describes a

multiplexed or not, and the number of bits in a data word – to be varied.

placed on memory chips.

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

containing the Bennett interface in order to connect to the Versatile Bus.

order to add an unnecessary, complex interface.

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

7. Bennett discloses that 24 pins are required simply to connect components

to this number of pins as “modest” in relation to a memory chip.

devices, synchronous semiconductor memory devices, or synchronous dynamic random access

‘a method of operation of a synchronous dynamic random access memory device.’ These

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

single chip when it wished to do so.”)

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

devices do not alone determine the actual configuration of the device.

discloses no such correlation.

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

parameter (“GROUP LINES”) of the configuration register shown in Figure 3 of Bennett

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

mandates a one cycle difference between the two configurations.

17. Moreover, the possibility of asserting a WAIT signal results in additional

arbitration with other components for control of the bus. Id.

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

described as “a dedicated signal input to indicate or command at will the termination of an

otherwise fixed-length burst in progress, thereby achieving variable-length bursts on-the-fly

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

Bennett, Col. 17:29-31 (emphasis added).

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

and centered with respect to write data.”

of Redwine are not present in Novak.

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

that are intended to be involved in a given serial read or write operation.

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

. . . .”) (emphasis added).

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

relationship between the transitions of the control signals and Φ.

the control signals.

no disclosure in Novak of a known timing relationship between A6 and A7 and Φ. According to

does not establish a known timing relationship between A6 and A7 and Φ.

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

“transaction request” as “a series of bits used to request performance of a transaction with a

synchronous memory device.

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

of the response to a serial read or write operation as Mr. McAlexander asserts.

64 shifts or less, rather than 256 shifts.” Novak, Col. 7:38-40.

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

CRT tube. Novak, Fig. 1; Col. 4:2-6.

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

loading of data into the shift register).

for the device to operate correctly.

[T]he precharge information does not simply convey a value

SUPPLEMENTAL EXPERT REPORT OF ROBERT J. MURPHY

precharging]. Instead it conveys whether the device should

Hynix I Claim Construction Order at 23 (emphasis added).