C.I 74HC373

74HC373; 74HCT373
Octal D-type transparent latch; 3-state

Rev. 4 3 September 2010 Product data sheet
1. General description
The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A. The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches. The 74HC373; 74HCT373 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D input changes. When LE is LOW the latches store the information that was present at the D inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the highimpedance OFF-state. Operation of the OE input does not affect the state of the latches. The 74HC373; 74HCT373 is functionally identical to:
74HC563; 74HCT563: but inverted outputs and different pin arrangement 74HC573; 74HCT573: but different pin arrangement
2. Features and benefits

3-state non-inverting outputs for bus oriented applications Common 3-state output enable input Functionally identical to the 74HC563; 74HCT563 and 74HC573; 74HCT573 ESD protection: HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V Specified from 40 C to +85 C and from 40 C to +125 C
NXP Semiconductors
74HC373; 74HCT373
3. Ordering information
Table 1. Ordering information Temperature range 74HC373N 74HCT373N 74HC373D 74HCT373D 74HC373DB 74HCT373DB 74HC373PW 74HCT373PW 74HC373BQ 74HCT373BQ 40 C to +125 C DHVQFN20 40 C to +125 C TSSOP20 40 C to +125 C SSOP20 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm plastic shrink small outline package; 20 leads; body width 5.3 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 4.5 0.85 mm SOT163-1 SOT339-1 SOT360-1 SOT764-1 40 C to +125 C Name DIP20 Description plastic dual in-line package; 20 leads (300 mil) Version SOT146-1 Type number Package
4. Functional diagram
3 4 7 8 13 14 17 18 11 1
D0 D1 D2 D3 D4 D5 D6 D7 LE OE
LATCH 1 TO 8
3-STATE OUTPUTS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
001aae050
Fig 1.
Functional diagram
74HC_HCT373
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 3 September 2010
2 of 26
NXP Semiconductors
74HC373; 74HCT373
OE LE 11 3 4 7 8 13 14 17 18 LE D0 D1 D2 D3 D4 D5 D6 D7 OE 1
001aae048
1 11
EN C1
D0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 D1 D2 D3 D4 D5 D6 D7
3 4 7 8 13 14 17 18
1D
2 5 6 9 12 15 16 19
001aae049
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
LE
LE LE D Q
LE
001aae051
Fig 4.
Logic diagram (one latch)
D0
D1
D2
D3
D4
D5
D6
D7
LATCH 1 LE LE
LATCH 2 LE LE
LATCH 3 LE LE
LATCH 4 LE LE
LATCH 5 LE LE
LATCH 6 LE LE
LATCH 7 LE LE
LATCH 8 LE LE
LE OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aae052
Fig 5.
Logic diagram
74HC_HCT373
Product data sheet
3 of 26
NXP Semiconductors
74HC373; 74HCT373
5. Pinning information
5.1 Pinning
74HC373 74HCT373
OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 1 2 3 4 5 6 7 8 9 20 VCC 19 Q7 Q0 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 LE
001aae046
74HC373 74HCT373
terminal 1 index area 2 3 4 5 6 7 8 9 GND 10 LE 11 GND(1) 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 OE 1 D0 D1 Q1 Q2 D2 D3 Q3
GND 10
001aae047
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input.
Fig 6.
Pin configuration DIP20, SO20, SSOP20 and TSSOP20
Fig 7.
Pin configuration DHVQFN20
5.2 Pin description

Table 2. Symbol OE Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 D0, D1, D2, D3, D4, D5, D6, D7 GND LE VCC Pin description Pin 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 10 11 20 Description 3-state output enable input (active LOW) 3-state latch output data input ground (0 V) latch enable input (active HIGH) supply voltage
74HC_HCT373
Product data sheet
4 of 26
NXP Semiconductors
74HC373; 74HCT373
6. Functional description
6.1 Function table
Table 3. Function table[1] Control OE Enable and read register (transparent mode) Latch and read register Latch register and disable outputs
[1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; X = dont care; Z = high-impedance OFF-state.
Operating mode
Input LE H L X Dn L H l h X
Internal latches L H L H X
Output Qn L H L H Z
L L H
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation DIP20 package SO20 package SSOP20 package TSSOP20 package DHVQFN20 package
[1] [2] [3] [4] For DIP20 package: Ptot derates linearly with 12 mW/K above 70 C. For SO20: Ptot derates linearly with 8 mW/K above 70 C. For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 C.
[1] [2] [3] [3] [4]
Conditions VI < 0.5 V or VI > VCC + 0.5 V VO < 0.5 V or VO > VCC + 0.5 V VO = 0.5 V to (VCC + 0.5 V)
Min 0.5 65 -
Max +7 20 20 35 +70 70 +150 750 500 500 500
Unit V mA mA mA mA mA C mW mW mW mW mW
500
74HC_HCT373
Product data sheet
5 of 26
NXP Semiconductors
74HC373; 74HCT373
8. Recommended operating conditions

Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC VI VO Tamb t/V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Conditions Min 2.0 0 0 40 74HC373 Typ 5.0 +25 1.67 Max 6.0 VCC VCC +125 625 139 83 Min 4.5 0 0 40 74HCT373 Typ 5.0 +25 1.67 Max 5.5 VCC VCC +125 139 V V V C ns/V ns/V ns/V Unit
9. Static characteristics
Table 6. Static characteristics 74HC373 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VIH Parameter HIGH-level input voltage Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 6.0 mA; VCC = 4.5 V IO = 7.8 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 6.0 mA; VCC = 4.5 V IO = 7.8 mA; VCC = 6.0 V II IOZ ICC CI
74HC_HCT373
Min 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 -
Typ 1.2 2.4 3.2 0.8 2.1 2.8 2.0 4.5 6.0 4.32 5.81 0 0 0 0.15 0.16 3.5
Max 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 0.5 8.0 -
Unit V V V V V V V V V V V V V V V V A A A pF
Tamb = 25 C
input leakage current OFF-state output current supply current input capacitance
VI = VCC or GND; VCC = 6.0 V VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND VCC = 6.0 V; IO = 0 A; VI = VCC or GND
Product data sheet
6 of 26
NXP Semiconductors
74HC373; 74HCT373
Table 6. Static characteristics 74HC373 continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VIH Parameter HIGH-level input voltage Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 6.0 mA; VCC = 4.5 V IO = 7.8 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 6.0 mA; VCC = 4.5 V IO = 7.8 mA; VCC = 6.0 V II IOZ ICC input leakage current OFF-state output current supply current VI = VCC or GND; VCC = 6.0 V VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND VCC = 6.0 V; IO = 0 A; VI = VCC or GND VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 6.0 mA; VCC = 4.5 V IO = 7.8 mA; VCC = 6.0 V 1.9 4.4 5.9 3.7 5.2 V V V V V 1.5 3.15 4.2 0.1 0.1 0.1 0.33 0.33 1.0 5.0 80 V V V V V A A A 1.9 4.4 5.9 3.84 5.34 V V V V V Min 1.5 3.15 4.2 Typ Max 0.5 1.35 1.8 Unit V V V V V V Tamb = 40 C to +85 C
Tamb = 40 C to +125 C VIH HIGH-level input voltage 0.5 1.35 1.8 V V V V V V
74HC_HCT373
Product data sheet
7 of 26
NXP Semiconductors
74HC373; 74HCT373
Table 6. Static characteristics 74HC373 continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VOL Parameter LOW-level output voltage Conditions VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 6.0 mA; VCC = 4.5 V IO = 7.8 mA; VCC = 6.0 V II IOZ ICC input leakage current OFF-state output current supply current VI = VCC or GND; VCC = 6.0 V VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND VCC = 6.0 V; IO = 0 A; VI = VCC or GND 0.1 0.1 0.1 0.4 0.4 1.0 10.0 160 V V V V V A A A Min Typ Max Unit
Table 7. Static characteristics 74HCT373 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VIH VIL VOH Parameter HIGH-level input voltage LOW-level input voltage HIGH-level output voltage Conditions VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VIH or VIL IO = 20 A; VCC = 4.5 V IO = 6.0 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 4.5 V IO = 6.0 mA; VCC = 4.5 V II IOZ input leakage current OFF-state output current VI = VCC or GND; VCC = 5.5 V VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A VI = VCC or GND; IO = 0 A; VCC = 5.5 V VI = VCC 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A Dn LE OE CI VIH VIL input capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V Tamb = 40 C to +85 C 2.0 0.8 V V 30 150 100 3.5 108 540 360 A A A pF 0.0 0.16 0.1 0.26 0.1 0.5 V V A A 4.4 3.98 4.5 4.32 V V Min 2.0 Typ 1.6 1.2 Max 0.8 Unit V V Tamb = 25 C
ICC ICC
supply current additional supply current
8.0
74HC_HCT373
Product data sheet
8 of 26
NXP Semiconductors
74HC373; 74HCT373
Table 7. Static characteristics 74HCT373 continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol VOH Parameter HIGH-level output voltage Conditions VI = VIH or VIL IO = 20 A; VCC = 4.5 V IO = 6.0 A; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 4.5 V IO = 6.0 mA; VCC = 4.5 V II IOZ input leakage current OFF-state output current VI = VCC or GND; VCC = 5.5 V VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A VI = VCC or GND; IO = 0 A; VCC = 5.5 V VI = VCC 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A Dn LE OE Tamb = 40 C to +125 C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V VI = VIH or VIL IO = 20 A; VCC = 4.5 V IO = 6.0 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 4.5 V IO = 6.0 mA; VCC = 4.5 V II IOZ input leakage current OFF-state output current VI = VCC or GND; VCC = 5.5 V VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A VI = VCC or GND; IO = 0 A; VCC = 5.5 V VI = VCC 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A Dn LE OE 147 735 490 A A A 0.1 0.4 1.0 10 V V A A 4.4 3.7 V V 2.0 0.8 V V 135 675 450 A A A 0.1 0.33 1.0 5.0 V V A A 4.4 3.84 V V Min Typ Max Unit
ICC ICC
80
ICC ICC
160
74HC_HCT373
Product data sheet
9 of 26
NXP Semiconductors
74HC373; 74HCT373
10. Dynamic characteristics

Table 8. Dynamic characteristics 74HC373 Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Tamb = 25 C tpd propagation delay Dn to Qn; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 5 V; CL = 15 pF VCC = 6.0 V LE to Qn; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 5 V; CL = 15 pF VCC = 6.0 V ten enable time OE to Qn; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tdis disable time OE to Qn; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tt transition time Qn; see Figure 8 and Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW pulse width LE HIGH; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tsu set-up time Dn to LE; see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V th hold time Dn to LE; see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CPD power dissipation capacitance per latch; VI = GND to VCC
[5] [4] [3] [2] [1]
Conditions
Min
Typ
Max
Unit
80 16 14 50 10 9 +5 +5 +5 -
41 15 12 12 50 18 15 14 44 16 13 47 17 14 14 5 4 17 6 5 14 5 4 8 3 2 45
150 30 26 175 35 30 150 30 26 150 30 26 60 12 10 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF
74HC_HCT373
Product data sheet
10 of 26
NXP Semiconductors
74HC373; 74HCT373
Table 8. Dynamic characteristics 74HC373 continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Tamb = 40 C to +85 C tpd propagation delay Dn to Qn; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V LE to Qn; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V ten enable time OE to Qn; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tdis disable time OE to Qn; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tt transition time Qn; see Figure 8 and Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW pulse width LE HIGH; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tsu set-up time Dn to LE; see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V th hold time Dn to LE; see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 5 5 5 ns ns ns 65 13 11 ns ns ns 100 20 17 ns ns ns
[4] [3] [2] [1]
Conditions
Min
Typ
Max
Unit
190 38 33 220 44 37 190 38 33 190 38 33 75 15 13
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
74HC_HCT373
Product data sheet
11 of 26
NXP Semiconductors
74HC373; 74HCT373
Table 8. Dynamic characteristics 74HC373 continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Tamb = 40 C to +125 C tpd propagation delay Dn to Qn; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V LE to Qn; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V ten enable time OE to Qn; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tdis disable time OE to Qn; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tt transition time Qn; see Figure 8 and Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW pulse width LE HIGH; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tsu set-up time Dn to LE; see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 75 15 13 ns ns ns 120 24 20 ns ns ns
[4] [3] [2] [1]
Conditions
Min
Typ
Max
Unit
225 45 38 265 53 45 225 45 38 225 45 38 90 18 15
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
74HC_HCT373
Product data sheet
12 of 26
NXP Semiconductors
74HC373; 74HCT373
Table 8. Dynamic characteristics 74HC373 continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter th hold time Conditions Dn to LE; see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
[1] [2] [3] [4] [5] tpd is the same as tPLH and tPHL. ten is the same as tPZH and tPZL. tdis is the same as tPLZ and tPHZ. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs.
Min 5 5 5
Typ -
Max -
Unit ns ns ns
Table 9. Dynamic characteristics 74HCT373 Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Tamb = 25 C tpd propagation delay Dn to Qn; see Figure 8 VCC = 4.5 V VCC = 5 V; CL = 15 pF LE to Qn; see Figure 9 VCC = 4.5 V VCC = 5 V; CL = 15 pF ten tdis tt tW tsu th CPD enable time disable time transition time pulse width set-up time hold time power dissipation capacitance OE to Qn; see Figure 10 VCC = 4.5 V OE to Qn; see Figure 10 VCC = 4.5 V Qn; see Figure 8 and Figure 9 VCC = 4.5 V LE HIGH; see Figure 9 VCC = 4.5 V Dn to LE; see Figure 11 VCC = 4.5 V Dn to LE; see Figure 11 VCC = 4.5 V per latch; VI = GND to (VCC 1.5 V)
[5] [4] [3] [2] [1]
Conditions
Min
Typ
Max
Unit
16 12 4 -
17 14 16 13 19 18 5 4 6 1 41
30 32 32 30 12 -
ns ns ns ns ns ns ns ns ns ns pF
74HC_HCT373
Product data sheet
13 of 26
NXP Semiconductors
74HC373; 74HCT373
Table 9. Dynamic characteristics 74HCT373 continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Tamb = 40 C to +85 C tpd propagation delay Dn to Qn; see Figure 8 VCC = 4.5 V LE to Qn; see Figure 9 VCC = 4.5 V ten tdis tt tW tsu th enable time disable time transition time pulse width set-up time hold time OE to Qn; see Figure 10 VCC = 4.5 V OE to Qn; see Figure 10 VCC = 4.5 V Qn; see Figure 8 and Figure 9 VCC = 4.5 V LE HIGH; see Figure 9 VCC = 4.5 V Dn to LE; see Figure 11 VCC = 4.5 V Dn to LE; see Figure 11 VCC = 4.5 V Tamb = 40 C to +125 C tpd propagation delay Dn to Qn; see Figure 8 VCC = 4.5 V LE to Qn; see Figure 9 VCC = 4.5 V ten tdis tt tW tsu enable time disable time transition time pulse width set-up time Dn to LE OE to Qn; see Figure 10 VCC = 4.5 V OE to Qn; see Figure 10 VCC = 4.5 V Qn; see Figure 8 and Figure 9 VCC = 4.5 V LE HIGH; see Figure 9 VCC = 4.5 V Dn to LE; see Figure 11 VCC = 4.5 V 18 ns 24 ns
[4] [3] [2] [1] [4] [3] [2] [1]
Conditions
Min
Typ
Max
Unit
20 15 4
38 40 40 38 15 -
ns ns ns ns ns ns ns ns
45 48 48 45 18
ns ns ns ns ns
74HC_HCT373
Product data sheet
14 of 26
NXP Semiconductors
74HC373; 74HCT373
Table 9. Dynamic characteristics 74HCT373 continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter th hold time Dn to LE Conditions Dn to LE; see Figure 11 VCC = 4.5 V
[1] [2] [3] [4] [5] tpd is the same as tPLH and tPHL. ten is the same as tPZH and tPZL. tdis is the same as tPLZ and tPHZ. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs.
Min 4
Typ -
Max -
Unit ns
11. Waveforms
Dn input
VM
t PLH 90 % Qn output VM 10 % t TLH
t PHL
t THL
001aae082
Measurement points are given in Table 10.
Fig 8.
Propagation delay input (Dn) to output (Qn) and transition time output (Qn)
LE input
VM
tW t PHL 90 % Qn output t THL VM 10 % t TLH

001aae083
t PLH
Fig 9.
Pulse width latch enable input (LE), propagation delay (LE) to output (Qn) and transition time output (Qn)
74HC_HCT373
Product data sheet
15 of 26
NXP Semiconductors
74HC373; 74HCT373
VI OE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled 90% VM VM 10% tPZH tPZL VM
outputs disabled
outputs enabled
001aae307
Fig 10.
3-state enable and disable time
LE input
VM
t su th
t su th
Dn input
VM
001aae084
Fig 11. Set-up and hold time data input (Dn) to latch enable input (LE) Table 10. Type 74HC373 74HCT373 Measurement points Input VM 0.5VCC 1.3 V Output VM 0.5VCC 1.3 V
74HC_HCT373
Product data sheet
16 of 26
NXP Semiconductors
74HC373; 74HCT373
VI negative pulse 0V
tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM
VI positive pulse 0V
VCC
VCC
VI
VO
RL
S1
DUT
RT CL
open
001aad983
Test data is given in Table 11. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistor S1 = Test selection switch
Fig 12. Test circuit for measuring switching times Table 11. Type 74HC373 74HCT373 Test data Input VI VCC 3V tr, tf 6 ns 6 ns Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 k 1 k S1 position tPHL, tPLH open open tPZH, tPHZ GND GND tPZL, tPLZ VCC VCC
74HC_HCT373
Product data sheet
17 of 26
NXP Semiconductors
74HC373; 74HCT373
12. Package outline

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
D seating plane
ME
A2
A1
c Z e b1 b 20 11 MH w M (e 1)
pin 1 index E
10
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
(1)
e 2.54 0.1
e1 7.62 0.3
L 3.60 3.05 0.14 0.12
ME 8.25 7.80 0.32 0.31
MH 10.0 8.3 0.39 0.33
w 0.254 0.01
Z (1) max. 2 0.078
26.92 26.54 1.060 1.045
6.40 6.22 0.25 0.24
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC MS-001 JEITA SC-603 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
Fig 13. Package outline SOT146-1 (DIP20)

74HC_HCT373 All information provided in this document is subject to legal disclaimers. NXP B.V. 2010. All rights reserved.
Product data sheet
18 of 26
NXP Semiconductors
74HC373; 74HCT373
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
A X
c y HE v M A
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 w M detail X (A 3) A
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
8o o 0
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 14. Package outline SOT163-1 (SO20)

Product data sheet
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NXP Semiconductors
74HC373; 74HCT373
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
A X
c
y
HE
v M A
Z
20 11
Q A2
pin 1 index
A1
(A 3) Lp L
10
detail X
bp
w M
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3
0.25
bp 0.38 0.25
c 0.20 0.09
D (1) 7.4 7.0
E (1) 5.4 5.2
e 0.65
HE 7.9 7.6
L 1.25
Lp 1.03 0.63
Q 0.9 0.7
v 0.2
w 0.13
y 0.1
Z (1) 0.9 0.5
8 o 0
o
ISSUE DATE 99-12-27 03-02-19
Fig 15. Package outline SOT339-1 (SSOP20)

Product data sheet
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NXP Semiconductors
74HC373; 74HCT373
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
c y HE v M A
20
11
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
10
w M detail X
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 16. Package outline SOT360-1 (TSSOP20)

Product data sheet
21 of 26
NXP Semiconductors
74HC373; 74HCT373
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm
A A1 E c
terminal 1 index area
detail X
terminal 1 index area e 2 L
e1 b 9 v M C A B w M C y1 C
C y
1 Eh 20
10 e 11
19 Dh 0
12 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.6 4.4 Dh 3.15 2.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT764-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
Fig 17. Package outline SOT764-1 (DHVQFN20)

Product data sheet
22 of 26
NXP Semiconductors
74HC373; 74HCT373
13. Abbreviations
Table 12. Acronym CMOS ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic
14. Revision history

Table 13. Revision history Release date 20100903 Data sheet status Product data sheet Change notice Supersedes 74HC_HCT373 v.3 Document ID 74HC_HCT373 v.4 Modifications:
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Figure 5 changed: inversion sign added to the output buffers. Product data sheet Product specification 74HC_HCT373_CNV v.2 -
74HC_HCT373 v.3 74HC_HCT373_CNV v.2
20060120 19970827
74HC_HCT373
Product data sheet
23 of 26
NXP Semiconductors
74HC373; 74HCT373
15. Legal information

15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term short data sheet is explained in section Definitions. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customers sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customers applications and products planned, as well as for the planned application and use of customers third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customers applications or products, or the application or use by customers third party customer(s). Customer is responsible for doing all necessary testing for the customers applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customers third party customer(s). NXP does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customers general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
15.3 Disclaimers
Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be
74HC_HCT373
Product data sheet
24 of 26
NXP Semiconductors
74HC373; 74HCT373
Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT373
Product data sheet
25 of 26
NXP Semiconductors
74HC373; 74HCT373
17. Contents
1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 23 Legal information. . . . . . . . . . . . . . . . . . . . . . . 24 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contact information. . . . . . . . . . . . . . . . . . . . . 25 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information.
NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 September 2010 Document identifier: 74HC_HCT373

C.I 74HC373

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Verfügbare Formate

74HC373; 74HCT373

Octal D-type transparent latch; 3-state

2. Features and benefits

All information provided in this document is subject to legal disclaimers.

NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 4 3 September 2010

IEC logic symbol

Logic diagram (one latch)

All information provided in this document is subject to legal disclaimers.

NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 4 3 September 2010

Transparent top view

Pin configuration DIP20, SO20, SSOP20 and TSSOP20

Pin configuration DHVQFN20

5.2 Pin description

All information provided in this document is subject to legal disclaimers.

NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 4 3 September 2010

Max +7 20 20 35 +70 70 +150 750 500 500 500

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NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 4 3 September 2010

8. Recommended operating conditions

Min 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 -

All information provided in this document is subject to legal disclaimers.

NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 4 3 September 2010

Tamb = 40 C to +125 C VIH HIGH-level input voltage 0.5 1.35 1.8 V V V V V V

All information provided in this document is subject to legal disclaimers.

NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 4 3 September 2010

supply current additional supply current

All information provided in this document is subject to legal disclaimers.

NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 4 3 September 2010

supply current additional supply current

supply current additional supply current

All information provided in this document is subject to legal disclaimers.

NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 4 3 September 2010

10. Dynamic characteristics

150 30 26 175 35 30 150 30 26 150 30 26 60 12 10 -

All information provided in this document is subject to legal disclaimers.

NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 4 3 September 2010

190 38 33 220 44 37 190 38 33 190 38 33 75 15 13

All information provided in this document is subject to legal disclaimers.

NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 4 3 September 2010

225 45 38 265 53 45 225 45 38 225 45 38 90 18 15

All information provided in this document is subject to legal disclaimers.

NXP B.V. 2010. All rights reserved.

Product data sheet