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# S.R.M.

Institute of Science and Technology (Deemed University) School of Electronics and Communication Engineering QUESTION BANK Subject Code Subject Name Class & Sem : : : EM506 VLSI Architecture and Design Methodologies I Year M.Tech (Embedded Systems), II Sem. Unit - I PART A 1. State consensus theorem with a suitable example? 2. State Shannon Expansion theorem with on suitable example? 3. What is meant by hazard & what are its various types? 4. Define static & dynamic hazard with a suitable example? 5. Define octal designation & various form of octal designation? 6. Octal designation of a number is 256. Express in its CCF & DCF forms? 7. Given characteristic no:01001011. Express its CCF&DCF forms? 8. State & obtain the run measure of the following Boolean sum F(a,b,c)= (1,2,3,5,6) 9. State read Muller Expansion with a suitable example? 10. State Involution, Idempotent, simplification theorem with a suitable example? 11. Explain in short the procedure for detecting static 0/1 hazard in a digit ckt? 12. Explain the signification of buffer gates? 13. Explain with an suitable example logic Expander? PART B 14. i) Expand the function F=AB+BC+D write B using Shannon expression Theorem. ii) Implement the function Y=AB+CD using multiplexer. iii) Explain the use of gate Expander technique. 15. i) Distinguish B/W static & dynamic hazards ii) Implement the function f=1x2+x1x3 without hazards iii) Give an example of dynamic hazards & how it can be presented 16. i) Explain the consensus theorem & its application ii) Explain how the read mailer Expression of a logical function is obtained with an Example? iii) Explain how the logic function can be implemented using look up table

17. With an Example explain how the multiple output logical circuit is synthesized using product map method 18. Realise the static o/p hazard free network for the following Boolean function ft=abc+ (a+d)a1+c1 Unit - II PART A 1. What are the advantages of CMOS devices using SOI process? 2. Compare the 3 types of MOS switches? 3. Explain body effect with an suitable example? 4. Explain the channel length modulation and its significance in MOS device modeling using suitable example? 5. Explain what is Implant ionization and its significance? 6. What is latch-up in CMOS devices and way to prevent it in CMOS devices? 7. State Layout design rules with its significance in CMOS devices? 8. Explain Noise Margin in CMOS devices with an suitable example? 9. Implement the basic Universal logic gate using CMOS switch logic? 10. Implement the function F=AB+C(A+B) using CMOS switch logic/ 11. Explain the schottky barrier potential? PART B 1. i) Explain how CMOS circuit are fabricated using SOI? ii) What does Latchup mean in CMOS circuits? Explain any 3 techniques for its prevention? 2. a) Compare the performance of MOS & CMOS switches? b) Draw the circuit diagram of EXOR gate implemented using CMOS switches? c) What is meant by layout design rules? Why they are required in VLSI design? 3. a) List the steps used in Fabrication of CMOS devices? b) Explain hoe the threshold voltage of MOS transistor can be varied? c) Show how 4:1 MUX can be implemented using CMOS switches? 4. a) What is meant by layout design rule? Why are they required? b) Draw the symbolic layout diagram of 2-input NAND gate? c) Draw the circuit diagram EX-NOR GATE using MOS transistors?asdf 5. Write the fabrication process involved in GaAs technology? 6. Explain the fabrication process of CMOS SOI insulator technology?

UNIT-III PART A 1. What are different types of ASICs? Draw the plot relating cost Vs Volume for these ASICs? 2. What is meant by ASIC design flow? Give brief description of the function of each step/ 3. Design logic Macro using Actel ACT series? 4. Explain Shannons Expansion Theorem with a suitable example for implementing in ACTEL Act series? 5. Explain the concept of Antifuse in Programmable ASIC? 6. Explain the terms logic Expander with an suitable example? 7. Explain what is supply and ground bounce in programmable ASICs? 8. Explain what is metastability with an suitable example? 9. What is meant by Mean time between upset? 10. Explain Boundary Scan methods in Xilinx RPGA? PART B 1. a) Explain the construction of EPROM cell? b) Give examples of programmable logic devices with I) In-System programmability II) Deterministic routing delay III) Re-programmability c) Explain the use of PREP benchmarks? 2. a) Explain the I/O cell in programmable ASIC for I)AC inputs II)clock inputs b) Explain what is meant by metastability? 3. Explain the basic logic cell array structure in Xilinx 3000 and 5200 series CLBs available? 4. Explain the logic macros cell structure involves in Later FLEX FPGA series? 5. Explain the I/O cells programmable ASIC for I) A/C output II) DC output? UNIT-IV PART A 1. What is meant by EDIF? What is its use/ 2. Draw the ACTI logic module? 3. Derive the equation for Elmore time constant?

4. Explain the term Logic synthesis in ASIC with a suitable example? 5. Explain Xilinx FPGA design flow with a suitable example? 6. Explain what is Half gate ASIC? 7. Explain what is back-annotation in ASIC design? 8. Explain hierarchical design structure in ASIC design flow? 9. Explain what is EDIF syntax with a suitable example? 10. Explain what is CFI design and its connectivity with an suitable example? PART B 1. a) Draw the flowchart ASIC design and Explain the function performed in each of the stages? b) Explain the three techniques for implementing the programmable interconnect.? 2. i) Explain the internal architecture of Xilinx LCA? ii) What is meant by logic synthesis? What are different approaches used for logic synthetis? 3. i) What are the different techniques available for design entry? Discuss their relative merits? ii) Explain the features of low level design languages? 4. i) Explain the Xilinx FPGA design flow? ii) Explain basic techniques used for logic synthesis/ iii) Explain how the programmable of Half gate ASIC differs when it is implemented using ACTEL, Xilinx, Altera, FPGAs/CPLDs. 5. i) Explain the features of schematic Entry Tools? ii) What is meant by Back Annotation? iii) Explain the features of EDIF with a neat sketch? 6. Explain the EDIF and CIF design structure involved in ASIC construction? UNIT-V PART A 1. What is the fault model used in VLSI design methodologies? 2. Explain any two techniques for fault simulation? 3. Explain the VHDL date types in brief? 4. Explain the various modeling involved in VHLD design flow? 5. Explain the significance of Boundary Scan Test in VLSI Circuits? 6. Explain the concept of Automatic Test Pattern Generation in VLSI Testing?

7. State and Explain the various techniques involved in ATPG methods? 8. Distinguish between behavioral and structural modeling in VHDL design? 9. Explain the various VHDL simulations in practice? 10. Explain the concepts involved in VHDL synthesis? PART B 1. i) Explain the structure of a VHDL model for a digital system with an example? ii) Explain how registers and counters are modeled in VHDL? iii) List the various data types supported by VHDL languages? 2. i) Explain the terms a) Observability b) Fault Coverage with respect to Digital system design? ii) Explain any one important self-test technique with a neat sketch? 3. i) Explain the different date types used in VHDL modeling? ii) Write the structural level VHDL programming for a 4-bit Ripple carry adder? 4. i) Explain the need for manufacturing test? ii) Explain the different techniques for fault simulation? iii) Explain the Adhoc technique using is VLSI testing? 5. i) Explain the various ATPG algorithm used in VLSI testing? ii) Explain the PODEM algorithm with a suitable example?