Curriculum Vitae VARUN PARASHAR

Masters of Science Electronics Dept. Of Electronics Sciences Delhi University Phone: +91 9818652292 +9111 25129690 Present Address FLAT NO 47-A DA BLOCK HARI NAGAR NEW DELHI-110064 Objective A responsible and challenging position with an organization, where education and ability can be used for professional growth and advancement, commensurate with the organizational objectives. Proficiency Operating Systems Programming languages Softwares and Simulator Educational Qualifications

: Windows and UNIX. : Visual basics, C, C++ : VHDL Pspice Virtuoso and Calibre

MSc Electronics from Department Of Electronics Sciences, Delhi University South Campus, with 74.07% . BSc.(H) Electronics from Sri Venkateswara Collage, Delhi University, New Delhi in 2009 with 74.93%. Class XIIth from Kendriya Vidyalaya, Janak Puri, New Delhi (C.B.S.E. Board), in 2006 with 87.4% Class Xth from Kendriya Vidyalaya, Janak Puri, New Delhi (C.B.S.E.Board), in 2004 with 78.4%

E-Mail: parashar.varun88@gmail.com Personal Details: DoB :Oct,01,1988 Sex :Male Nationality :Indian Marital Status : Single Lang. Known : English, Hindi Hobbies: Listening to music Playing Chess and Cricket

Extracurricular Activities

Semifinalist in the Inter-Departmental Chess Tournament at Masters level Part of the runners up team in the Inter-Departmental Cricket Tournament at graduation level. Runner up in the Inter-Departmental Chess Tournament at graduation level. Participated in Technical Fest at graduation as well as masters.

Key Skills Can work effectively in team, as well as individually. Have good inter-personal skills. Quick learner and dedicated to my work.

ACADEMIC PROJECTS AND SEMINARS

Project titled DESIGN AND SIMULATION OF OPTICAL INTEGRATED CIRCUITS USING BPM CAD SIMULATOR in M.Sc. 4th sem Gave seminar on Halographic Memories in M.Sc. Project based on Microprocessor 8085 titled TEMPRATURE CONTROLLER in B.Sc. 3rd year. Project based on Visual Basics 6.0 and Oracle titled TELEPHONE EXCHANGE MANAGEMENT SYSTEM in class 12th.

TRAINING AND WORK EXPERIENCE Summer training at Central Electronics Limited in SPD on UNIVERSAL AXLE COUNTER in M.Sc. II year.

Presently working in CMR Design and Automation as a Layout Engineer (On site ST MICROELECTRONICS in TR&D Department Digital Logic Group) since July 2012. I joined Back-End Team of Digital Logic Group in TR&D Department.The role assigned to me was to develop Layouts from schemetics. The Projects undertaken in the Last 6 months are
1.

Adding DFM in the Layouts in CORE libraries in CMOSM10ULP Plateform.

2. Implementing CDM protection in 8T and 16T Level Shifter libraries in CMOS028 technology. 3. Developing Level Shifter libraries with CDM protection in CMOS040 technology for various Domains. 4. Development of layouts in different pitches and height for PNR trails for High Density plateform in BCD9S. 5. Regression work in BCD9S and CMOSM65 technology. 6. Performing various checks (DRC,LVS etc) for Various final Back-End products

Personal Contribution to the Group 1. Developing CDM structure in CMOS028 CMOS032 and CMOS040 technology. 2. Architecture Finalisation in CMOS040 Level Shifters.

3. Given the responsibility of reviewing layouts of all the group members in BCD9S trials. 4. Provided Libkit support and Skills across technology.