What are the Basic Differences Between CMOS and TTL Signals?

Hardware: Multifunction DAQ (MIO) Problem: What are the Basic Differences Between CMOS and TTL Signals? Solution: Characteristics of CMOS logic: 1. Dissipates low power: The power dissipation is dependent on the power supply voltage, frequency, output load, and input rise time. At 1 MHz and 50 pF load, the power dissipation is typically 10 nW per gate. 2. Short propagation delays: Depending on the power supply, the propagation delays are usually around 25 nS to 50 nS. 3. Rise and fall times are controlled: The rise and falls are usually ramps instead of step functions, and they are 20 - 40% longer than the propagation delays. 4. Noise immunity approaches 50% or 45% of the full logic swing. 5. Levels of the logic signal will be essentially equal to the power supplied since the input impedance is so high. Characteristics of TTL logic: 1. Power dissipation is usually 10 mW per gate. 2. Propagation delays are 10 nS when driving a 15 pF/400 ohm load. 3. Voltage levels range from 0 to Vcc where Vcc is typically 4.75V - 5.25V. Voltage range 0V 0.8V creates logic level 0. Voltage range 2V - Vcc creates logic level 1. CMOS compared to TTL: 1. CMOS components are typically more expensive that TTL equivalents. However, CMOS technology is usually less expensive on a system level due to CMOS chips being smaller and requiring less regulation. 3. CMOS circuits do not draw as much power as TTL circuits while at rest. However, CMOS power consumption increases faster with higher clock speeds than TTL does. Lower current draw requires less power supply distribution, therefore causing a simpler and cheaper design. 4. Due to longer rise and fall times, the transmission of digital signals become simpler and less expensive with CMOS chips. 5. CMOS components are more susceptible to damage from electrostatic discharge than TTL compenents.

Resource: National Semiconductor CMOS Logic Databook and National Semiconductor LS/S/TTL Logic Databook

Answer
TTL is less sensitive to static-discharge failure and less expensive. It is also faster.

Answer
There is a condition called "latch up" that can happen with CMOS circuits if an overvoltage is applied during operation, so you have to design the input/output buffers to suit the operating conditions, like if a wire is attached. The first commercial applications of CMOS were by a company called Integrated Device Technology (IDT). Strangely enough, the singular advantage at that time was that CMOS allowed Hewlett Packard to create a practical calculator that was able to retain its memory registers when powered down. (Power was maintained to the chip, but the chip clock was stopped, and the chip could retain its state on very low power.) Before that though, the U.S. Navy used CMOS to reduce the size of circuits jammed in the nose cones of missiles so they could pack them with more explosives instead. TTL (Transistor-Transistor Logic) uses a different type of transistor (bipolar) whereas CMOS uses MOSFETs (metal oxide semiconductor field effect transistor). FETs don't have current flowing into the "gate" when static, whereas bipolars do (into the "base"), so generally this allows them to operate with lower power especially in a stand-by type of state. Before CMOS there was NMOS, which used N transistors and resistors. It's a bit complicated to explain in lay terms without a decent diagram, but CMOS stands for "Complimentary MOS" and uses a P transistor in place of the resistor. The advantage here is no static current flow is required, only at switching. Bipolar or TTL can in fact be faster, although it's not an apples-to-apples comparison because there are different processes for each. Some hybrids have been created like "BiCMOS," where both are combined on one chip. This is probably a lot more than you wanted to know. In short, CMOS is many things, but with the huge amounts of money invested in CMOS today it obviously has all the advantages necessary to be the default technology for most integrated electronics.
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Other contributors say:

CMOS logic has advantage of having smaller dimensions with new coming (usually smaller) technologies. Thus, the RC constant (RC defines transition time, where R = resistance is coming

from R-ON resistance and C = capacitance is coming from gate capacitance) is smaller. Smaller RC constant means shorter transition (0->1 or 1->0)time. Logic is faster and can do more in same time (provided faster system clock). Same functionality is having smaller silicon area and this also means lower price for same functionality. Therefore the CMOS is very popular today and widely used. Concerning the ESD, yes CMOS is more sensitive, because breakdown of MOS gate is always destructive while impact of junction breakdown still depends on ESD pulse energy. Nevertheless, low-voltage CMOS is relatively easy to protect and our company has standard of 4kV ESD HBM (human body model) susceptibility as minimum. I do not remember problems after hand manipulation in the lab.

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