DHANALAKSHMI COLLEGE OF ENGINEERING

MANIMANGALAM- CHENNAI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY
FOR IV SEMESTER B.E (EEE)

NAME REG.NO

: :

131452-LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

1. Study of Basic Digital ICs.(Verification of truth table for AND, OR, EXOR, NOT, NOR,NAND, JK FF, RS FF, D FF) 2. 3. (a) Implementation of Boolean Functions (b) Design and Implement Adder/ Subtractor circuits (a) Design and Implementation of Combinational circuits for Code conversion, Parity generator and parity checker. (b) Design and implement Encoders and Decoders using suitable ICs.

4. Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8 demultiplexer. 5. Design and Implementation of Synchronous and Asynchronous Counters. 6. Design and implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO Modes using suitable ICs. 7. Timer IC applications: Study of NE/SE 555 timer in Astable, Monostable operation. 8. Application of Op-Amp: Slew rate verifications, inverting and non-inverting amplifier, Adder, comparator, Integrator and Differentiator. 9. Study of Analog to Digital Converter and Digital to Analog Converter: Verification of A/D conversion using dedicated ICs. 10. Study of VCO and PLL ICs (a) Voltage to frequency characteristics of NE/ SE 566 IC. (b) Frequency multiplication using NE/SE 565 PLL IC.

The Breadboard
The breadboard consists of two terminal strips and two bus strips (often broken in the centre). Each bus strip has two rows of contacts. Each of the two rows of contacts is a node. That is, each contact along a row on a bus strip is connected together (inside the breadboard). Bus strips are used primarily for power supply connections, but are also used for any node requiring a large number of connections. Each terminal strip has 60 rows and 5 columns of contacts on each side of the centre gap. Each row of 5 contacts is a node. You will build your circuits on the terminal strips by inserting the leads of circuit components into the contact receptacles and making connections with 22-26 gauge wire. There are wire cutter/strippers and a spool of wire in the lab. It is a good practice to wire +5V and 0V power supply connections to separate bus strips.

Fig 1. The breadboard. The lines indicate connected holes.

The 5V supply MUST NOT BE EXCEEDED since this will damage the ICs (Integrated circuits) used during the experiments. Incorrect connection of power to the ICs could result in them exploding or becoming very hot - with the possible serious injury occurring to the people working on the experiment!

Ensure that the power supply polarity and all components and connections are correct before switching on power.

Building the Circuit

Throughout these experiments we will use TTL chips to build circuits. The steps for wiring a circuit should be completed in the order described below: 1. Turn the power (Trainer Kit) off before you build anything! 2. Make sure the power is off before you build anything! 3. Connect the +5V and ground (GND) leads of the power supply to the power and ground bus strips on your breadboard. 4. Plug the chips you will be using into the breadboard. Point all the chips in the same direction with pin 1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch next to it on the chip package) 5. Connect +5V and GND pins of each chip to the power and ground bus strips on the breadboard. 6. Select a connection on your schematic and place a piece of hook-up wire between corresponding pins of the chips on your breadboard. It is better to make the short connections before the longer ones. Mark each connection on your schematic as you go, so as not to try to make the same connection again at a later stage. 7. Get one of your group members to check the connections, before you turn the power on. 8. If an error is made and is not spotted before you turn the power on. Turn the power off immediately before you begin to rewire the circuit. 9. At the end of the laboratory session, collect you hook-up wires, chips and all equipment and return them to the demonstrator. 10.Tidy the area that you were working in and leave it in the same condition as it was before you started.

Common Causes of Problems 1. Not connecting the ground and/or power pins for all chips. 2. Not turning on the power supply before checking the operation of the circuit. 3. Leaving out wires. 4. Plugging wires into the wrong holes. 5. Driving a single gate input with the outputs of two or more gates 6. Modifying the circuit with the power on.

In all experiments, you will be expected to obtain all instruments, leads, components at the start of the experiment and return them to their proper place after you have finished the experiment. Please inform the demonstrator or technician if you locate faulty equipment. If you damage a chip, inform a demonstrator, don't put it back in the box of chips for somebody else to use. Example Implementation of a Logic Circuit Build a circuit to implement the Boolean function F =A.B.

Fig 2. The complete designed and connected circuit Sometimes the chip manufacturer may denote the first pin by a small indented circle above the first pin of the chip. Place your chips in the same direction, to save confusion at a later stage. Remember that you must connect power to the chips to get them to work.

INDEX
S.No

Date

Name of the Experiment Study of Basic Digital ICs.(Verification of truth table for AND, OR, EXOR, NOT, NOR,NAND, JK FF, RS FF, D FF) (a) Implementation of Boolean Functions (b) Design and Implement Adder/ Subtractor circuits (a) Design and Implementation of Combinational circuits for Code conversion, Parity generator and parity Checker. (b) Design and implement Encoders and Decoders using suitable ICs. Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8 demultiplexer. Design and Implementation of Synchronous and Asynchronous Counters. Design and implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO Modes using suitable ICs Timer IC applications: Study of NE/SE 555 timer in Astable, Monostable operation. Application of Op-Amp: Slew rate verifications, inverting and non-inverting amplifier, Adder, comparator, Integrator and Differentiator. Study of Analog to Digital Converter and Digital to Analog Converter: Verification of A/D conversion using dedicated ICs. Study of VCO and PLL ICs (a) Voltage to frequency characteristics of NE/ SE 566 IC. (b) Frequency multiplication using NE/SE 565 PLL IC.

Pg.no

Marks out of 10

Signature of staff

4 5

10

COMPLETED / INCOMPLETE / LATE SUBMISSION

AVERAGE MARKS:

AND GATE SYMBOL TRUTH TABLE

OR GATE SYMBOL TRUTH TABLE

NOR GATE SYMBOL TRUTH TABLE

Experiment No:

Date: __/__/____

STUDY OF LOGIC GATES & FLIP FLOPS

AIM: To realize logic functions using gates & verify the operation of flip-flops. Apparatus Required: S.No 1 2 3 Apparatus IC 7404, IC 7432, IC7408 IC 7402, IC7400, IC 7486 Digital trainer Board Connecting wires Specifications Quantity

THEORY: A. Gates: 1. NOT Gate It is called so because its output is not the same as its input. It is also called an Inverter, because it inverts the input signal. It has one input & one output. If A is an input, then Y= A is its output. 2. OR Gate The OR gate has an output of 1 when either A or B or Both are 1.In other words, it is an anyor-all gate because an output occurs when any or all inputs are present. The OR gate truth table, may be defined as a table, which give the output state for all possible input combinations. If A and B are inputs, then the output is Y = A+B. 3. NOR Gate This is NOT-OR gate. It can be made out of an OR gate by connecting an inverter in its output. A NOR gate will have an output of 1 only when all its inputs are 0. If any one of the input is 1, then output is 0. In a NOR gate, the output is true only all inputs are false. If A & B are inputs, then output Y = (A+B) 4. AND Gate The AND gate gives an output only when all its inputs are present. The AND gate has output 1 if both A & B are 1. Hence this is an all-or-nothing gate whose output occurs only all its inputs are present. The output Y= A . B. 5. NAND Gate This is NOT-AND gate. It can be made out of an AND gate by connecting an inverter in its output. A NAND gate will have an output of 1 when all its inputs are 0. If any one of the input is 1, then output is 1. In a NAND gate, the output is true only all inputs are false. If A & B are inputs, then output Y = (A.B)

NOT GATE SYMBOL TRUTH TABLE

X-OR GATE SYMBOL TRUTH TABLE

2-INPUT NAND GATE SYMBOL TRUTH TABLE

6. EX-OR Gate In this gate, output is one if its input but not both is 1.In other words, it has an output 1 if its inputs are different. The output is 0, if its input is same. It is also called Inequality Comparator. The output Y= A B + A B 7. Universal Gates The Universal gates are NAND and NOR gates because the logic gates like NOT, OR and AND can be realized using these gates. B. Flip-flops: Flip Flops is a bi-stable multivibrator circuit that has two stable states. The FF can be used as memory device since it can maintain a binary state indefinitely (as long as power is delivered to the circuit) until directly by an input signal to switch states. It forms the heart of all sequential digital circuits. The FF is often called a latch, since it will hold, or latch in either stable state. The FF has two outputs; one for the normal valve and another one for the complement value of the bit stored in it. Binary information can enter a flip-flop in a variety of ways, a fact which gives rise to different types of Flip-Flops. The different types of Flip Flops are RS FF, Clocked RS FF, D FF, JK FF and T FF. The major differences among various types of FFs are in the number of input they possess and in the manner in which the inputs affect the binary state. The important applications of FFs are Storage register Shift register Frequency divider Counters 1. Clocked RS Flip-Flop: The operation of the basic FF can be modified by providing an additional control input that determines when the state of the circuit is to be changed. The clocked RS flip-flop shown in fig consists of a basic flip-flop circuit and two additional NAND gates. The clock pulse input acts as an enable signal for the other two inputs. The outputs of NAND gates 3 and 4 stay at the logic 1 level as long as the clock input (abbreviated CP) remains at 0.This is the quiescent condition for the basic FF. When the clock pulse input goes to 1, information from the S or R inputs is allowed to reach the output. The set state is reached with S=1, R=0, and CP=1. This causes the output of gate 3 to go to 0,the output of gate 4 to remain at 1,and the output of the FF at Q to go to1. To change to the reset state, the inputs must be S=0, R=1, and CP=1.In either case, when CP returns to 0, the circuit remains in its previous state When CP=1 and both the inputs S and R are equal to 0, the state of the circuit does not change. An indeterminate condition occurs when CP=1 and both the inputs S=1, R=1. This condition places 0s in the outputs of gates 3 and 4 and 1s in both outputs Q and Q. When the clock pulse goes back to 0 (while S=R=1), it is not possible to determine the next state, as it depends on whether the output of gate 3 or gate 4 goes to 1 first. This indeterminate condition makes this circuit difficult to manage and it is seldom used in practice. Nevertheless, it is important circuit because all other flip-flops are constructed from it.

LOGIC CIRCUIT

SR - Flip Flop

D- Flip Flop

JK- Flip Flop

T- Flip Flop

3. Delay Flip Flop The RS FF has two data inputs and therefore, generation of two signals to drive a FF is a disadvantage in many applications. One way to eliminate the undesirable condition of the indeterminate state in the clocked RS FF is to ensure that inputs S and R are never equal to 1at the same time. This has lead to the D FF, a circuit that needs only single data input. The D input goes directly to the S input, and its complement, through gate 5, is applied to the R input. As long as the clock pulse input is at 0, the output of gates 3 and 4 are at the 1 level and the circuit cannot change state regardless of the value of D. This conforms to the requirement that the two inputs of a basic NAND flip flop remain initially at the 1 level. The D input is sampled during the occurrence of a clock pulse. If D is 1, the output f gate 3 goes to 0, switching the flip-flop to the set state. If D is 0, the output of gate 4 goes to 0, switching the flip-flop to the clear state. The D FF receives the designation from its ability to hold data into its internal storage. When the clock input goes high, input data is loaded into the FF and appears at the output. Then when the clock pulse goes low, the output retains the data. The characteristic equation shows that the next state of the flip-flop is the same as the D input and is independent of the value of the present state. 4. J-K Flip Flop A JK flip flop is a refinement of the RS flip flop in that the indeterminate state of the RS type is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flipflop respectively. When both inputs J=K=1 simultaneously the flip-flop switches to its complement state, that is if Q=1, it switches to Q =0 and vice versa. A clocked JK flip-flop is shown in fig -5. Output Q is AND-ed with K and CP inputs so that the flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, output Q is AND-ed with J and CP inputs so that the flip-flop is set with a clock pulse only if Q was previously 1. When both J and K are 1, the clock pulse is transmitted through one AND gate only. The one whose input is connected to the flip-flop output which is presently equal to 1. Thus if Q=1, the output of the upper AND gate becomes 1 upon application of a clock pulse, and the flip-flop is cleared. If Q=1, the output of the lower AND gate becomes a 1 and the flip-flop is set. In either case, the output state of the flip-flop is complemented. It is very important to realize that because of the feedback connection in the JK FF, a clock pulse that remains in the 1 state while both J=K=1 will cause the output to complement again and repeat complementing until the clock pulse goes back to 0.this is called Race-around condition in the FF. To avoid this indeterminate condition, clock pulse must have time duration that is shorter than the propagation delay time of FF. This is a restrictive requirement, since the operation of the circuit depends on the width of the pulses. For this reason, JK flip-flop are never constructed. The restriction on the pulse width can be eliminated with a mater- slave or edgetriggered flip flop. The same reasoning applies to the T flip-flop.

Truth table
SR Flip Flop S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Qn 0 1 0 1 0 1 0 1 Qn+1 1 1 0 0 1 1 X X

D Flip Flop D Qn 0 0 0 1 1 0 1 1 JK Flip Flop J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Qn 0 1 0 1 0 1 0 1 Qn+1 1 1 0 0 1 1 1 0 Qn+1 0 0 1 1

T Flip Flop T Qn 0 0 0 1 1 0 1 1 Qn+1 0 1 1 0

5. Toggle Flip Flop The Toggle flip-flop is a single input version of the JK flip-flop. The T flip flop is obtained from a JK type if both inputs are tied together. The designation T comes from the ability of the flip-flop to toggle or complement its state. Regardless of the present state of the flipflop complements its output when the clock pulse occurs while input T is logic-1. The characteristic equation shows that when T=0, Q (T+1)=Q, that is next state is same as the present sate and no change occurs. When T=1, Q (T+1)=Q that is the state of FF is complemented.

PROCEDURE: 1. In a digital IC trainer board, Fix the IC s firmly and the connections are made as per the circuit diagram. 2. Apply +5 V to the 14th pin of IC s 7404, 7432, 7402, 7408, 7400 & 7486 and connect ground to the 7th pin of IC s. 3. Apply inputs to the circuit & verify the outputs with Truth table. 4. To realize a particular gate using Universal gates, Connect the IC s as shown in logic diagram and verify the truth table for that particular gate, Repeat the same for other gates.

DISCUSSION QUESTIONS: 1. What is Integrated Circuit? 2. What is a Logic gate? 3. What are the basic digital logic gates? 4. What are the gates called universal gates? 5. Why NAND and NOR gates are called universal gates? 6. What are the properties of EX-NOR gate?

Result:

. Signature of the staff in charge

Boolean function implementation K-Map (i) (ii)

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F1=

F2= Circuit Diagram

Experiment No:

Date: __/__/____

IMPLEMENTATION OF BOOLEAN FUNCTIONS, ADDER/ SUBTRACTOR CIRCUITS. AIM: To design and verify the truth table of the Adder and Subtractor circuits.

Pre-Laboratory : There are two tasks that you must perform prior to sitting this laboratory:
1. Understand the design problem given to you. 2. Draw up the truth tables and logic diagram for the design .

Apparatus Required:
S.No Components Specifications Quantity

Truth Table

(a) Half Adder

(b) Half Subtractor

(c) Full Adder

(d) Full Subtractor

THEORY: The most basic arithmetic operation is the addition of two binary digits. There are four possible elementary operations, namely, 0+0=0 0+1=1 1+0=1 1 + 1 = 0 with carry 1 The first three operations produce a sum of whose length is one digit, but when the last operation is performed the sum is two digits. The higher significant bit of this result is called a carry and lower significant bit is called the sum. Half adder: A combinational circuit which performs the addition of two bits is called half adder. The input variables designate the augend and the addend bit, whereas the output variables produce the sum and carry bits. Full adder: A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented with two half adders and one OR gate. Half subtractor: A combinational circuit which performs the subtraction of two bits is called half subtractor. The input variables designate the minuend and the subtrahend bit, whereas the output variables produce the difference and borrow bits. Full subtractor: A combinational circuit which performs the subtraction of three input bits is called full subtractor. The three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be implemented with two half subtractors and one OR gate.

K-map Simplification Full Adder

0 1 3 2

Sum=

Carry=

Full Subtractor
0 1 3 2

Difference=

Borrow=

PROCEDURE: 1. The connections are given as per the circuit diagram. 2. Two 4 bit numbers added or subtracted depend upon the control input and the output is obtained. 3. Apply the inputs and verify the truth table for the half adder or s subtractor and full adder or subtractor circuits. DISCUSSION QUESTIONS: 1. What is combinational circuit? 2. What is different between combinational and sequential circuit? 3. What are the gates involved for binary adder? 4. List the properties of Ex-Nor gate? 5. What is expression for sum and carry?

CIRCUIT DIAGRAM

Full Adder

Full Subtractor

Result:

.. Signature of the staff in charge

Truth Table (a) Code converter (i) Binary to Gray (ii) Gray to Binary

B3 B2 B1 B0 G3 G2 G1 G0

G3 G2 G1 G0 B3 B2 B1 B0

Experiment No:

Date: __/__/____

Design and Implementation of Combinational circuits for Code Conversion, Parity generator and parity checker.

Aim: To Design and Implement the combinational code converters, Parity generator and Parity checker.

Pre-Laboratory :There are two tasks that you must perform prior to sitting this laboratory:
1. Understand the design problem given to you. 2. Draw up the truth tables and logic diagram for the design .

Apparatus Required:
S.No Components Specifications Quantity

K-Map Simplification (a)Binary to Gray

0 1 3 2 0 1 3 2

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G0=

G1=

G2=
0 1 3 2

G3=
0 1 3 2

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THEORY: Binary to gray: The MSB of the binary code alone remains unchanged in the Gray code. The remaining bits in the gray are obtained by EX-OR ing the corresponding gray code bit and previous bit in the binary code. The gray code is often used in digital systems because it has the advantage that only one bit in the numerical representation changes between successive numbers. Gray to binary: The MSB of the Gray code remains unchanged in the binary code the remaining bits are obtained by EX OR ing the corresponding gray code bit and the previous output binary bit.

K-Map Simplification (b) Gray to Binary

0 1 3 2 0 1 3 2

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B3=

B2=

B1=
0 1 3 2

B0=
0 1 3 2

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DISCUSSION QUESTIONS ON CODE CONVERSION: 1. List the procedures to convert gray code into binary? 2. Why weighted code is called as reflective codes? 3. What is a sequential code? 4. What is error deducting code? 5. What is ASCII code? 6. What is the need for code conversion?

CIRCUIT DIAGRAM (a) Code Converter

Truth Table (b) Parity generator for 3-bit message

Parity Generator and Parity Checker

A parity bit is used for the purpose of detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number of 1s either odd or even. The message including the parity bit is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker. In even parity the added parity bit will make the total number of 1s an even amount and in odd parity the added parity bit will make the total number of 1s an odd amount. In a three bit odd parity generator the three bits in the message together with the parity bit are transmitted to their destination, where they are applied to the parity checker circuit. The parity checker circuit checks for possible errors in the transmission. Since the information was transmitted with odd parity the four bits received must have an odd number of 1s. An error occurs during the transmission if the four bits received have an even number of 1s, indicating that one bit has changed during transmission. The output of the parity checker is denoted by PEC (parity error check) and it will be equal to 1 if an error occurs, i.e., if the four bits received has an even number of 1s.

Truth Table (c) Parity Checker for 3-bit message

K-Map simplification
(c) Even Parity generator
0 1 3 2

(d) Odd Parity generator

0 1 3 2

PE = PO =

DISCUSSION QUESTIONS ON PARITY BIT: 1. What is parity bit? 2. Why parity bit is added to message? 3. What is parity checker? 4. What is odd parity and even parity? 5. What are the gates involved for parity generator?

K-Map simplification
(e) Even Parity Checker
0 1 3 2

(f) Odd Parity Checker

0 1 3 2

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E =

O =

CIRCUIT DIAGRAM (c) Even Parity generator (d) Odd Parity generator

(c) Even Parity Checker

(d) Odd Parity Checker

Result: -

.. Signature of the staff in charge

Truth Table

(a) Decoder

Experiment No:

Date: __/__/____

Design and implementation of Encoders and Decoders

AIM: To design and implement encoder using IC 74148 (8-3 encoder)

Pre-Laboratory: There are two tasks that you must perform prior to sitting this laboratory:
1. Understand the design problem given to you. 2. Draw up the truth tables and logic diagram for the design.

Apparatus Required:
S.No Components Specifications Quantity

Truth Table (b) Encoder

THEORY: Encoder: An encoder is digital circuit that has 2n input lines and n output lines. The output lines generate a binary code corresponding to the input values 8 3 encoder circuit has 8 inputs, one for each of the octal digits and three outputs that generate the corresponding binary number. Enable inputs E1 should be connected to ground and Eo should be connected to VCC

Decoder: A decoder is a combinational circuit that converts binary information from n input lines to 2n unique output lines. In 3-8 line decoder the three inputs are decoded into right outputs in which each output representing one of the minterm of 3 input variables. IC 74155 can be connected as a dual 2*4 decoder or a single 3*8 decoder desired input in C1 and C2 must be connected together and used as the C input. G1 and G2 should be connected and used as the G (enable) input. G is the enable input and must be equal to 0 for proper operation.

Circuit/diagram (or) Pin configuration

Decoder

Encoder

PROCEDURE: 1. Connections are given as per the logic diagram. 2. The truth table is verified by varying the inputs.

DISCUSSION QUESTIONS: 1. How the output line will be activated in decoder circuit? 2. What are the necessary steps for implementing higher order decoders? 3. What is the use of code converters? 4. How to convert BCD to Decimal decoder? 5. What is seven segment displays? 6. What is the other name of encoder? 7. What is encoding? 8. What are the applications of encoder? 9. What is BCD encoder?

RESULT:

.. Signature of the staff in charge

Truth Table (a) 4:1 Multiplexer

K-Map

Experiment No:

Date: __/__/____

Study of Multiplexer and Demultiplexer

AIM:

Pre-Laboratory: There are two tasks that you must perform prior to sitting this laboratory:
1. Understand the design problem given to you. 2. Draw up the truth tables and logic diagram for the design.

Apparatus Required:
S.No Components Specifications Quantity

Truth Table (a) 1:4 Demultiplexer

K-Map

THEORY: Multiplexer is a digital switch which allows digital information from several sources to be routed onto a single output line. The basic multiplexer has several data input lines and a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2n input lines and n selector lines whose bit combinations determine which input is selected. Therefore, multiplexer is many into one and it provides the digital equivalent of an analog selector switch. DESIGN: 4 X 1 MULTIPLEXER LOGIC SYMBOL

Circuit Diagram (a) 4:1 Mux

(b) 1:4 Demux

A Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines. The selection of specific output line is controlled by the values of n selection lines. 1X4 DEMULTIPLEXER LOGIC SYMBOL

Study of Mux and Demux using MSI devices:

(a) Mux (4-1)

(b) De-Mux (1-4)

( c ) 8:1 Mux (IC 74XX151)

(d) Demux 1:8 (IC 74X138)

PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. 3. Apply the inputs and verify the truth table for the multiplexer & demultiplexer. DISCUSSION QUESTIONS: 1. What is the other name of de-multiplexer? 2. Compare MUX and DE-MUX? 3. How many select lines needed for four outputs of DE-MUX? 4. What is other name of multiplexer? 5. What is serial to parallel converter? 6. What is the use of select lines? 7. How to enable the multiplexer? 8. What are the applications of multiplexer?

Result: -

.. Signature of the staff in charge

(a) Pin Configuration of IC7476 ( Dual JK Flip flop)

State table diagram for Mod-9 Synchronous Up counter:

State table for Mod-9 Synchronous counter:

Experiment No:

Date: __/__/____

Design and Implementation of Synchronous and Asynchronous Counters.

AIM: To design a mod-5 Synchronous Counter and 3-bit Asynchronous binary Counter using JK Flip-Flop and Verify their function with the truth table.

Apparatus Required: S.No Components Specifications Quantity

THEORY: A counter is one of the most useful and versatile subsystems in a digital system. A equential circuit that goes through a prescribed sequence of states upon the application of input pulses is called a counter. The input pulses, called count pulses may be clock pulses, or they may originate from an external source and may occur at prescribed intervals of time or

at random. In a counter, the sequence of states may follow a binary count or any other sequence of states. Counter has a natural count of 2n where n is the number of flip-flop in the counter. Modulus of a counter is the total number of states through which the counter can progress. For example mod-8 counter has 8 states. Counter of any modulus can be constructed by incorporating logic, which causes certain states to be skipped over, or omitted. One technique for skipping counts is to steer clock pulses to certain FFs at the proper timethis is called steering logic. A second technique is to precondition the logic inputs to each FF in order to omit certain states. This is called look-ahead logic. Logic can be included such that the counter can operate in either a count-up or count-down mode. Furthermore, logic gates can be designed to uniquely decode each state of a counter. There are basically two different types of counters. Synchronous or parallel counter Asynchronous or serial counter An asynchronous or ripple counter in which each flip-flop is triggered by the output of the previous flip-flop and all the FFs do not change states in exact synchronism with the applied clock pulses. The first flip flop must change state before it can trigger the second FF, and the second FF has to change state before it can trigger the third FF and so on. The triggers move

K-Map Simplification for Mod-9 Synchronous Up counters

Logic circuit for Mod-9 Synchronous Up counter

through the flip-flop like a ripple in water. Because of this, the overall propagation delay time is sum of all the individual delays i.e. the total settling time is approximately equal to n delay time of single FF, where n is the total number of FF. Therefore the speed of operation is limited. A synchronous counter in which all flip-flops change states simultaneously since all clock inputs are driven by the same clock and the settling time is equal to the delay time of a single flip-flop. Therefore the speed of operation can be increased. The basic function of a counter is to memorize how many clock pulses have been applied to the input; hence in the most basic sense counters are memory systems. The important applications are (i) counting pulse, (ii) frequency division (iii)time measurement (iv) control and timing operations. Working of Three Bit Asynchronous Binary Counter 1. Up Counter: Up counter is one, which will count upward from zero to a maximum count. A binary 3-bit ripple counter can be constructed by using the clocked JK flip-flop. Lets assume that all FF are in the logic 0 states. 1. A clock pulse is applied only to the clock input of FF-A. Thus FF-A will toggle (change to its opposite state) each time the clock pulse make a negative (HIGH to LOW) transition. Note that J= K=1 for all the FFs. 2. The normal output of FF-A acts as the clock input for FF-B, and so FF-B will toggle each time the FF-A output goes from 1 to 0. Similarly, FF-C will toggle when FF-B goes from 1to 0. 3. FF outputs C, B and A represent a 3-bit binary number with C as the most significant bit (MSB). The waveforms in fig 1 show that a binary counting sequence from 000 to 111 is followed as clock pulses are continuously applied. 4. After the NGT (negative going transition) of the seventh clock pulse has occurred the counter FFs are in the 111 condition. 5. On the eighth NGT, the FF-A goes from 1 to 0 which causes FF-B to go from 1 to 0, and so on, until the counter is in the 000 state. In other words, the counter has gone through one complete cycle (000 through 111) and has recycled back 000, from where it will begin new a counting cycle as subsequent clock pulses are applied. 2. Down Counter: Down counter is one, which will count downward from a maximum count to zero. Let as examine the countdown sequence for a 3-bit binary down counter. 1. A, B and C represent the FF output states as the counter goes through its sequence. It can be seen that FF-A (LSB) changes states (toggles) at each step in the sequence just as it does in up counter. The FF-B changes states each time B goes from LOW to HIGH; C changes states each time B goes from LOW to HIGH. Thus, in a down counters each FF, except first, must toggle when the preceding FF goes from LOW to HIGH. 2. If the FFs have clock inputs that respond to negative transitions (HIGH to LOW), then an inverter can be placed in front of each FF clock input; however the same effect can be accomplished by driving each FF clock input from inverted output of preceding FF. this is illustrated in fig 2 for a Mod 8 down counter. 3. The input pulses are applied to the FF-A .The output serves as the clock input for FF-B, the B output serves as clock for FF-C. The waveforms at A, B and C show that B toggles whenever A goes LOW to HIGH (so that goes HIGH to LOW) and C toggles whenever B goes LOW to HIGH. This results in the desired down counting sequence at the C, B, and A outputs.

(b) Circuit Diagram for 3-bit Asynchronous Up Counter

Truth Table for 3-bit asynchronous up counter and Timing Waveforms

Applications: Down counters are not as widely used as up counters. Their major application is in situations where it must be known when a desired number of input pulses have occurred. In these situations the down counter is preset to desired number and then allowed to count down as the pulses are applied. When the counter reaches the zero state, a logic gate whose output then indicates that the preset number of pulses has occurred detects it. Design Of Mod-5 Synchronous Counter Basic idea: In synchronous counters the FFs entire are clocked at the same time. Before each clock pulse, the input of each FF in the counter must be at the correct level to ensure that the FF goes to the correct state. Therefore, the process of designing a synchronous counter then becomes one of designing the logic circuits that decode the various states of the counter to supply the logic levels to each FF input. The inputs to these decoder circuits will come from the outputs of one or more of the FFs. Design Procedure: In order to design a MOD-5 counter the number of flip-flops required is three.This is found from the equation 2n N, where N=5, the number states present in MOD-5 counter. Let us assume that the MOD-5 counter has five states 000, 001, 010, 011 and 100.The counter is to designed by treating the unused states 101,110 and 111 as dont care condition. Step 1: State transition diagram The state diagram for Mod-5 counter can be drawn as shown in figure below here it is assumed that the state transition from one state to another takes place when the clock pulse is asserted; when the clock is unasserted, the counter remains in present state.

Step 2: State transition table Use the state transition diagram to setup a table that lists all present states and their next states. The undesired states 101, 110, and 111 are considered as dont care condition.

(c) Circuit Diagram for 3-bit Asynchronous Down Counter

Step 3: J-K flip-flop excitation table

Step 4: Circuit excitation table Our design uses 3 FFs, C, B and A of each one has J and k input. Therefore, we must add three new columns as shown in the table. This complete table is called circuit excitation table. The entries under each J and K are obtained from state transition table and JK FF excitation table.

Step 4: Excitation Maps Design the logic circuits to generate the levels required at each J and K input using Karnaughs map. The circuit excitation table, lists six J and K inputs, JC, KC, JB, KB and JA, KA .We must consider each of these as an output from its own logic circuit with inputs from flip-flops C, B and A. Then we must design circuit for each one. Step 5: Implement the final expressions The logic circuits for each J and K inputs are implemented from the expressions obtained from the K-Mapping.

PROCEDURE: 1. Connections are given as per the circuit diagrams. 2. Apply the input and verify the truth table of the counter.

DISCUSSION QUESTIONS: 1. Compare synchronous and asynchronous sequential circuits? 2. What is ripple counter? 3. What is propagation delay in ripple counter? 4. Define MOD counter? 5. What are the applications of counters? 6. State the types of counter? 7. Define bit, byte and word. 8. Define address of a memory.

Result: -

.. Signature of the staff in charge

Pin configuration of IC 7474

Data input = 1100 1. SISO circuit diagram

Experiment No:

Date: __/__/____

Design and implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO Modes using suitable ICs.

Aim: To study shift register using IC 7474 in all its modes

SIPO/SISO, PISO/PIPO.

Apparatus Required:
S.No Components Specifications Quantity

2. SIPO logic circuit

THEORY:

A register is a group of flip-flops that can be used to store a binary number. There must be one flip-flop for each bit in the binary number. An n bit register has a group of n FFs and is capable of storing any binary information containing n bits. A group of flip-flops connected in such way that a binary number can be shifted into or out of the flip-flops is called shift register. There are two ways to shift data into a resister (i.e. serial or parallel) and similarly two ways to shift the data out of the register.Serial shifting involves shifting data 1 bit at a time in a serial fashion beginning with either the MSB or LSB. Parallel shifting involves shifting all the data bit simultaneously with single clock transition. Hence, the parallel shifting method is much faster than the serial shifting method. They are classified into following four types based on how binary information is entered or shifted out. a) Serial-in Serial-out Shift Register (SISO) b) Serial-in Parallel-out Shift Register (SIPO) c) Parallel-in Serial-out Shift Register (PISO) d) Parallel-in Parallel-out Shift Register (PIPO) D flip flop is used for constructing shift register. Applications 1. A register might be used to accept input data from an alphanumeric keyboard and then present this data at the input of a microprocessor chip. They are often used to momentarily store binary data at the output of a decoder. 2. It can be connected to form a number of different types of counter. 3. The shift forms a very important link between main digital system and the input output channels. For example, a register could be used to accept output data from a microprocessor chip and then present this data on a CRT screen.

3. PIPO logic circuit

PROCEDURE: Give the circuit connections as per logic diagram. Give the input and the clock pulse Observe the output. Influence is made from the observation . DISCUSSION QUESTIONS: 1. What is register? 2. What are the modes of shift register? 3. How ring counter is implemented using shift registers? 4. Compare parallel and serial sub registers? 5. Define sequence generator? 6. What are the types of shift register? 7. Define shift registers.

Result: -

.. Signature of the staff in charge

Truth Table
Input Data A Input Data B C 0 1 0 0 1 1 1 Addition S4 S3 S2 S1 1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 0 0 0 0 0 1 B 1 1 0 0 0 0 0 Subtraction D4 D3 D2 D1 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 1 1 1

A4 A3 A2 A1 B4 B3 B2 B1 1 1 0 0 1 1 1 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1

Experiment No:

Date: __/__/____

DESIGN OF 4-BIT ADDER AND SUBTRACTOR

AIM: To design and implement 4-bit adder and subtractor using IC 7483. APPARATUS REQUIRED: Sl.No. 1. 2. 3. 3. 4. THEORY: 4 BIT BINARY ADDER: A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of next full adder in chain. The augends bits of A and the addend bits of B are designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The carries are connected in chain through the full adder. The input carry to the adder is C0 and it ripples through the full adder to the output carry C4. 4 BIT BINARY SUBTRACTOR: The circuit for subtracting A-B consists of an adder with inverters, placed between each data input B and the corresponding input of full adder. The input carry C0 must be equal to 1 when performing subtraction. COMPONENT IC EX-OR GATE NOT GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7483 IC 7486 IC 7404 QTY. 1 1 1 1 40

4-bit Parallel Adder

4-bit Parallel subtractor

4 BIT BINARY ADDER/SUBTRACTOR: The addition and subtraction operation can be combined into one circuit with one common binary adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it becomes subtractor. 4 BIT BCD ADDER: Consider the arithmetic addition of two decimal digits in BCD, together with an input carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than 19, the 1 in the sum being an input carry. The output of two decimal digits must be represented in BCD and should appear in the form listed in the columns. ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal digits, together with the input carry, are first added in the top 4 bit adder to produce the binary sum. PIN DIAGRAM FOR IC 7483:

4-bit Parallel Adder/subtractor

Result: -

.. Signature of the staff in charge