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San Jos State University Department of Electrical Engineering EE124, Electronic Design II Number 41329, Section 01, Fall 2011
Coordinator: Instructor: OfficeLocation: Phone: Email: OfficeHours: ClassSchedule: Classroom: Prerequisites: Prof.HamediHagh Prof.HamediHagh ENGR381 (408)9244041 hamedi@sjsu.edu Tuesdays13:30to16:00and Wednesdays10:15to12:00orbyappointment Mondays/Wednesdays9:0010:15 ENGR345 EE122,EE128andEngr100WwithgradesofCorbetter

Course Description AnalysisanddesignofAnalogintegratedcircuitsusingBipolarandCMOStransistors.Topicsin cludecurrentsources,activeloads,differentialamplifiers,frequencyresponse,frequencycompensa tion,outputstages,feedbackamplifiersandoperationalamplifiers. Course Goals and Student Learning Objectives ThiscourseteachesdesignoffundamentalbuildingblocksforAnalogintegratedcircuits.Itbegins with analysis and design of current sources and active loads using Bipolar and CMOS transistors. Design of singlestage and differentialpair amplifiers with their frequency response is introduced. Impactoffeedbackoninputandoutputresistancesaswellasvoltageandcurrentgainsisanalyzed. Designofoutputstagesandoperationalamplifiersarediscussed.Frequencycompensationandpow erbandwidthoptimizationinamplifiersarealsostudied. GE/SJSU Studies Learning Outcomes (LO), if applicable Uponsuccessfulcompletionofthiscourse,studentswillbeableto: LO1:DemonstrateanunderstandingofthefundamentalsofElectricalEngineering,includingits mathematicalandscientificprinciples,analysisanddesign. LO2:DemonstratetheabilitytoapplythepracticeofEngineeringinrealworldproblems. Course Content Learning Outcomes Uponsuccessfulcompletionofthiscourse,studentswillbeableto: LO3:Applytheknowledgeofmathematics,science,andengineeringincircuitanalysis(3.a) LO4:Analyzeanddesignintegratedamplifiercircuitstomeetdesiredneeds(3.c) LO5:Identify,formulate,andsolveengineeringproblemsinAnalogcircuitdesign(3.e) LO6:Demonstratetousethetechniques,skills,andmodernengineeringtoolsnecessaryfor engineeringpractice(3.k) ABET outcomes

ElectronicDesignII,EE124

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ThelettersinparenthesesinthecourselearningobjectivesrefertoABETcriterion3outcomessa tisfiedbythecourse.Thesearelistedbelowasareference: (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) (m) (n) (o) Anabilitytoapplyknowledgeofmathematics,science,andengineering Anabilitytodesignandconductexperiments,aswellastoanalyzeandinterpretdata Anabilitytodesignasystem,component,orprocesstomeetdesiredneeds Anabilitytofunctiononmultidisciplinaryteams Anabilitytoidentify,formulate,andsolveengineeringproblems Anunderstandingofprofessionalandethicalresponsibility Anabilitytocommunicateeffectively Thebroadeducationnecessarytounderstandtheimpactofengineeringsolutionsinaglobal andsocietalcontext Arecognitionoftheneedfor,andanabilitytoengageinlifelonglearning Aknowledgeofcontemporaryissues Anabilitytousethetechniques,skills,andmodernengineeringtoolsnecessaryfor engineeringpractice Specializationinoneormoretechnicalspecialtiesthatmeettheneedsofcompanies Knowledgeofprobabilityandstatistics,includingapplicationstoelectricalengineering Knowledgeofadvancedmathematics,includingdifferentialandintegralequations,linear algebra,complexvariables,anddiscretemathematics Basicsciences,computerscience,andengineeringsciencesnecessarytoanalyzeanddesign complexelectricalandelectronicdevices,software,andsystemscontaininghardwareand softwarecomponents

Required Textbook:

MicroelectronicCircuits,6thEdition,bySedraandSmith,OxfordUniversityPress,2010
Other Reading for Reference Only:

AnalysisandDesignofAnalogIntegratedCircuits,5thEdition,byGray,Hurst,LewisandMeyer,
Wiley,2009 Classroom Protocol Studentsareexpectedtoparticipateactivelyinclass.Studentswillturntheircellphonesofforput themonvibratemodewhileinclass.Theywillnotanswertheirphonesinclass. Dropping and Adding Studentsareresponsibleforunderstandingthepoliciesandproceduresaboutadd/drops,academic renewal,etc.Studentsshouldbeawareofthecurrentdeadlinesandpenaltiesforaddinganddropping classes. Information on add/drops are available at http://info.sjsu.edu/webdbgen/narr/socfall/rec 298.html.Informationonlatedropisathttp://www.sjsu.edu/sac/advising/latedrops/policy. Projects and Homework: Problemsolutionisessentialforstudentssuccessinthiscourseandthetextbookproblemsareall designed to better prepare students for examinations. Textbook provides answers to some chapter questions.Itishighlyrecommendedthatstudentssolveasmanyquestionsaspossibleandverifytheir answersduringofficehours. Anumberofprojectswillbeassignedtothestudentsinthelaboratorypartofthiscourse,wherea studentwilldesign,simulate,build,andtestanelectroniccircuit,writeafinalreportontheproject andgiveapresentation.FormoredetailrefertoEE124LaboratoryManual.

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 Exams and Grading Policy

Therewillbetwomidtermexamsandafinalexam.Examsareclosedbook.Studentsareallowed to bring a calculator and a page of formula. Final exam will be comprehensive. There will be no makeupexams(unlessunderaveryspecialcircumstanceandwhenbothwrittenexcuseandofficial proofsareprovided).Examsolutionswillbediscussedintheclassafterthemidtermexams. Grades MidtermExam1 MidtermExam2 Finalexam Laboratory 90%andabove 89%85% 84%82% 81%79% 78%75% 74%72% 71%69% 68%65% 64%62% 61%59% 58%55% below55% 20% 20% 35% 25% A A B+ B B C+ C C D+ D D F

Grading Percentage Breakdown

University Policy in Academic integrity Students should know that the Universitys Academic Integrity Policy is availabe at http://www.sa.sjsu.edu/download/judicial_affairs/Academic_Integrity_Policy_S072.pdf. Your own commitmenttolearning,asevidencedbyyourenrollmentatSanJoseStateUniversityandtheUni versitysintegritypolicy,requireyoutobehonestinallyouracademiccoursework.Facultymem bersarerequiredtoreportallinfractionstotheofficeofStudentConductandEthicalDevelopment. The website for Student Conduct and Ethical Development is available at http://www.sa.sjsu.edu/judicial_affairs/index.html. Instancesofacademicdishonestywillnotbetolerated.Cheatingonexamsorplagiarism(present ingtheworkofanotherasyourown,ortheuseofanotherpersonsideaswithoutgivingpropercre dit)willresultinafailinggradeandsanctionsbytheUniversity.Forthisclass,allassignmentsareto be completed by the individual student unless otherwise specified. If you would like to include in yourassignmentanymaterialyouhavesubmitted,orplantosubmitforanotherclass,pleasenotethat SJSUsAcademicPolicyF061requiresapprovalofinstructors. Campus Policy in Compliance with the American Disabilities Act Ifyouneedcourseadaptationsoraccommodationsbecauseofadisability,orifyouneedtomake specialarrangementsincasethebuildingmustbeevacuated,pleasemakeanappointmentwithmeas soon as possible, or see me during office hours. Presidential Directive 9703 requires that students withdisabilitiesrequestingaccommodationsmustregisterwiththeDRC(DisabilityResourceCenter) toestablisharecordoftheirdisability.

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T entative Course Syllabus and Schedule

Date Wed, Aug 24 Mon, Aug 29 Wed, Aug 31 Wed, Sep 7 Mon, Sep 12 Wed, Sep 14 Mon, Sep 19 Wed, Sep 21 Mon, Sep 26 Wed, Sep 28 Mon, Oct 3 Wed, Oct 5 Mon, Oct 10 Wed, Oct 12 Mon, Oct 17 Wed, Oct 19 Mon, Oct 24 Wed, Oct 26 Mon, Oct 31 Wed, Nov 2 Mon, Nov 7 Wed, Nov 9 Mon, Nov 14 Wed, Nov 16 Mon, Nov 21 Wed, Nov 23 Mon, Nov 28 Wed, Nov 30 Wed, Dec 5 Mon, Dec 7 Tue, Dec 13 Topic Review of MOSFETs and BJT Operation Integrated Circuit Design Current Mirrors CS/CE Amplifiers Cascode Amplifiers Folded Cascode Amplifiers CD/CC Amplifiers CG/CB Amplifiers Midterm Exam 1 (from the first third of lectures) Solutions to Midterm Exam 1 Differential-Pair Amplifiers Small-Signal Analysis of Differential-Pair Amplifiers CMRR of Differential-Pair Amplifiers Differential-Pair Offset Voltage Differential to Single-Ended Conversion Frequency Response of CS/CE Amplifiers Frequency Response of CG/CB Amplifiers Frequency Response of CD/CC Amplifiers Frequency Response of Differential-Pair Amplifiers Midterm Exam 2 (from the second third of lectures) Solutions to Midterm Exam 2 Modeling Basic Amplifiers Series-Shunt Feedback Analysis Series-Series Feedback Analysis Shunt-Shunt Feedback Analysis Shunt-Series Feedback Analysis Loop Gain, Stability and Phase Margin Class A Operation Class B Operation Class AB Operation Final Exam (Comprehensive) Reading 46 7.1 7.47.5 7.2 7.3 7.3.6 7.6.1 7.6.3 75 minutes 8.1, 8.3, 8.5 8.2 8.2.5 8.4 8.5 9.19.5 9.6 9.7 9.89.10 75 minutes 10.3 10.4 10.5 10.6 10.7 10.910.12 11.2 11.3 11.411.6 7:159:30

Holidays: ThursdayNov24

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EE124_Lecture1 (5/9)

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San Jose State University Department of Electrical Engineering S. Hamedi-Hagh Fall 2011

This handout includes a summary of transistors and some suggested homework from the textbook. The summary of the MOSFET and Bipolar devices, output I-V curves, schematic symbols, current and voltage notations, current equations, small-signal models and small-signal parameters are all briefly reviewed in the following pages to aid students with solving the homework problem sets. Please study the Appendix 7.A, Table 7.A.3 and Table 9.1 of the textbook very carefully as they contain important information regarding transistors. The suggested problem sets from the textbook are listed in the last page of this handout. Students are urged to practice as much textbook questions as possible. Please remember that these homework questions may or may not resemble the actual exam. Current mirrors and main amplifying transistors can be genrally designed using either MOSFET or Bipolar devices. MOSFET devices can be designed using either NMOS or PMOS devices and the Bipolar devices can be designed using either NPN or PNP devices. Each amplifier can also be designed using both MOSFET and Bipolar devices to form a hybrid architecture. Hence, it is possible to create a wide variety of amplifiers using basic architectures presented in this course.

S. Hamedi-Hagh, 2011

EE124_Lecture1 (6/9)

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Electronic Circuit Design II Suggested Homework Questions

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nmos transistor: IDS

Triode Region VGS>Vth VDS<Veff Active Region VGS>Vth VDS>Veff Breakdown Region

pmos transistor: ISD

Triode Region VSG>|Vth| VSD<Veff

Cgs

V eff V GS V th g m = C ox 1 r ds = ----------I DS S. Hamedi-Hagh, 2011 page 2 of 4 W ---- V eff = L 2C ox ( W L )I DS 2I DS = ---------V eff

EE124_Lecture1 (7/9)

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IDS gate
VGS

drain bulk
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W I DS = n C ox ---L W I DS n C ox ---- eff V DS -V L

source

Cutoff Region VGS<Vth

p C ox W I SD = -------------- ---- eff - -V 2 2 L

p C ox W I SD = -------------- ---- eff [ 1 + ( V SD V eff ) ] - -V 2 2 L 2 V SD W I SD = p C ox ---- V eff V SD ---------2 L W I SD p C ox ---- eff V SD -V L

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Cgs [F] 20f 20f

Cgd [F] 10f 10f |Vth| [V] 0.5 0.5

Csb [F] 10f 10f [1/V] 0.02 0.05

Cdb [F] 5f 5f gb [A/V] 0 0 CL [F] 500f

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npn transistor: IC Saturation

Region Active Region Breakdown Region

pnp transistor: IC Saturation

Region

IE = IC + IB IB = IC IC g m = -----VT VA r o = ------IC VT r = ------ = ----IB gm S. Hamedi-Hagh, 2011 page 3 of 4

EE124_Lecture1 (8/9)

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Suggested Problem Sets from Textbook

Order Chapter 7 7.11 7.13 7.18 7.19 7.23 7.26 7.29 7.31 7.38 7.45 7.47 7.51 7.57 Chapter 8 8.2 8.6 8.20 8.21 8.24 8.25 8.30 8.54 8.59 8.61 8.62 8.77 8.94 8.106 8.108 8.112 8.118 8.119 Chapter 9 Chapter 10 Chapter 11 9.1 9.3 9.11 9.14 9.15 9.20 9.30 9.34 9.41 9.42 9.51 9.69 9.76 9.89 9.97 9.102 9.103 9.104 9.105 10.2 10.16 10.22 10.26 10.27 10.28 10.30 10.36 10.37 10.38 10.39 10.41 10.45 10.47 10.51 10.55 10.57 10.61 10.66 10.70 10.99 11.1 11.9 11.17 11.20 11.25 11.41

S. Hamedi-Hagh, 2011

EE124_Lecture1 (9/9)

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1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21.

These suggested homework questions represent less than 20% of the problem sets in the text book.

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