EECS 270A PROJECT Design of an Operational Amplifier with a Bandgap Reference

University of California Irvine

Vipul Jain

Arastoo Shahabi

Contents
1. Introduction 2. Design Considerations 3. Design Methodology 4. Tradeoffs 5. Simulation Results 6. Areas for improvement 7. Conclusion 8. References Appendix A: HSPICE files Appendix B: Plots and waveforms

Introduction
Operational amplifiers are key elements of most analog subsystems, and the performance of many systems is strongly influenced by op amp performance. As technology scales down, the design of high-performance op amps becomes more challenging, and trade-offs between various performance parameters become more prominent. This report discusses an attempt to design an op amp in 0.18:m BiCMOS technology. A detailed description of the design methodology, the trade-offs encountered and the simulation results is presented in the following sections.

Design Considerations
Several preliminary decisions need to be taken before actually beginning to design the circuit. In particular, it is important to choose a circuit topology that is best suited for the given performance specifications. Current Reference: A current reference supplying a current with a low temperature coefficient is an essential part of an op amp. The topology options were a bandgap reference and a gm-based reference. The bandgap reference is chosen as its temperature coefficient can be well-controlled. Although the complexity of the bandgap reference leads to more power dissipation than that in a gm-based reference, it is more important to achieve a low temperature sensitivity. The output voltage of the bandgap reference was converted to a current using the following circuit.

Op Amp:
A simple two-stage CMOS op amp is used. This circuit configuration provides good common mode range, output swing, voltage gain, stability and bandwidth. Other available topologies are the ones that employ cascode configurations. As the supply voltage is limited, these topologies exhibit inferior input common mode range and output swing. Also, the noise performance is degraded due to more devices in the circuit.

EMBED Basic a two-stage op schematic of amp

The first s t a g e of t h e o p - a m p consists of a differential pair with active load. T h i s differential ga i n stage consists of transistors M1 through M4. T h e amplifi e r input stage is implemented with PMOS transistors M1 and M2. PMOS devices are used as the inputs to the differential pair because of their better noise performance over NMOS transistors; 1/f noise is reduced. Also, PMOS input transistors tend to raise unity gain frequency. The non-inverting input is the gate of M2 and the inverting input is the gate of M1. The differential stage amplifies an applied differential input. Gm of M2 multiplied by the output resistance at M2s drain is the gain of this stage.

The current mirror active load is implemented with NMOS transistors M3 and M4. These active load devices convert the input signal from a differential signal to a single-ended signal. In other words, the differential output voltage is combined by the current mirror of M3 and M4 resulting in a single output voltage. NMOS transistors are used for this current mirror because we want it to operate fast. The second stage is another gain stage implemented in a commonsource configuration with NMOS transistor M6. M6 amplifies the single-ended signal at the drain of M2. PMOS transistor M7 is the load resistance for M6; M7 is this amplifiers current source load. Gm of M6 multiplied by the output resistance at M6s drain is the gain of this stage. PMOS transistor M8 serves as the current mirror which biases the op-amp by mirroring its current to PMOS transistors M5 and M7. The W/L of M5 and M7 can be scaled with respect to the W/L of M8 in order to scale the mirrored current.

Design Methodology
Current Reference: The schematic for the bandgap is as shown:

Hand calculations for the design of our bandgap voltage reference are shown below:

For a zero TC, we require

Where x is the ratio of R2 to R1 and n is the factor by which the area of Q2 and Q3 is larger than Q1. As is the case for the op-amp, here we also spent a lot of time adjusting the bipolar transistor area factor to get the output voltage TC of zero centered at 60EC. We expected to have some level of discrepancy between our simulations and hand calculations. The reason for this is in our hand calculations we ignored parasitic capacitance.

Op Amp:
The schematic is as shown:

Now that the two-stage op-amp was chosen as our topology, we need to design the op-amp to meet the specifications accordingly and thus determine the size of each transistor used in the circuit and the bias conditions. The gain of the op-amp is inversely proportional to the square root of the current. In order to have a large gain, small bias currents must be chosen. Also in order to have a large slew rate large bias currents must be chosen. To satisfy both of these we bias the second stage with a current larger than the one biasing the first stage. We choose ID5 to be 40uA and ID7 to be 80uA. We want Id7 to be equal to Id6 for a zero differential input. We ensure this by proper transistor sizing. Channel lengths for M3, M4 and M6 were chosen to be the same to reduce process induced variations. The sizes of PMOS transistors M1 and M2 determine the differential stage gain. Choosing a smaller W/L for M3 and M4 helps reduce offset voltage. The transistors whose gm affects DC gain, M1 and M2, were designed to have minimum length size. As a result of this minimum size we reduce the capacitances that contribute to zeros and poles encountered at high frequencies. The second stage common source amplifier, M6, was designed to have a transistor length larger than minimum length. As a result the gain for the second stage is increased Hand Calculations: We present below the hand calculations used before our design of the op-amp.

For the specified output swing, we want

For some error margin we choose Our bias current is We mirror this bias current as The drain current of M5 is equal to 40uA which is Now we choose transistor sizes for M3 through M7.

To meet the input common mode range specification we choose

Using this result we can properly size M1 and M2.

Using these hand calculations we transistors according to this table:

initially

size

the

op-amp

The W/L ratios from hand calculations cant be used in the design directly because of secondary effects like channel modulations and body effect. These make the sizes of the actual devices vary. After an initial simulation we discovered our gain was around 40dB. In order to increase this gain we varied the sizes of the transistors. We varied the biasing transistors M5 and M7 by doubling both the width and length. Also we varied the differential input transistors M1 and M2 by increasing the width to the maximum allowed.

Now that we had the gain spec met, we wanted to increase our unity gain bandwidth as much as possible while still trying to meet the phase margin specification. We made the lengths of transistors M3, M4 as small as possible while maintaining the W/L ratios to increase the gain. This was also done to reduce parasitic capacitances which affect our frequency response. We next increased the width of transistors M3, M4, and M6 while maintaining W/L ratios and maintaining same length to increase gain bandwidth. We spent a lot of time adjusting the transistor

sizes to get them operating in the desired region. We tested and modified all transistor sizes to meet the specifications. Frequency Compensation: Typically, phase margins of around 60 degrees seem to ensure opamp stability. The phase margin is taken at the point of 0dB gain response. To improve the phase margin of our op-amp we try to space apart the poles. We use Miller compensation. An effect of the Miller Effect phenomenon is Cgd of M6 multiplied by the gain of the stage. By adding Cc in parallel with Cgd6 we shift down in frequency the pole from the capacitance at M6s gate away from the pole from the load capacitance. The second pole is relatively unaffected by increasing Cc. But the first pole does move down in frequency. Second pole affects are minimized as a result. Decreasing Cc makes it harder to split apart the poles therefore this wont raise the unity-gain bandwidth. A high frequency zero is added with the placement of the compensation capacitance. A reason we need compensation capacitance is because of the small gm of MOS transistors compared to BJT transistors. This easily causes RHP zeros to be created at operating frequencies which in affect worsen stability. As the input signal passes through the compensation capacitor the RHP zero easily results. Introducing a nulling resistor in series with the compensation capacitor is the answer to this problem. As a result the zero shifts. This zero has the affect of peaking the gain and degrading phase margin. The introduction of the RHP zero is a problem because negative phase shifts result in the op-amp transfer function. Further increasing of Cc becomes futile because both the first pole and zero move down in frequency; they dont separate. Making the nulling resistor relatively large moves the RHP zero to the LHP. The non-dominant pole cancels as a result. By experimentally determining the second pole frequency, we calculated the compensation capacitor and nulling resistor to be:

We experimentally adjusted the nulling resistance and compensation capacitance value to optimize our frequency response. The result is the cancellation of the non-dominant pole. We achieve the phase margin specification of 60 degrees by varying this capacitance and resistance.

Tradeoffs
One of the first tradeoffs we encountered was with choosing an op-amp topology. The two main contenders we considered were the two-stage and the folded cascade op-amp. We knew both could give us good stability, generally high gain and good bandwidth. A drawback of the folded cascade is the smaller output swing. But this can be improved by use of a wide swing cascade. But we would tradeoff increased power consumption because of the additional biasing involved. The two-stage op-amp on the other hand has good power consumption while having high output swing. The drawback of this topology, however, is that it requires compensation for stability. But compensation is a relatively painless procedure.

Therefore we chose the two-stage op-amp for these reasons and for its familiarity since it has been used in lecture a number of times. The performance of our op-amp depends on various parameters. It is highly desirable for op-amps to high gain and high bandwidth all while consuming as little power as possible. We will see below that these requirements are contradictory and tradeoff in other circuit performance aspects. Improving DC Gain: The CMOS two-stage op-amp topology provides good DC gain. However, there are many methods to increase gain. We can increase the transistor lengths while maintaining W/L to achieve higher gain. But increased lengths would tradeoff unity-gain bandwidth. Large parasitic capacitances can also result from large transistor sizes. This can degrade frequency response by lowering of zeros and poles. Larger lengths result in a severe slow down. Gain is also inversely proportional to (Vsg1-Vtp) and (Vgs6-Vtn) which themselves depend on transistor current densities. Vgs-Vt and Vsg-Vt get larger as we squeeze more current through it. Therefore small current is desired. A tradeoff of this is a slow down and increased noise. We can also increase gm while keeping the same length and same drain current. But this can worsen the matching between transistors. Another way is to reduce the drain currents while keeping the same gm. The tradeoff for this is that the slew rate degrades. And if we had chosen a cascade stage to achieve higher gain then Cascade stage then we would tradeoff voltage headroom. For a given speed, fT, there is a limit to how big we can make the gain. Improving Unity Gain Bandwidth:

Its clearly seen from our results that as the temperature rises, our gain and bandwidth both go down. However the stability rises with increased temperature. To see higher bandwidth, we need to tradeoff for lower gain. This is one of the major tradeoffs opamp design. The other major tradeoff we see is if you want great stability then you trade off for lower gain too. Reduction of the compensation capacitance, the improvement of unity gain bandwidth. Cc, also results in

Improving Phase Margin: In analog design we usually see a tradeoff between high gain and sufficient phase margin. There is a strong dependency of phase margin to the separation of the dominant pole and the pole nearest to it. The dominant pole can be moved down in frequency but this is limited by the slew rate. Generally a phase margin of 60E in feedback amplifiers is desirable. For good phase margin we tradeoff between loop stability and settling time.

Improving Slew Rate: An Increase of power dissipation will increase our bias current. This improves slew rate or correspondingly lowers the settling time. But the tradeoff for this is increased device capacitances. Therefore the larger total on-chip capacitance, the smaller the slew rate. Reduction of the compensation capacitance therefore improves slew rate. Improving Power Dissipation: We already have good power dissipation. But a trend we can see is the higher the temperature, the more power dissipated. Also the more transistors you have in your design, the more power is dissipated. Reducing currents can improve power dissipation. But this can slow down the circuit, decrease slew rate, increase the noise, and potentially decrease bandwidth.

Improving Offset Voltage: We have relatively good offset voltage. However, reducing offset can be realized by using a common-centroid geometry. The disadvantages of this are a larger chip area and larger parasitic capacitances. Improving Noise Corner Frequency: Reduction of noise always involves tradeoffs. To reduce the effects from noise we want the signal to noise ratio to be as high as possible. A way to do this is to increase the supply voltage and/or increase the current through your circuit. But this has the tradeoff of increased power consumption.

Simulation Results

Simulations were carried out using HSPICE and waveforms were plotted using Avan Waves. The plots and waveforms are shown in Appendix B and the simulation input files are listed in Appendix A. A table comparing the results is shown below: design specifications and the achieved

total on-chip resistance total on-chip capacitance BG output current(uA) output voltage Rout at 1.6V output voltage Rout at 0.2V DC Power Dissipation Phase margin(degrees) overshoot in step response Linear common-mode input swing Output Swing open-loop gain(dB) sysematic offset voltage (mV) Gain-bandwidth product Slew rate (V/us) Noise corner frequency Input-referred spot voltage

Specification < 50K < 50pF 200, < 1% variation > 50K > 50K < 5mW > 60 < 1% 0.5 to 1.3V 0.25V to 1.55V > 60 < 0.1mV > 1GHz > 25V/us < 2.5MHz < 1nV/(Hz)^(-1/2)

20C 38.15 2 200.5 (0.25%) 3930 5.11 1.736 42 0.66% 0.5V to 1.0V 0.07V to 1.73V 60.3 0.028 720MHz 357 27.2 12.9

60C 38.3 2 200 3400 5.13 1.724 61 0.01% 0.5V to 0.95V 0.08V to 1.73V 60.2 0.032 553MHz 418 47.4 12.5

100C 38.45 2 198.7 (0.65%) 3290 5.16 1.72 108.2 0.008% 05V to 0.9V 0.08V to 1.7V 60.1 0.036 272MHz 472 40.2 13.9

Areas for improvement

We are allowed a maximum DC power dissipation of 5mW. This means the total current from the 1.8V supply is a maximum of 2.78mA. Our power dissipation was well under the specifications; therefore we could have increased our current from the supply to enlarge the transistor transconductances in order to increase zeros and poles. This result in us not having as great frequency response as we could because of the lowering our zeros and poles. In summary we have room to increase our power consumption therefore we could further improve our gain and bandwidth.

Conclusion
We designed and simulated a two-stage, single-ended, CMOS op-amp in this project. We met most of the design specifications. A compromise of tradeoffs characterized our final design. As a result of this project we both have increased levels of confidence with our circuit analysis and design abilities. We have a better understanding of the tradeoffs involved in analog design. We have achieved deeper understanding of analog CMOS design principles. We have also gained practical analog design experience by use of the HSPICE tool. We feel this project culminated the course perfectly. It incorporated everything we learned from this course this quarter.

References
[1] Gray, Paul R. and Meyer, Robert G., Analysis and Design of Analog Integrated Circuits, 4 th Edition, New York : Wiley, 2001 [2] B.Razavi, Design of Analog CMOS Integrated Circuits, McGrawHill 2001

Appendix A HSPICE Input Files

Note: Please see the attached files in the folder HSPICE output files for the HSPICE output. HSPICE input for OpAmp subcircuit: File name: opamp.sp
* OPAMP SUBCIRCUIT .subckt OPAMP 1 2 3 4 5 9 M1 6 1 7 4 CMOSP W=50u L=.18u M2 8 2 7 4 CMOSP W=50u L=.18u M3 6 6 5 5 CMOSN W=6u L=0.25u M4 8 6 5 5 CMOSN W=6u L=0.25u M5 7 9 4 4 CMOSP W=21.6u L=0.36u M6 3 8 5 5 CMOSN W=27.62u L=0.275u M7 3 9 4 4 CMOSP W=43.38u L=0.36u M8 9 9 4 4 CMOSP W=50u L=0.21u Cc 10 3 1p Rz 8 10 2.75k tc1=100e-6 .ends

HSPICE input for Bandgap subcircuit: File Name: bandgap.sp

*Bandgap Subcircuit .subckt BANDGAP VDD 0 10 .inc './opamp.sp' m3 1 2 VDD VDD CMOSP l=.18u w=2.2u m4 2 2 VDD VDD CMOSP l=.18u w=2.2u m5 7 2 VDD VDD CMOSP l=.18u w=2.2u m1 1 1 3 0 CMOSN l=.18u w=11.0u m2 2 1 4 0 CMOSN l=.18u w=11.0u Q6 3 3 0 npn_270 Q7 5 5 0 npn_270 6.22 Q8 6 6 0 npn_270 6.22 R1 4 5 1k TC1=100e-6 R2 7 6 11k TC1=100e-6 X1 8 7 9 VDD 0 11 OPAMP m6 10 9 8 0 CMOSN l=.18u w=50u R3 8 0 5.0942k tc1=100e-6 m7 11 12 13 0 CMOSN l=.18u w=4.5u

m8 12 12 0 0 CMOSN l=.18u w=4.5u R4 13 0 9.75 tc1=100e-6 R5 VDD 12 5.825k tc1=100e-6 .ends

HSPICE input for transistor models: File Name: models.sp

.model npn_270 npn bf=120 vaf=150 cjc=3.5p cje=4p tf=.5n .model pnp_270 pnp bf=80 vaf=50 cjc=3.5p cje=6p tf=.8n

.MODEL CMOSN NMOS ( +VERSION = 3.1 4.1E-9 +XJ = 1E-7 0.362984 +K1 = 0.5885847 +K3B = 3.7815373 1.860566E-7 +DVT0W = 0 +DVT0 = 1.4086679 0.0486416 +U0 = 258.7497687 2.383629E-18 +UC = 5.583802E-11

TNOM NCH K2 W0 DVT1W DVT1 UA VSAT

= 27 = 2.3549E17 = 3.76408E-3 = 1E-7 = 0 = 0.3533272 = -1.46771E-9 = 9.851815E4

LEVEL TOX VTH0 K3 NLX DVT2W DVT2 UB A0

= 49 = = = 1E-3 = = 0 = = = 2

+AGS = 0.426067 4.336657E-6 +KETA = -0.0122339 0.9386604 +RDSW = 150 +WR = 1 9.489663E-9 +XL = 0 1.082575E-8 +DWB = 1.1951E-8 2.2044501 +CIT = 0 +CDSCB = 0 1.367897E-5 +DSUB = 8.985625E-3 0.2760984 +PDIBLC2 = 2.12337E-3 0.818617 +PSCBE1 = 3.85109E10 0.126606 +DELTA = 0.01 +PRT = 0 0.11 +KT1L = 0 4.31E-9 +UB1 = -7.61E-18 3.3E4 +WL = 0 +WWN = 1 +LLN = 1 +LWL = 0 +CGDO = 8E-10 12 +CJ = 9.705893E-4 0.3806281 +CJSW = 2.60616E-10 0.1441172

B0 A1 PRWG WINT XW VOFF CDSC ETA0 PCLM

= 6.237667E-9 = 4.202279E-4 = 0.5 = 0 = -1E-8 = -0.0897588 = 2.4E-4 = 2.798951E-3 = 0.8697869

B1 A2 PRWB LINT DWG

= = = -0.2 = = -

NFACTOR = CDSCD ETAB = 0 =

PDIBLC1 = DROUT PVAG MOBMOD KT1 UA1 AT WW LL LWN XPART CGBO MJ MJSW = = = 1 = = = = = = = = = = 0 0 1 0.5 1E-

PDIBLCB = -0.1 PSCBE2 RSH UTE KT2 UC1 WLN WWL LW CAPMOD CGSO PB PBSW = 2.21832E-9 = 6.9 = -1.5 = 0.022 = -5.6E-11 = = = = = 1 0 0 2 8E-10

= 0.8 = 0.8

+CJSWG = 3.3E-10 0.1441172 +CF = 0 3.3282873 +PK2 = 1.555499E-3 4.96986E-3 +PU0 = 9.3998967 +PVSAT = 1.967792E3 2.359213E-3 +KF = 8.10e-35 * .MODEL CMOSP PMOS ( +VERSION = 3.1 4.1E-9 +XJ = 1E-7 0.3865056 +K1 = 0.5599269 +K3B = 11.2797921 1.303936E-7 +DVT0W = 0 +DVT0 = 0.5232411 +U0 = 114.4429215 21 +UC = -1E-10 1.8222237 +AGS = 0.3949112 1.273176E-6 +KETA = 0.0179106 +RDSW = 251.4557825 0.2263602 +WR = 1 2.481017E-8 +XL = 0 4.825664E-8 +DWB = 2.273674E-9 1.9315957 +CIT = 0

PBSWG PVTH0 WKETA PUA PETA0 NLEV

= 0.8 = -4.673241E-5 = 3.758729E-3 = 3.011863E-12 = 1.003159E-4 = 2 )

MJSWG PRDSW LKETA PUB PKETA

= = = = 0 = -

TNOM NCH K2 W0 DVT1W DVT1 UA VSAT B0 A1 PRWG WINT XW VOFF CDSC

= 27 = 4.1589E17 = 0.0323178 = 1E-6 = 0 = 0.199934 = 1.494048E-9 = 2E5 = 4.786404E-7 = 0.4425988 = 0.5 = 0 = -1E-8 = -0.0902726 = 2.4E-4

LEVEL TOX VTH0 K3 NLX DVT2W DVT2 UB A0 B1 A2 PRWB LINT DWG

= 49 = = = 0 = = 0 = 0.1 = 1E= = = 0.3 = = = -

NFACTOR = CDSCD = 0

+CDSCB = 0 0.0263285 +DSUB = 0.694208 4.957775E-4 +PDIBLC2 = 0.0187829 9.92461E-4 +PSCBE1 = 1.759119E9 14.9999262 +DELTA = 0.01 +PRT = 0 0.11 +KT1L = 0 4.31E-9 +UB1 = -7.61E-18 3.3E4 +WL = 0 +WWN = 1 +LLN = 1 +LWL = 0 +CGDO = 6.22E-10 12 +CJ = 1.173778E-3 0.4181467 +CJSW = 1.878218E-10 0.3628729 +CJSWG = 4.22E-10 0.3628729 +CF = 0 6.8211508 +PK2 = 3.5937E-3 2.178699E-3 +PU0 = -2.2075051 21 +PVSAT = -50 2.426351E-3 +KF = 6.75e-23

ETA0 PCLM

= 0.0572231 = 2.1212768

ETAB

= -

PDIBLC1 = DROUT PVAG MOBMOD KT1 UA1 AT WW LL LWN XPART CGBO MJ MJSW MJSWG PRDSW LKETA PUB PKETA = = = 1 = = = = = = = = = = = = = = 1E= 0 0 1 0.5 1E-

PDIBLCB = -8.156661E-4 PSCBE2 RSH UTE KT2 UC1 WLN WWL LW CAPMOD CGSO PB PBSW PBSWG PVTH0 WKETA PUA PETA0 NLEV = 5.090913E-10 = 7.8 = -1.5 = 0.022 = -5.6E-11 = = = = = 1 0 0 2 6.22E-10

= 0.8744627 = 0.8 = 0.8 = 4.029365E-3 = 0.0305095 = -8.27642E-11 = 1.003159E-4 = 2 )

HSPICE input for open loop configuration: File name: openloop.sp

OPEN LOOP CONFIGURATION *Parameters obtained: *Open-loop gain *Gain-bandwidth product reference *DC power dissipation output voltage *Noise corner frequency .inc './opamp.sp'

*Phase margin *Output current of current *Systematic input-referred *Input-referred spot voltage

.inc './bandgap.sp' .inc './models.sp' .OPTIONS post .temp 20 60 100 .dc sweep temp lin 20 20 100 Vin+ 2 0 DC 0.9 AC 1.0 VDD 4 0 DC 1.8 Vin- 1 0 DC 0.9 VSS 0 5 DC 0 CL 3 0 0.3p X1 1 2 3 4 5 9 OPAMP X2 4 0 9 BANDGAP .op .tf V(3) Vin+ .dc Vin+ .89 .91 100u .noise V(3) Vin+ 1 .print noise inoise onoise .print dc I(X2.R3) .print dc V(3) .ac dec 50 10 10G .print ac VDB(3) VP(3) .print dc power .end

HSPICE input for linear common-mode input swing: File name: inputswing.sp
Linear common-mode input swing .OPTIONS POST .inc './bandgap.sp' .inc './opamp.sp' .inc './models.sp'

.temp 20 60 100 Vind 2 1 ac 1.0 Vinc 1 0 .dc Vind -0.001 0.001 100u sweep vinc poi 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 VDD 4 0 DC 1.8 VSS 0 5 DC 0 CL 3 0 0.3p X1 1 2 3 4 5 9 OPAMP X2 4 0 9 BANDGAP .op .tf V(3) Vind .print dc V(3) .ac dec 50 10 10G sweep vinc poi 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 .print ac Vdb(3) .end

HSPICE input for output swing: File name: outputswing.sp

Output Swing .OPTIONS POST .inc './bandgap.sp'

.inc './opamp.sp' .inc './models.sp' .temp 20 60 100 Vin+ 6 0 .dc Vin+ 0 1.8 1m VDD 4 0 DC 1.8 VSS 0 5 DC 0 CL 3 0 0.3p R1 1 3 25k tc1=100e-6 R2 6 1 1k tc1=100e-6 X1 1 2 3 4 5 9 OPAMP X2 4 0 9 BANDGAP vcm 2 0 0.9 .op .tf V(3) Vin+ .print dc V(3) .end

HSPICE input for overshoot in step response: File name: overshoot.sp

Overshoot in step response .OPTIONS POST .inc './bandgap.sp' .inc './opamp.sp' .inc './models.sp' .temp 20 60 100 Vin+ 2 0 pulse(0.9 1 20n 0.1n 0.1n 70000n 140000n) VDD 4 0 DC 1.8 VSS 0 5 DC 0 CL 3 0 0.3p X1 3 2 3 4 5 9 OPAMP X2 4 0 9 BANDGAP .op .tf V(3) Vin+ .tran 1n 10000n 1n .print tran V(3) .end

HSPICE input for slew rate: File name: slewrate.sp

Slew Rate .OPTIONS POST .inc './bandgap.sp' .inc './opamp.sp' .inc './models.sp' .temp 20 60 100 Vin+ 2 0 pulse(0.9 1.8 20n 0.1n 0.1n 70000n 140000n) VDD 4 0 DC 1.8 VSS 0 5 DC 0 CL 3 0 0.3p X1 3 2 3 4 5 9 OPAMP X2 4 0 9 BANDGAP .op .tf V(3) Vin+ .tran 1n 10000n 1n .print tran V(3) .end

HSPICE input for output resistance of current reference: File name: rout.sp
Output resistance of bandgap reference .inc './bandgap.sp' .inc './opamp.sp' .inc './models.sp' .options post .temp 20 60 100 Vdd 1 0 DC 1.8 Vx 2 0 .dc Vx 0.2 1.6 0.01 X1 1 0 2 BANDGAP .print I(2) .op .end

Appendix B Plots and Waveforms

Open loop gain and phase: 20EC

Open loop gain and phase: 60EC

Open loop gain and phase: 100EC

DC Power Dissipation:

Overshoot in step response: 20EC

Overshoot in step response: 60EC

Overshoot in step response: 100EC

Linear common mode input swing: 20EC

Linear common mode input swing: 60EC

Linear common mode input swing: 100EC

Output swing: 20EC

Output swing: 60EC

Output swing: 100EC

Systematic input-referred offset voltage: 20EC

Systematic input-referred offset voltage: 60EC

Systematic input-referred offset voltage: 100EC

Slew Rate: 20EC

Slew Rate: 60EC

Slew Rate: 100EC

Noise corner frequency: 20EC

Noise corner frequency: 60EC

Noise corner frequency: 100EC

Input-referred spot voltage: 20EC

Input-referred spot voltage: 60EC

Input-referred spot voltage: 100EC

Output current of current reference:

Output resistance of current reference: 20EC

Output resistance of current reference: 60EC

Output resistance of current reference: 100EC