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By the late 1980s, the proliferation of 32-bit CPUs and graphics-intensive operating
systems made it painfully obvious that the 8.33MHz ISA bus was no longer satisfactory. The PC industry began to develop alternative architectures for improved performance. Two architectures are now prominent: VL and PCI. Although the VL bus seems ideal, some serious limitations must be overcome. Perhaps most important is the VL bus dependence on CPU speedfast computers must use wait states with the VL bus, and the VL bus only supports one or two slots (maximum). Another problem is that the VL standard is voluntary, and not all manufacturers adhere to VESA specifications completely. In mid-1992, Intel Corporation and a comprehensive consortium of manufacturers introduced the Peripheral Component Interconnect (PCI) bus. Where the VL bus was designed specifically to enhance PC video systems, the 188-pin PCI bus looks to the future of CPUs (and PCs in general) by providing a bus architecture that also supports peripherals, such as hard drives, networks, etc. This chapter shows you the layout and operations of the PCI bus.
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Performance features include: s Data bursting as normal operating modeboth read and write s Linear burst ordering s Concurrency support (deadlock, buffering solutions) s Low latency guarantees for real-time devices s Access-oriented arbitration (not time slice) s Supports multiple loads (PCI boards) at 33MHz s Error detection and reporting s Multimaster; peer-to-peer communication s 32-bit multiplexed, processor independent s Synchronous, 833MHz (132MB/sec) operation s Variable length, linear bursting (both read and write) s Parity on address, data, command signals s Concurrency/pipelining support s Initialization hooks for auto-configuration s Arbitration supported s 64-bit extension transparently compatible with 32-bit s CMOS drivers; TTL voltage levels s 5-V and 3.3-V compatible
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The PCI bus supports bus mastering, which allows one of a number of intelligent peripherals to take control of the bus to accelerate a high-throughput, high-priority task. PCI architecture also supports concurrencya technique that ensures that the microprocessor operates simultaneously with these masters, instead of waiting for them. As one example, concurrency allows the CPU to perform floating-point calculations on a spreadsheet while an Ethernet card and the LAN have control of the bus. Finally, PCI was developed as a dual-voltage architecture. Normally, the bus is a +5-Vdc system, like other busses. However, the bus can also operate in a +3.3-Vdc (low-voltage) mode.
FIGURE 33-1
TABLE 33-2 PCI BUS PINOUT5 VOLT AND 3.3 VOLT (REV. 2.0) 5 VOLT 12 Vdc TCK Ground TDO +5 Vdc +5 Vdc INTB INTD PRSNT1 Reserved PRSNT2 Ground Ground 3.3 VOLT 12 Vdc TCK Ground TDO +5 Vdc +5 Vdc INTB INTD PRSNT1 Reserved PRSNT2 Key Key PIN B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 3.3 VOLT TRST +12 Vdc TMS TDI +5 Vdc INTA INTC +5 Vdc Reserved +3.3 Vdc (I/O) Reserved Key Key 5 VOLT TRST +12 Vdc TMS TDI +5 Vdc INTA INTC +5 Vdc Reserved +5 Vdc Reserved Ground Ground
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TABLE 33-2 PCI BUS PINOUT5 VOLT AND 3.3 VOLT (REV. 2.0) (CONTINUED) 5 VOLT Reserved Ground Clock Ground REQ +5 Vdc Adr/Dat 31 Adr/Dat 29 Ground Adr/Dat 27 Adr/Dat 25 +5 Vdc C/ BE3 Adr/Dat 23 Ground Adr/Dat 21 Adr/Dat 19 +5 Vdc Adr/Dat 17 C/ BE2 Ground IRDY +5 Vdc DEVSEL Ground LOCK PERR +5 Vdc SERR +5 Vdc C/ BE1 Adr/Dat 14 Ground Adr/Dat 12 Adr/Dat 10 Ground Key Key Adr/Dat 8 Adr/Dat 7 +5 Vdc Adr/Dat 5 3.3 VOLT Reserved Ground Clock Ground REQ +3.3 Vdc Adr/Dat 31 Adr/Dat 29 Ground Adr/Dat 27 Adr/Dat 25 +3.3 Vdc C/ BE3 Adr/Dat 23 Ground Adr/Dat 21 Adr/Dat 19 +3.3 Vdc Adr/Dat 17 C/ BE2 Ground IRDY +3.3 Vdc DEVSEL Ground LOCK PERR +3.3 Vdc SERR +3.3 Vdc C/ BE1 Adr/Dat 14 Ground Adr/Dat 12 Adr/Dat 10 Ground Ground Ground Adr/Dat 8 Adr/Dat 7 +3.3 Vdc Adr/Dat 5 PIN B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 PIN A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 3.3 VOLT Reserved RST +3.3 Vdc GNT Ground Reserved Adr/Dat 30 +3.3 Vdc Adr/Dat 28 Adr/Dat 26 Ground Adr/Dat 24 IDSEL +3.3 Vdc Adr/Dat 22 Adr/Dat 20 Ground Adr/Dat 18 Adr/Dat 16 +3.3 Vdc FRAME Ground TRDY Ground STOP +3.3 Vdc SDONE SBO Ground PAR Adr/Dat 15 +3.3 Vdc Adr/Dat 13 Adr/Dat 11 Ground Adr/Dat 9 Ground Ground C/ BE0 +3.3 Vdc Adr/Dat 6 Adr/Dat 4 5 VOLT Reserved RST +5 Vdc GNT Ground Reserved Adr/Dat 30 +5 Vdc Adr/Dat 28 Adr/Dat 26 Ground Adr/Dat 24 IDSEL +5 Vdc Adr/Dat 22 Adr/Dat 20 Ground Adr/Dat 18 Adr/Dat 16 +5 Vdc FRAME Ground TRDY Ground STOP +5 Vdc SDONE SBO Ground PAR Adr/Dat 15 +5 Vdc Adr/Dat 13 Adr/Dat 11 Ground Adr/Dat 9 Key Key C/ BE0 +5 Vdc Adr/Dat 6 Adr/Dat 4
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TABLE 33-2 PCI BUS PINOUT5 VOLT AND 3.3 VOLT (REV. 2.0) (CONTINUED) 5 VOLT Adr/Dat 3 Ground Adr/Dat 1 +5 Vdc ACK64 +5 Vdc +5 Vdc Key Key Reserved Ground C/ BE6 C/ BE4 Ground Adr/Dat 63 Adr/Dat 61 +5 Vdc Adr/Dat 59 Adr/Dat 57 Ground Adr/Dat 55 Adr/Dat 53 Ground Adr/Dat 51 Adr/Dat 49 +5 Vdc Adr/Dat 47 Adr/Dat 45 Ground Adr/Dat 43 Adr/Dat 41 Ground Adr/Dat 39 Adr/Dat 37 +5 Vdc Adr/Dat 35 Adr/Dat 33 Ground Reserved Reserved Ground 3.3 VOLT Adr/Dat 3 Ground Adr/Dat 1 +3.3 Vdc ACK64 +5 Vdc +5 Vdc Key Key Reserved Ground C/ BE6 C/ BE4 Ground Adr/Dat 63 Adr/Dat 61 +3.3 Vdc Adr/Dat 59 Adr/Dat 57 Ground Adr/Dat 55 Adr/Dat 53 Ground Adr/Dat 51 Adr/Dat 49 +3.3 Vdc Adr/Dat 47 Adr/Dat 45 Ground Adr/Dat 43 Adr/Dat 41 Ground Adr/Dat 39 Adr/Dat 37 +3.3 Vdc Adr/Dat 35 Adr/Dat 33 Ground Reserved Reserved Ground PIN B56 B57 B58 B59 B60 B61 B62 Key Key B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 B93 B94 PIN A56 A57 A58 A59 A60 A61 A62 Key Key A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94 3.3 VOLT Ground Adr/Dat 2 Adr/Dat 0 +3.3 Vdc REQ64 +5 Vdc +5 Vdc Key Key Ground C/ BE7 C/ BE5 +3.3 Vdc PAR64 Adr/Dat 62 Ground Adr/Dat 60 Adr/Dat 58 Ground Adr/Dat 56 Adr/Dat 54 +3.3 Vdc Adr/Dat 52 Adr/Dat 50 Ground Adr/Dat 48 Adr/Dat 46 Ground Adr/Dat 44 Adr/Dat 42 +3.3 Vdc Adr/Dat 40 Adr/Dat 38 Ground Adr/Dat 36 Adr/Dat 34 Ground Adr/Dat 32 Reserved Ground Reserved 5 VOLT Ground Adr/Dat 2 Adr/Dat 0 +5 Vdc REQ64 +5 Vdc +5 Vdc Key Key Ground C/ BE7 C/ BE5 +5 Vdc PAR64 Adr/Dat 62 Ground Adr/Dat 60 Adr/Dat 58 Ground Adr/Dat 56 Adr/Dat 54 +5 Vdc Adr/Dat 52 Adr/Dat 50 Ground Adr/Dat 48 Adr/Dat 46 Ground Adr/Dat 44 Adr/Dat 42 +5 Vdc Adr/Dat 40 Adr/Dat 38 Ground Adr/Dat 36 Adr/Dat 34 Ground Adr/Dat 32 Reserved Ground Reserved
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able to find 12 Vdc and +5 Vdc, regardless of whether the bus is standard or low-voltage.
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For a low-voltage bus, you should also be able to find a +3.3-Vdc supply. If any of these supply levels are low or are absent, troubleshoot or replace the power supply. s CLOCK (pin B16) The Clock signal provides timing signals for the expansion device. It can be adjusted between DC (0Hz) and 33MHz. If this signal is absent, the expansion board will probably not run. Check the clock-generating circuitry on the motherboard or replace the motherboard outright. s RST (pin B18) The Reset line can be used to re-initialize the PCI expansion device. This line should not be active for more than a few moments after power is applied or after a warm reset is initiated.
PCI busses are highly dependent on a myriad of settings in the CMOS setup. Always check for proper CMOS configuration whenever you encounter trouble with PCI devices or bus performance.
Another point to consider is that bus connectors are mechanical devices. As a result, they do not last forever. If you or your customer are in the habit of removing and inserting boards frequently, it is likely that the metal fingers providing contact will wear, resulting in unreliable connections. Similarly, inserting a board improperly (or with excessive force) can break the connector. In extreme cases, even the motherboard can be damaged. The first rule of board replacement is: always remove and re-insert the suspect board. It is not uncommon for oxides to develop on board and slot contacts that may eventually degrade signal quality. By removing the board and re-inserting it, you can wipe off any oxides or dust and possibly improve the connections. The second rule of board replacement is: always try a board in another expansion slot before replacing it. This way, a faulty bus slot can be ruled out before suffering the expense of a new board. Keep in mind that many current PCI motherboards have only one or two PCI slotsthe remainder are ISA slots. If a bus slot is defective, a technician can do little, except: 1 Block the slot and inform the customer that it is damaged and should not be used. 2 Replace the damaged bus slot connector (a tedious and time-consuming task) and pass the labor expense on to the customer. 3 Replace the motherboard outright (also a rather expensive option).
Further Study
Thats it for Chapter 33. Be sure to review the glossary and chapter questions on the accompanying CD. If you have access to the Internet, take a look at some of these various PCI resources: PCI Special Interest Group Home Page: http://www.pcisig.com/ PC2 Consulting: http://www.pc2.com/ CompactPCI Home Page: http://www.compactpci.com/ Small PCI: http://www.pcisig.com/current/smallpci/