In this project, we are building up a Modified Booth Encoding Radix-4 8-bit Multiplier using 0.5um CMOS technology.

Booth multiplication allows for smaller, faster multiplication circuits through encoding the signed numbers to 2 s complement, which is also a standard technique used in chip design, and provides significant improvements by reducing the number of partial product to half over long multiplication techniques. In this project, we demonstrate an extendable system diagram for 8-bit radix-4 MBE algorithm. Encoder, decoder and Carry Look Ahead Adder (CLA) are presented in this system.

Booth decoder

Booth encoder

12 Bit adder:We make use of 3 4-bit CLA Adders to implement 12 bit adders to sum all the partial product rows.

Figure 2 Proposed encoder for the glitchfree MBE scheme in gate level and in transistor level. In the Figure 1 design, the delay from X and Y to PPj is one XOR/XNOR gate delay plus one complex gate delay. However, the delay time in the complex gate of MBE decoder is still large to be the bottleneck in a pipelined Booth multiplier because of its large fan-in. To reduce the delay time in the complex gate, the delay time in one complex gate of fan-in 6 can be divided into the delay time of 3 stages which include one complex gate of fan-in 3, one NAND gate of fan-in 2, and one inverter Because of much smaller loading capacitance at each stage of the levelized new MBE decoder, we can accelerate the speed of critical path in the MBE decoder. Also we can provide fast rise time and fall time

because of the inverter in the output stage of the levelized new MBE decoder. As a result, the new MBE decoder with better performance in both speed and power respects because of larger driving force in a very high speed multiplier.The new MBE decoder is presented in transistor

INPUT Y

I N P U T X

E N C O D E R

9 BIT DECODED (2 S COMPLEME NT)

12 bit adder

OUTPUT

FLOOR PLAN

Main reference:
Shiann-Rong Kuang,Member,IEEE,Jiun-Ping Wang,and Cang-Yuan Guo IEEE TRANSATIONS ON CIRCUITS AND SYSTEMS2:EXPRESS BRIEFS.VOL.56.NO.5,MAY2009
Manuscript received October 31,2008;revised January 20,2009. Current version published May15,2009. This work was supported in part by the National Science Council,Taiwan,under Grant NSC97-2220-E-110-006. This paper was recommended by Associate Editor A.-Y.Wu. The authors are with department of Computer science and Engineering ,National Sun Yat sen University,Kaohsiung 80424,Taiwan.