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REPOR T
SHANKARAGATTA-577451
Project on
MODIFIED BOOTH MULTIPLIER WITH A REGULAR PARTIAL PRODUCT ARRAY
Dissertation submitted in partial fulfillment of the requirements for the award of degree in BACHELOR OF ENGINEEGING in ELECTRONICS AND COMMUNICATION by
PROJECT MEMBERS SADASHIV J.PATGAR BE080266 SHASHIDHAR S.B. BE080273 SHAMBULING M.S. BE080272 NAVEEN S. R. BE070251 VIJAYKUMAR P.H. BE080286
M.Tech
DAVANGERE - 577004.
Synopsis:
delay, and power consumption when compared with conventional MBE multipliers.
INTRODUCTION:
Enhancing the processing performance and reducing the power dissipation of the systems are the most important design challenges for multimedia and DSP applications. Multiplication consists of 3 steps: 1)Recoding and generating partial products. 2)Reducing the partial products by partial product reduction schemes. 3)Adding the remaining two rows of partial products by using a carry propagate adder to obtain the final product. The partial products are generally generated by modified booth encoding algorithm. The MBE reduces the number of partial product rows to be added by half, thus reducing the size and enhancing the speed of reduction tree. The conventional MBE algorithm generates n/2+1 partial product rows rather than n/2 due to extra partial product(neg bit) at the least significant bit position of each partial product row for negative encoding, leading to an irregular partial product array and a complex reduction tree. In addition the proposed approach can also be applied to regularize the partial product array of post truncated MBE multipliers. Post truncated multiplication which generates 2n bit product and then rounds the product into n bits is desirable in many multimedia and DSP systems due
to fixed register size and bus width inside the hardware. Experimental results shows that proposed general and post truncated MBE multipliers with a partial product array can achieve significant improvement in area, delay and power consumption when compared with conventional MBE multipliers.
BOOTH RECODING: Recoding is done following table: Xi+1 0 0 1 1 Example: 0 0 6x 0 1 1 1 0 14 0 0 (1 1 0 Xi 0 1 0 1 according Y 0 1 -1 0 to the
+1 0 0 -1 0 1 6) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0
0 0
0 0
1 1
1 0
0 1 0 1 0 0 84 and
Advantages
Depends on the architecture Potential advantage: might reduce the # of 1s in multiplier In the multipliers that we have seen so far:
Doesnt save inspeed (still have to wait for the critical path, e.g., the shift-add delay in sequential multiplier)
Groups 0 1 1 0 1 0 0 1 0 0 1 1
Coding 1Y -2 Y -1 Y 2Y
Xi+1 Xi 0 0 0 0 1 1 1 0 0 1 1 1 0 0 1
Xi-1 0 1 1 0 1 0 1 0 1
Modified
Booth
1 0 0 1 0 1 0 1 -107 0 1 1 0 1 0 0 1 105
1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1 1Y 0 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 0 1 0 0 1 0 1 0 1 0 -2 Y -1 Y 2Y
1 1 0 1 0 1 0 0 0 0 0 1 1 1 0 1 11235
BLOCK DIAGRAM OF MODIFIED BOOTH MULTIPLIER WITH A REGULAR PARTIAL PRODUCT ARRAY:
Multiplicand X
Multiplier Y
Booth decoder
Booth encoder
C L A adder
Product