EX.NO.

1 DATE: AIM:

Design of Adder using VHDL

To develop the source code for half adder and full adder by using VHDL and obtain the simulation output.

TOOLS REQUIRED: Xilinx-9.2i Software package

THEORY:

Half-Adder A combinational circuit that performs the arithmetic addition of two bits is called a Half Adder. The input variables of a half adder are called augend and addend bits. The output variables are called the sum and carry. It is implemented by using AND and XOR gates. Full-Adder A combinational circuit that performs the arithmetic addition of three bits is called a Full Adder. The input variables of a Full adder are called augend and addend bits. The output variables are called the sum and carry. It is implemented by using AND, OR and XOR gates.

Half Adder Truth Table Input A B 0 0 0 1 1 0 1 1 Output sum carry 0 0 1 0 1 0 0 1

a
b

Logic Circuit

sum=ab+ab carry=ab

Full Adder Truth Table A 0 0 0 0 1 1 1 1 Input b 0 0 1 1 0 0 1 1 Output cin 0 1 0 1 0 1 0 1 sum 0 1 1 0 1 0 0 1 cout 0 0 0 1 0 1 1 1

Logic Circuit

a b cin

sum

cout

PROCEDURE: 1. Start the Xilinx tool 2. Create project using the project wizard 3. Select VHDL module for writing the code in VHDL 4. Initialize the entity declaration by input and output ports entry 5. Write the architecture part of the coding in VHDL for adder 6. Synthesize and rectify the errors 7. Create a test bench waveform 8. Simulate the output after giving the inputs 9. Verify the operation of the adder. PROGRAM: Half adder library ieee; use ieee.std_logic_1164.all; entity ha is port(a,b:in std_logic; sum,carry:out std_logic);

end ha; architecture ha1 of ha is begin process(a,b) begin sum <= a xor b; carry <= a and b; end process; end ha; Full adder library ieee; use ieee.std_logic_1164.all; entity fulladder is port(a,b,c:in std_logic; sum,carry:out std_logic); end fulladder; architecture behavioral of fulladder is begin process(a,b,c) begin sum <=(a xor b) xor c; carry <=(a and b) or(b and c) or(a and c); end process; end behavioral; SIMULATION OUTPUT:

RESULT: Thus the source code for half adder and full adder was developed and also verified its output.

ADDERS AND SUBTRACTORS AIM

To write a source code and simulate in VHDL mode for Half Adder Half Subtractor Full Adder Full Subtractor

PROGRAM:
--BEHAVIOURAL MODEL library ieee; use ieee.std_logic_1164.all; entity ha is port(a,b:in std_logic;sum,carry:out std_logic); end ha; architecture ha1 of ha is begin process(a,b) begin sum <= a xor b;

carry <= a and b; end process; end ha; 2) HALF SUBTRACTOR --BEHAVIOURAL MODEL library ieee; use ieee.std_logic_1164.all; entity hsub is port(a,b:in std_logic;diff,borrow:out std_logic); end hsub; architecture hsub1 of hsub is signal abar:std_logic; begin process(a,b) begin abar <= not a; diff <= a xor b; borrow <= abar and b; end process; end hsub1; 3) FULL ADDER --BEHAVIOURAL MODEL library ieee; use ieee.std_logic_1164.all; entity fulladder is port(a,b,c:in std_logic;sum,carry:out std_logic); end fulladder; architecture fulladder_df of fulladder is begin process(a,b,c) begin sum <=(a xor b) xor c; carry <=(a and b) or(b and c) or(a and c); end process; end fulladder_df; 4) FULL SUBTRACTOR --BEHAVIOURAL MODEL library ieee;

use ieee.std_logic_1164.all; entity fullsubtractor is port (a,b,c:in std_logic;difference,borrow:out std_logic); end fullsubtractor; architecture fullsubtractor_df of fullsubtractor is begin process(a,b,c) begin difference<=(a xor b)xor c; borrow<=(not a and(b or c))or(b and c); end process; end;

RESULT:
Thus VHDL program for half adder, half Subtractor, full adder, full Subtractor was compiled, simulated and verified.

MULTIPLEXER AND DEMULTIPLEXER AIM

To write a source code and simulate in VHDL mode for Multiplexer Demultiplexer

PROGRAM:
1) MUTIPLEXER --BEHAVIOURAL MODEL library ieee; use ieee.std_logic_1164.all; entity muxbeh is port(a,b,c,d:in std_logic;s:in std_logic_vector(1 downto 0);y:out std_logic); end muxbeh; architecture muxbeh1 of muxbeh is begin process begin

case s is when "00"=>y<=a; when "01"=>y<=b; when "10"=>y<=c; when others=>y<=d; end case; wait on s,a,b,c,d; end process; end muxbeh1; 2) DEMULTIPLEXER --BEHAVIOURAL MODEL library ieee; use ieee.std_logic_1164.all; entity demuxbeh is port(a:in std_logic;s:in std_logic_vector(1 downto 0);y:out std_logic_vector(3downto 0)); end demuxbeh; architecture demuxbeh1 of demuxbeh is begin process (s) begin case s is when "00"=>y<= a & "000"; when "01"=>y<= "0" & a & "00"; when "10"=>y<= "00" & a & "0"; when others =>y<= "000" & a; end case; end process; end demuxbeh1;

RESULT:
Thus VHDL program for multiplexer, demultiplexer was compiled, simulated and verified.

ENCODER AND DECODER AIM

To write a source code and simulate in VHDL mode for Encoder Decoder

PROGRAM:
1) ENCODER

--BEHAVIOURAL MODEL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity encoder3 is port(s:in std_logic_vector(7 downto 0);a:out std_logic_vector(2 downto 0)); end encoder3;

architecture encoder31 of encoder3 is begin process(s) begin case s is when "10000000"=>a<="000"; when "01000000"=>a<="001"; when "00100000"=>a<="010"; when "00010000"=>a<="011"; when "00001000"=>a<="100"; when "00000100"=>a<="101"; when "00000010"=>a<="110"; when others=>a<="111"; end case; end process; end encoder31;

2) DECODER
--BEHAVIOURAL MODEL library ieee; use ieee.std_logic_1164.all; entity decobehav is port(s:in std_logic_vector(2 downto 0);a:out std_logic_vector(7 downto 0)); end decobehav; architecture decobehav1 of decobehav is begin process (s) begin case s is when "000"=>a<="10000000"; when "001"=>a<="01000000"; when "010"=>a<="00100000"; when "011"=>a<="00010000"; when "100"=>a<="00001000"; when "101"=>a<="00000100"; when "110"=>a<="00000010"; when others=>a<="00000001"; end case; end process; end decobehav1;

RESULT:

Thus VHDL program for encoder, decoder was compiled, simulated and verified.

FLIPFLOPS AIM
To write a source code and simulate in VHDL mode for D-Flip Flop JK-Flip Flop T-Flip Flop SR-Flip Flop

PROGRAM:
1) D-FLIPFLOP library ieee; use ieee.std_logic_1164.all; entity dff is port(d,clk:in std_logic;q:out std_logic); end entity; architecture dff_beh of dff is begin process(d,clk)

begin if clk = '0'then q<='0'; else if(clk='1' and clk'event)then q<=d; end if; end if; end process; end; 2) JK-FLIPFLOP library ieee; use ieee.std_logic_1164.all; entity jk is port(j,k,clk:in std_logic;q,qbar:inout std_logic); end jk; architecture jk1 of jk is begin process (clk) begin if clk'event and clk='1' then if j='0' and k='0' then q<=q; elsif j='0' and k='1' then q<='0'; elsif j='1' and k='0' then q<='1'; elsif j='1' and k='1' then q<=not q; end if; end if; end process; qbar<=not q; end jk1; 3) T-FLIPFLOP library ieee; use ieee.std_logic_1164.all; entity tflip is port(t,clk:in std_logic;q,qbar:inout std_logic); end tflip; architecture tflip1 of tflip is begin process(clk)

begin q<='0'; if clk='1' and clk'event then if t='0' then q<=q; elsif t='1' then q<=not q; end if; end if; end process; qbar<=not q; end tflip1; 4) SR-FLIPFLOP library ieee; use ieee.std_logic_1164.all; entity sr is port(s,r,clk:in std_logic;q,qbar:inout std_logic); end sr; architecture sr1 of sr is begin process (clk) begin if clk'event and clk='1' then if s='0' and r='0' then q<=q; elsif s='0' and r='1' then q<='0'; elsif s='1' and r='0' then q<='1'; elsif s='1' and r='1' then q<='u'; end if; end if; end process; qbar<=not q; end sr1;

RESULT:
Thus VHDL program for flip-flops was compiled, simulated and verified.

COUNTERS AIM
To write a source code and simulate in VHDL mode for UP-DOWN counter.

PROGRAM:
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity updown is port(d:in std_logic_vector(3 downto 0);enable,clk,mode:in std_logic;count:out std_logic_vector(3 downto 0)); end updown; architecture updown1 of updown is signal z:std_logic_vector(3 downto 0); begin process(clk,enable)

begin if(clk='1' and clk'event) then if(enable='1') then if(mode='0') then z<=signed(z)+'1'; else if(mode='1') then z<= signed(z)-'1'; end if; end if; else z<="0000"; end if; end if; end process; count<=z; end updown1;

RESULT:
Thus VHDL program for Up-Down counter was compiled, simulated and verified.

SHIFT REGISTERS AIM

To write a source code and simulate in VHDL mode for Serial In Serial Out [SISO] Parallel In Parallel Out [PIPO]

PROGRAM:
1) SERIAL IN SERIAL OUT library ieee; use ieee.std_logic_1164.all; entity shift is port(d: in std_logic;clk: in std_logic;q: out std_logic_vector(3 downto 0)); end shift; architecture shift1 of shift is signal t:std_logic_vector(3 downto 0); begin

process (clk) begin if (clk'event and clk='1') then t(3)<=d; t(2)<=t(3); t(1)<=t(2); t(0)<=t(1); end if; end process; q <= t; end shift1; 2) PARALLEL IN PARALLEL OUT library ieee; use ieee.std_logic_1164.all; entity pipo is generic(n:integer:=4); port(d:in std_logic_vector(n-1 downto 0);r,e,clk:in std_logic;q:out std_logic_vector(n1downto 0)); end pipo; architecture pipo1 of pipo is begin process(r,clk) begin if( r='0') then q<=(others=>'0'); elsif clk'event and clk='1' then if e='1' then q<=d; end if; end if; end process; end pipo1;

RESULT:
Thus VHDL program for Shift Registers was compiled, simulated and verified.

2*2 MULTIPLIER AIM

To write a source code and simulate in VHDL mode for 2*2 Multiplier.

PROGRAM:
library ieee; use ieee.std_logic_1164.all; entity mul is port(a0,a1,b0,b1:in std_logic;l1,l2,l3,l4:out std_logic); end mul; architecture mul1 of mul is signal s1,s2,s3,c:std_logic; component and2 port(m,n:in std_logic;o:out std_logic); end component; component ha port (a,b:in std_logic;sum,carry:out std_logic);

end component; begin x1: and2 port map(a0,b0,l1); x2: and2 port map(a1,b0,s1); x3: and2 port map(a0,b1,s2); x4: ha port map(s1,s2,l2,c); x5: and2 port map(a1,b1,s3); x6: ha port map(c,s3,l3,l4); end mul1;

RESULT:
Thus VHDL program for 2*2 Multiplier was compiled, simulated and verified.