A10 Datasheet 2011.8.22

Allwinner Technology CO., Ltd.
A10
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Copyright 2011 Allwinner Technology. All Rights Reserved.
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2011-8-22
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V1.00
A10 Datasheet
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Allwinner Technology CO., Ltd. Revision History

Version Date Section/ Page Changes compared to previous issue
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Technical Items
NO. Abbreviation Full Name
ARM Cortex-A8
ARM Cortex-A8
Mali-400
Mali-400
SDRAM
Synchronous
Random Access Memory
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Serial Peripheral Interface Universal Asynchronous Receiver/Transmitter Dynamic-Memory-Allocation in a IIS Pulse Code Modulation Audio Codec 97 2
PWM
Pulse Width Modulator
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ARM Holdings Dynamic practical switches by master/slave mode DCE) or data set computer together analog signals
SPI
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6 UART 7 DMA 8 I2S 9 PCM 10 AC97
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Description a processor core designed the by ARM v7 Holdings implementing ARM instruction set architecture A 2D/3D graphic processor unit designed by dynamic random access memory (DRAM) that is synchronized with the system bus a commonly used technique for controlling power to inertial electrical devices, made modern electronic power a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in where the master device initiates the data frame used for serial communication with a peripheral, modem (data carrier equipment, the allocation of memory storage for use program during the run-time of that program an electrical serial bus interface standard used for connecting digital audio devices method used to digitally represent sampled Intel Corporation's Audio Codec standard
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V1.00
2011-8-22
Initial version

developed by the Intel Architecture Labs in 1997, and used mainly in motherboards, modems, and sound cards. 11 Audio Codec Audio Codec a computer program implementing an algorithm that compresses and
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decompresses digital audio data according to a given audio file format or streaming
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SD
Security Digital3.0
non-volatile
developed by the SD Card Association for use in portable devices.
dual-role controller, which supports both 13 USB OTG USB On-The-Go
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EHCI
Enhanced Interface
Host
Controller
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LRADC
Low Resolution Analog to Digital Converter
16 17
TP TS
Touch Panel Controller Transport Stream
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CAN
Controllerarea network
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microcontrollers Advanced An old computer different image Multimedia a compact 3
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PATA
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Parallel Technology Attachment Serial Advanced Technology Attachment Camera Sensor Interface High-Definition Interface
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SATA
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21 CSI 22 HDMI
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compliant with the On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a a high-speed controller standard that is publicly specified A module which can transfer analog signal to digital signal A Human-Machine Interactive Interface A data stream defined by ISO13818-1, which consists of one or more programs with video and audio data. a vehicle bus standard designed to allow and devices to communicate with each other within a vehicle without a host computer bus interface for connecting hard disk drivers, optical drivers, and compact flash card a computer bus interface for connecting host bus adapters to mass storage devices such as hard disk drives and optical drives. the hardware block that interfaces with sensor interfaces and provides a standard output that can be used for subsequent image processing. audio/video interface for transmitting uncompressed digital data
Host and device functions and is full
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memory card format
media audio format.

Contents
A10
Revision History ...................................................................................................................................... 2 Technical Items........................................................................................................................................ 2 1. 2. 3. 4. Introduction ...................................................................................................................................... 7 Feature .............................................................................................................................................. 7 Functional Block Diagram ............................................................................................................. 10 Pin Assignments ............................................................................................................................ 11 4.1. 4.2. 5. Dimension ................................................................................................................................. 11
Pin Description............................................................................................................................... 14 5.1. 5.2. 5.3. Pin Characteristics .................................................................................................................... 14 Multiplexing Characteristics ...................................................................................................... 36 Power and Miscellaneous Signals ............................................................................................ 43
6.
Electrical Characteristics .............................................................................................................. 47 6.1. 6.2. 6.3. 6.4. Absolute Maximum Ratings ...................................................................................................... 47 Recommended Operating Conditions ....................................................................................... 48
Oscillator Electrical Characteristics ........................................................................................... 48 24MHz Oscillator Characteristics ................................................................................... 49 32.768kHz Oscillator Characteristics ............................................................................. 49
6.4.1. 6.4.2. 6.5. 6.6.
Power up/down and Reset Specifications ................................................................................. 50 This section includes specification for the following: ................................................................. 50 Power-up Sequence......................................................................................................... 50 Power-down Sequence.................................................................................................... 50
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7. 7.1. 7.2. 8. 9. 9.1.
6.6.1. 6.6.2.
Clock Controller ............................................................................................................................. 50 Clock Tree Diagram .................................................................................................................. 51 PLL Diagram ............................................................................................................................. 54
PWM ................................................................................................................................................ 54 8.1.1. Overview........................................................................................................................... 54 8.1.2. PWM Signal Description.................................................................................................. 54 Timer Controller ............................................................................................................................. 54 Overview ................................................................................................................................... 54
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DC Electrical Characteristics..................................................................................................... 48
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5.3.1. 5.3.2.
Power Domain Signal Description.................................................................................. 44 Miscellaneous Signal Description .................................................................................. 46
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Pin Map..................................................................................................................................... 12
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10. 10.1. 10.2. 11.
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Interrupt Controller..................................................................................................................... 55 Overview ............................................................................................................................... 55 External Interrupt Signal Description ..................................................................................... 55
DMA Controller ........................................................................................................................... 56 Overview ............................................................................................................................... 56
11.1. 12.
12.1. 12.2. 13.
Overview ............................................................................................................................... 56 NAND Flash Controller Signal Description ............................................................................ 57
SD3.0 Controller ......................................................................................................................... 58 SD 3.0 Overview ................................................................................................................... 58 SD3.0 Controller Signal Description ...................................................................................... 58
13.1. 13.2. 14.
Two Wire Interface ...................................................................................................................... 59 Overview ............................................................................................................................... 59 TWI Controller Signal Description ......................................................................................... 59
14.1. 14.2. 15.
SPI Interface................................................................................................................................ 59 Overview ............................................................................................................................... 59 SPI Controller Signal Description .......................................................................................... 60
15.1. 15.2. 16.
UART Interface............................................................................................................................ 60
16.2. 17.
IR Interface .................................................................................................................................. 61 Overview ............................................................................................................................... 61 IR Controller Signal Description ............................................................................................ 61
17.1. 17.2. 18.
USB OTG Controller ................................................................................................................... 62 Overview ............................................................................................................................... 62 USB OTG Controller Signal Description ................................................................................ 62
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18.1. 18.2. 19. 19.1. 19.2. 20. 20.1. 20.2. 21.
USB HOST Controller ................................................................................................................. 62 Overview ............................................................................................................................... 62 USB HOST Controller Signal Description.............................................................................. 63
Digital Audio Interface................................................................................................................ 63 Overview ............................................................................................................................... 63 Digital Audio Signal Description............................................................................................. 63

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AC97 Interface ............................................................................................................................ 64 Copyright 2011 Allwinner Technology. All Rights Reserved.
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16.1.
Overview ............................................................................................................................... 60 UART Controller Signal Description ...................................................................................... 61
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NAND Flash Controller............................................................................................................... 56

21.1. 21.2. 22.
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Overview ............................................................................................................................... 64 AC97 Signal Description........................................................................................................ 64
Audio Codec ............................................................................................................................... 64 Overview ............................................................................................................................... 64 Audio Codec Signal Description ............................................................................................ 65
22.1. 22.2. 23.
23.1. 23.2. 24.
Overview ............................................................................................................................... 65 LRADC Signal Description .................................................................................................... 66
Keypad Interface......................................................................................................................... 66 Overview ............................................................................................................................... 66 Keypad Signal Description .................................................................................................... 66
24.1. 24.2. 25.
Touch Panel ................................................................................................................................ 66 Overview ............................................................................................................................... 66 Touch Panel Signal Description............................................................................................. 67
25.1. 25.2. 26.
Port Controller ............................................................................................................................ 67 Port Description..................................................................................................................... 67
26.1. 27.
Camera sensor interface............................................................................................................ 67 Feature .................................................................................................................................. 67
27.1. 27.2. 28.
Universal LCD/TV Timing Controller......................................................................................... 68 Overview ............................................................................................................................... 68 LCD Signal Description ......................................................................................................... 69
28.1. 28.2. 29.
Mixer Processor.......................................................................................................................... 69 Overview ............................................................................................................................... 69
29.1.
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30. 30.1. 30.2. 31.
29.2. Block diagram........................................................................................................................ 70 29.2.1. Layer rotation and mirroring control................................................................................ 70 TV Encoder.................................................................................................................................. 71 Feature .................................................................................................................................. 71 TV-OUT Signal Description ................................................................................................... 71
Declaration .................................................................................................................................. 72
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Camera sensor Signal Description ........................................................................................ 68
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LRADC ......................................................................................................................................... 65
Allwinner Technology CO., Ltd. 1. Introduction
A10
With ARM Cortex A8 core, A10 will drive SoC into a brand new era of connected Smart HD which can enhance the application of connected HD SOC as well as user experiences of consumer electronics like multimedia products. Due to its outstanding connected HD video performance and cost efficiency, the highly integrated A10 is target at cool HD pad which can bring end-users better experiences of surfing, watching, gaming and reading.
2.
Feature
CPU

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ARM Cortex-A8 Core 32KB I-Cache/32KB D-Cache/256K L2 Cache Using NEON for video, audio,and graphic workloads eases the burden of supporting more delicated accelerators across the SoC and enable the system to support the standards of tomorrow RCT JAVA-Accelerations to optimize just in time(JIT) and dynamitic adaptive compilation(DAC), and reduces memory footprint up to three times Trustzone technology allows for secure transactions and digital right managements(DRM)
GPU
3D 2D
support Open GL ES 2.0 / open VG 1.1
support BLT / ROP2/3/4 Rotation 90/180/270 degree Mirror / alpha (including plane and pixel alpha) / color key support Scaling function with 4*4 taps and 32 phase
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There is no doubt that low power consumption and excellent user experience will be always on the top of end-users wish list. A10 has adopted Allwinnertechs most advanced technology of video CODEC and power consumption is much lower during 1080p decoding process. Whats more, Allwinnertech will keep applying progressive VLSI design under new process so that end products can become even more competitive with shorter R&D cycle and easier production advantages.
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Besides self-developed display acceleration frame, MALI400 2D/3D GPU has also been introduced to strengthen the connected smart HD SOC in terms of high profile display so that it can support popular smart systems such as Android2.3/3.0 better and improve the performance of Android-loaded products as well as user experience.
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The A10 is dedicated to furthering the development of connected HD video CODEC application, and 1080P H.264 high profile encoding technology can become one of the benchmarks. Besides its remarkable super HD 2160p video decoding capability, A10 can stream smoothly HD video over internet, including FLASH10.3/HTML5/3RD APK.

Support format conversion
A10
VPU
Video Decoding (Super HD 2160P) Support all popular video formats, including VP8, AVS, H.264, H.263, VC-1, MPEG-1/2/4 Support 1920*1080@60fps in all formats Video Encoding Support encoding in H.264 High Profile format 1080p@60fps 720p @100fps
Display Output Ability

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ImageInput Ability
Support HDMI V1.3/V1.4 Flexible LCD interface (CPU / Sync RGB / LVDS) up to 1920*1080 resolution CVBS / YPbPr up to 1920*1080 resolution
Dual camera sensor interface (CSI0 supports ISP function)
Memory
16/32-bits SDRAM controller support DDR2 SDRAM and DDR3 SDRAM up to 800Mbps Memory Capacity up to 16 G-bits 8-bits NAND Flash Controller with 8 chip select and 2 r/b signals Support SLC/MLC/TLC/DDR NAND ECC up to 64bit
Peripherals

1 USB 2.0 OTG controller for general application/2 USB2.0 EHCI Controller for HOST application 4 high-speed Memory controller supports SD version 3.0 and MMC version 4.2 8 UARTs with 64 Bytes TX FIFO and 64 Bytes RX FIFO,
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Four moveable and size-adjustable layers Support 8 tap scale filter in horizontal and 4 tap in vertical direction for scaling support Multi-format image input support Alpha blending / color key / gamma support Hardware cursor / sprite support Vertical keystone correction support Output color correction (luminance / hue / saturation etc) support motion adaptive de-interlace support Video enhancement support 3D format content input/output format convert/display (including HDMI)
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Display Processing Ability
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System

Security
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Security System Support DES, 3DES, AES encryption and decryption. Support SHA-1, MD5 message digest Support hardware 64-bit random generator 128-bits EFUSE chip ID
Package
TFBGA441package 0.8mm pitch
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8 channel normal DMA and 8 channel dedicateed DMA Internal (32K+64K) SRAM on chip 4 timer, 1 RTC timer and 1 watchdog
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1 UART with full modem function 2 UARTs with RTS/CTS hardware flow control 5 UARTs with two wires 4 SPI controller 1 dedicated SPI controller for serial NOR Flash boot application 3 SPI for general applications 3 Two-Wire Interfaces up to 400Kbps Key Matrix (8x8) with internal debounce filter IR controller supports MIR, FIR and IR remoter 2-CH 6-bits LRADC for line control Internal 4-wire touch panel controller with pressure sensor and 2-point touch I2S/PCM controller for 8-channel output and 2-channel input AC97 controller compatible with AC97 version 2.3 standard Internal 24-bits Audio Codec for 2 channel headphone, 2 channel microphone, 2 channel FM input and Line input 2 PWM controller
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Allwinner Technology CO., Ltd. 3. Functional Block Diagram
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32.768K Crystal Microphone Audio Input Audio Output Class D AMP G-Sensor Security
Cable Line
24M Crystal
Nand Flash
DDR DRAM
Card Slot2,3
Card Slot0,1 Card Controller0 WIFI
LCD Display &Touch
LVDS Display
HD Video Display
Head Phone
HP AMP
Audio DAC
Card Controller2
Touch Controller
LVDS Controller
E-Mac IR Controller ADC
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HDMI Controller Video TV-OUT USB0 Controller USB1,2 Controller PMU System Power 5V USB0 OGT USB1,2 HOST
CortexA8 GPU VE Processor
LCD Controller
IR
Key
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3G
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Card Controller3 LCD Buffer HDMI Port AC Adapter Plug AC Line Battery Power Management Support 4.1V/4.2V/4.36V
Audio ADC
Card Controller1
Allwinner Technology CO., Ltd. 4.

4.1.
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Pin Assignments
Dimension
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Figure 4-1 A10 TFBGA441 Package Dimension
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4.2.
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Pin Map
The following pin maps show the top view of the 441-pin FBGA package pin assignments in four quadrants (A, B, C, D).
Figure 4-2 TFBGA441 Pin Map-Top View [Quadrant A]
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Figure 4-3 TFBGA441 Pin Map-Top View [Quadrant B]
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Figure 4-4 TFBGA441 Pin Map-Top View [Quadrant C]
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Figure 4-5 TFBGA441Pin Map-Top View [Quadrant D]
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5.1.
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Pin Description
Pin Characteristics
1. BALL#: Ball numbers on the bottom side associated with each signals on the bottom. 2. Pin Name: Names of signals multiplexed on each ball (also notice that the name of the pin is the signal name in function 0). 3. Function: Multiplexing function number. Function 0 is the the default function, but is not necessarily the primary mode. Functions 1 to 5 are possible modes for alternate functions. 4. Type: signal direction - I = Input - O = Output - I/O = Input/Output - A = Analog - AIO = Analog Input/Output - PWR = Power - GND = Ground 5. Pin Reset State: The state of the terminal at reset (power up). - 0: The buffer drives VOL(pull down/pull up resistor not activated) - 0 (PD): The buffer drives VOL with an active pull down resistor. - 1: The buffer drives VOH (pull down/pull up resistor not activated). - 1 (PU): The buffer drives VOH with an active pull up resistor. - Z: High-impedance - L: High-impedance with an active pull down resistor. - H: High-impedance with an active pull up resistor. 6. Pull Up/Down: Denotes the presence of an internal pull up or pull down resister. Pull up and pull down resistor can be enabled or disabled via software. 7. Buffer Strength: Drive strength of the associated output buffer.
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BALL#
AB4 SDQ0 AC7 AC4 AB8 AC8 AB5 AB7 SDQ1 SDQ2 SDQ3 SDQ4 SDQ5 SDQ6
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Pin Name Function
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Table 5-1
Table 5-1 Pin Characteristics (FBGA441)
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Type
I/O I/O I/O I/O I/O I/O I/O
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Reset State Pull Up/Down Buffer Strength (mA)

BALL#
AC3 AB2 Y1 AC2 Y2 AA1 AB3 W2 AC1 N1 T2 N2 U1 U2 P1 T1 M2 L1 H1 L2 H2 J1 M1 G2 K2
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Pull Up/Down Buffer Strength (mA)
Pin Name
SDQ7 SDQ8 SDQ9 SDQ10 SDQ11 SDQ12 SDQ13 SDQ14 SDQ15 SDQ16 SDQ17 SDQ18 SDQ19 SDQ20 SDQ21 SDQ22 SDQ23 SDQ24 SDQ25 SDQ27 SDQ29 SDQ26
Function
Type
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I/O O O I/O O O I/O O O I/O O O
Reset State
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AB6 AC5 W1 SDQS0 SDQS0 # SDQM0 SDQS1 AB1 W1 R2 P2 AA2 SDQS1 # SDQM1 SDQS2 SDQS2 # SDQM2 SDQS3 SDQS3 # SDQM3
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SDQ30 SDQ31 H3 SVREF0 SVREF1 H4 Y5 SVREF2 AA8 SVREF3 H4 K1 J2 G1
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SDQ28
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BALL#
V2 V1 J4 N3 W4 R4 U4 M4 Y4 N5 V4 M3 AA3 P4 L3 W3 P3 Y3 R3 K3 L4 K4 T3 T4 U3
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Pin Name
SCK# SCK SCKE1 SCKE0 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14
Function
Type
O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O P P
Reset State
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AA7 SZQ NC AA6 SRST N8/P8/R8 M8/N9/P9 M9/N10/P10 PA0 D5 ERXD3 SPI1_CS0 PA1 ERXD2 E5
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SWE SCAS SCS0 SRAS SCS1 V3 AA4 AA5 J3 SDOT0 SDOT1 VDD_DLL GND_DLL 0/1 2 3 4 0/1 2 3
16
UART2_RTS
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SBA0 SBA2 SBA1 I/O I/O SPI1_CLK
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BALL# Pin Name
UART2_CTS PA2 D6 ERXD1 SPI1_MOSI UART2_TX PA3 E6 ERXD0 SPI1_MISO UART2_RX PA4 D7 ETXD3
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Function
4 0/1 2 3 0/1 2 3 4 0/1 2 3 4
Type
Reset State
I/O
SPI1_CS1
PA5 E7 ETXD2
SPI3_CS0
PA6 D8 ETXD1 PA7
E8
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D9 ERXCK PA9 2
E9
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PA11 E10 EMDC PA12 D11 EMDIO PA13 E11 ETXEN
UART1_RST
UART1_CTS
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2
SPI3_CLK
ETXD0 PA8
SPI3_MOSI
SPI3_MISO
ERXERR PA10
SPI3_CS1
ERXDV
UART1_TX
UART1_RX
UART6_TX
UART6_RX
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I/O 0/1 2 3 I/O 0/1 3 I/O 0/1 2 3 I/O 0/1 3 I/O 0/1 2 3 I/O 0/1 2 4 0/1 2 4 0/1 2 3 4 0/1 2 3 4
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I/O I/O I/O I/O I/O

BALL# Pin Name
PA14 D12 ETXCK UART7_TX UART1_DTR PA15 E12 ECRS UART7_RX UART1_DSR PA16 D13 ECOL CAN_TX UART1_DCD PA17 C13 ETXERR CAN_RX UART1_RING A15 B15 A14 PB0 PB1 PB2 PB3 NC TWI0_SCK
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Function
0/1 2 3 4 2 3 4 0/1 2 3 0/1
Type
I/O
Reset State
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0/1 2 3 B14 IR_TX EINT16 PB4 PB5 IR_RX 5 A13 0/1 2 0/1 2 3 0/1 2 3 0/1 2 3 0/1 2 3 0/1
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B13 PB6 A12 PB7 B12 PB8 A11 C12 I2S_DO0 AC97_DO PB9
AC97_MCLK I2S_BCLK
AC97_BCLK I2S_LRCK
AC97_SYNC
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0/1 2 0/1 2 0/1 2 I/O I/O I/O I/O TWI0_SDA PWM0 I/O I/O I2S_MCLK I/O I/O I/O I/O
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4 0/1 2 3 I/O 4
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I/O
I/O

BALL# Pin Name
I2S_DO1 C11 C10 PB10 I2S_DO2 PB11 I2S_DO3 PB12 C9 I2S_DI AC97_DI NC PB13 B11 SPI2_CS1 NC PB14 A10 SPI2_CS0 JTAG_MS0 PB15 B10 SPI2_CLK PB16 JTAG_CK0
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Function
2 0/1 1 0/1 1 0/1 2 3 4 0/1 2 4
Type
Reset State
I/O I/O
A9
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B9 SPI2_MOSO JTAG_DI0 PB18 PB19 PB20 PB21 PB22 2 3 A8 B8 C8 C7 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 3 0/1 2 3 0/1 2 3
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A7
B7
M23
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2 3 0/1 2 3 I/O SPI2_MOSI JTAG_DO0 PB17 0/1 I/O I/O I/O I/O I/O I/O TWI1_SCK TWI1_SDA TWI2_SCK TWI2_SDA UART0_TX
IR1_TX
PB23
UART0_RX
IR1_RX
PC0
NWE#
SPI0_MOSI
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I/O 0/1 2 3 I/O 0/1 I/O I/O I/O
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I/O

BALL# Pin Name
PC1 M22 NALE SPI0_MISO PC2 L23 NCLE SPI0_CLK PC3 L22 NCE1 SDC1_CMD K23 PC4 NCE0 PC5 K22 NRD SDC1_CLK PC6 J23 NRB0 SDC2_CMD PC7 NRB1 PC8
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Function
0/1 2 3 0/1 2 3 0/1 2 3 0/1 1 0/1 1 2
Type
I/O
Reset State
I/O
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3 0/1 2 3 I/O SDC2_CLK ND0 PC9 0/1 2 3 I/O SDC2_D0 ND1 0/1 2 3 I/O SDC2_D1 PC10 ND2 0/1 2 3 I/O SDC2_D2 PC11 ND3 0/1 2 3 0/1 2 3 0/1 2 3 0/1 2 3
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J22
H23
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G22 SDC2_D3 PC12 ND4 H21 SDC1_D0 PC13 ND5 H20 SDC1_D1 PC14 G21 ND6 SDC1_D2
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H22 G23
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I/O I/O Pull Up (default) 0/1 2 I/O Pull Up (default) Pull Up (default) I/O I/O I/O I/O
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I/O Pull Up (default)

BALL# Pin Name
PC15 G20 ND7 SDC1_D3 M21 F23 F22 PC16 NWP PC17 NCE2 PC18 NCE3 PC19 L21 NCE4 SPI2_CS0 EINT12 PC20 K21 NCE5 SPI2_CLK EINT13 PC21 NCE6
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Function
0/1 2 3 0/1 1 0/1 1 0/1 1 0/1 1 2
Type
I/O
Reset State
I/O I/O I/O I/O
Pull Down (default) Pull Up Pull Up
J21
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J20 NCE7 1 SPI2_MISO EINT15 PC23 PC24 PD0 2 5 G19 F21 0/1 2 0/1 SPI0_CS0 NDQS
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5 0/1 1 2 I/O SPI2_MOSI EINT14 PC22 5 0/1 I/O I/O I/O I/O Pull Up (default) 0/1 2 3 0/1 2 3 0/1 2 3 0/1 2 3
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AB15 PD1 AC15 LCD0_D1 PD2 AB14 LCD0_D2 PD3 AC14 LCD0_D3
LCD0_D0
LVDS0_VP0
LVDS0_VN0
LVDS0_VP1
LVDS0_VN1
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5 0/1 1 2 I/O I/O I/O I/O
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(default) (default)

BALL# Pin Name
PD4 AB13 LCD0_D4
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Function
0/1 2 3 0/1 2 3 0/1 2 3 0/1 2 3
Type
I/O
Reset State
LVDS0_VP2
PD5 AC13 LCD0_D5
I/O
LVDS0_VN2
PD6 AB12 LCD0_D6
LVDS0_VPC
PD7 AC12 LCD0_D7
LVDS0_VNC
PD8 AB11 LCD0_D8
LVDS0_VP3
PD9 AC11 LCD0_D9 PD10
LVDS0_VN3
Y15 LCD0_D10 PD11
LVDS1_VP0
AA15 LCD0_D11 PD12
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2
LVDS1_VN0
LCD0_D12 PD13
Y14
LVDS1_VP1
LCD0_D13 PD14
AA14
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Y13 PD15 AA13 PD16 Y12 AA12 PD17
LVDS1_VN1
LCD0_D14
LVDS1_VP2
LCD0_D15
LVDS1_VN2
LCD0_D16
LVDS1_VPC
LCD0_D17
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2 3 0/1 2 3 I/O 0/1 3 I/O 0/1 2 3 I/O 0/1 2 3 0/1 2 3 0/1 2 3 0/1 2 3 0/1 2
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I/O 0/1 2 3 I/O 0/1 I/O I/O I/O I/O I/O I/O
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I/O

BALL# Pin Name
LVDS1_VNC
PD18 Y11 LCD0_D18
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Function
3 0/1 2 3 2 3 0/1 2 3 0/1 2 3 0/1
Type
Reset State
I/O
LVDS1_VP3
PD19 AA11 LCD0_D19
LVDS1_VN3
PD20 Y10 LCD0_D20
CSI1_MCLK
PD21 AA10 LCD0_D21
SMC_VPPEN
PD22 AB10 LCD0_D22
SMC_VPPPP
PD23 AC10
Y9
SMC_VCCEN
PD25 AA9
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0/1 2 3 2 3 2 3 0/1 2 3 0/1 2 3 0/1 2 3 0/1
23
AB9
LCD0_HSYNC SMC_SLK
PD27
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AC9 PE0 E23 TS0_CLK PE1 E22 TS0_ERR CSI0_CK PE2 D23 D22 PE3
LCD0_VSYNC SMC_SDA
CSI0_HSYNC
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0/1 2 3 2 3 I/O
LCD0_D23 SMC_DET
PD24
LCD0_CLK
LCD0_DE
PD26
SMC_RST
CSI0_PCK
TS0_SYNC
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I/O 0/1 2 3 I/O 0/1 I/O I/O 0/1 I/O 0/1 I/O I/O I/O I/O I/O
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I/O
I/O

BALL# Pin Name
TS0_DVLD CSI0_VSYNC PE4 C23 TS0_D0 CSI0_D0 PE5 C22 TS0_D1 CSI0_D1 PE6 B23 TS0_D2 CSI0_D2 PE7 B22 TS0_D3 CSI0_D3 PE8 A23 TS0_D4 CSI0_D4 PE9 TS0_D5 PE10
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Function
2 3 0/1 2 0/1 2 3 0/1 2 3 3
Type
Reset State
I/O
A22
B21
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CSI0_D6 PE11 TS0_D7 PF0 3 0/1 2 3 A21 CSI0_D7 0/1 2 4 M20 SDC0_D1 PF1 JTAG_MS1 SDC0_D0 PF2
Co
M19 L20 PF3 L19 PF4 K20 SDC0_D3
de
3 0/1 2 3 I/O CSI0_D5 TS0_D6 0/1 2 I/O I/O I/O 0/1 2 4 0/1 2 4 0/1 2 4 0/1 2 4
24
JTAG_DI1
SDC0_CLK
UART0_TX
SDC0_CMD JTAG_DO1
UART0_RX
nti
0/1 2 3 I/O 0/1 2 I/O I/O I/O I/O I/O
al
I/O I/O

BALL# Pin Name
PF5 K19 SDC0_D2 JTAG_CK1 PG0 F20
A10
Function
0/1 2 4 0/1 2 3 4 0/1 2 3 4 2 3 4 2 3 4 2 3 4 5 2 3 4 5 2 3 4 5 0/1 2 3 4 5 0/1 2
25
Type
I/O
Reset State
I/O
CSI1_PCLK SDC1_CMD
PG1
CSI1_MLCK SDC1_CLK
PG2
E20
TS1_SYNC CSI1_HSYNC SDC1_D0

PG3
D21
CSI1_VSYNC SDC1_D1
PG4
D20
nfi
SDC1_D2 CSI0_D8
PG5 0/1
C21
Co
PG6
E19
C20
D19
de
TS1_DVLD
0/1 I/O
TS1_D0
CSI1_D0
TS1_D1
CSI1_D1 CSI0_D9 TS1_D2
SDC1_D3
CSI1_D2
UART3_TX CSI0_D10
PG7
TS1_D3
CSI1_D3
UART3_RX CSI0_D11
PG8
TS1_D4
nti
0/1 I/O 0/1 I/O I/O 0/1 I/O I/O I/O
E21
TS1_ERR
al
I/O
TS1_CLK

BALL# Pin Name
CSI1_D4 UART3_RTS CSI0_D12
PG9
A10
Function
3 4 5 0/1 2 3 4 5 0/1 2 3 4 5 2 3 4 5 2 3 4 6 7 2 3 4 6 7 0/1 2 3 4 6 7 0/1 2 3 4 6
26
Type
Reset State
I/O
C19
CSI1_D5 UART3_CTS CSI0_D13

PG10
TS1_D6
D18
CSI1_D6 UART4_TX CSI0_D14

PG11
TS1_D7
C18
CSI1_D7 UART4_RX CSI0_D15

PH0
A6
nfi
EINT0
PH1
B6
Co
CSI1_D1
PH2 C6
UART3_RTS EINT2
PH3
A5
UART3_CTS EINT3
de
0/1 I/O
LCD1_D0 ATAA0
UART3_TX CSI1_D0
LCD1_D1 ATAA1 EINT1
UART3_RX
LCD1_D2 ATAA2
CSI1_D2
LCD1_D3 ATAIRQ
nti
0/1 I/O 0/1 I/O I/O I/O
al
I/O
TS1_D5

BALL# Pin Name
CSI1_D3
PH4 LCD1_D4 B5 ATAD0 UART4_TX
A10
Function
7 0/1 1 2 3
Type
Reset State
I/O
EINT4 CSI1_D4
PH5 LCD1_D5 C5 ATAD1 UART4_RX 0/1 2 3 4
EINT5 CSI1_D5
PH6 LCD1_D6 ATAD2 A4 UART5_TX MS_BS
nfi
ATAD3 3 B4 UART5_RX 4
Co
ATAD4 C4 KP_IN0
D4
de
4 5
EINT6
PH7
CSI1_D6
LCD1_D7
MS_CLK EINT7
PH8
CSI1_D7
LCD1_D8
MS_D0 EINT8
PH9
CSI1_D8
LCD1_D9 ATAD5 KP_IN1
MS_D1 EINT9 CSI1_D9
nti
6 7 0/1 2 3 I/O 6 7 0/1 2 I/O 5 6 7 0/1 2 3 4 5 6 7 0/1 2 3 4 5 6 7
27
al
I/O I/O I/O

BALL# Pin Name
PH10 LCD1_D10 ATAD6 A3 KP_IN2
A10
Function
0/1 2 3 4 6 7 0/1 2 3 4 5
Type
I/O
Reset State
EINT10 CSI1_D10
PH11 LCD1_D11 ATAD7 B3 KP_IN3
MS_D3 EINT11 CSI1_D11

PH12 LCD1_D12 ATAD8 PS2_SCK1
C3
nfi
LCD1_D13 ATAD9 PS2_SDA1 2 3 A2 4
Co
ATAD10 B2
SMC_VPPEN EINT14
PH15
A1
SMC_VPPPP EINT15
de
2 3 4
EINT12
PH13
CSI1_D12
SMC_RST EINT13
PH14
CSI1_D13
LCD1_D14
PS2_KP_IN4
CSI1_D14
LCD1_D15 ATAD11 KP_IN5
nti
5 6 7 0/1 I/O 6 7 0/1 I/O 5 6 7 0/1 2 3 4 5 6 7 0/1 2 3 4 5 6
28
al
I/O I/O I/O
MS_D2

BALL# Pin Name
CSI1_D15
PH16 LCD1_D16 ATAD12 B1 KP_IN6
A10
Function
7 0/1 2 3 5 6 7 0/1 2 3 4
Type
Reset State
I/O
SMC_DET EINT16 CSI1_D16

PH17 LCD1_D17 ATAD13 C1 KP_IN7
SMC_VCCEN EINT17 CSI1_D17

PH18 LCD1_D18 ATAD14 KP_OUT0
C2
nfi
PH19 0/1 2 3 LCD1_D19 ATAD15 KP_OUT1 D1 4
Co
PH20 D2 ATAOE CAN_TX
D3
de
2 3 4
SMC_SLK EINT18 CSI1_D18
SMC_SDA EINT19 CSI1_D19
LCD1_D20
EINT20
PH21
CSI1_D20
LCD1_D21 CAN_RX
ATADREQ
EINT21 CSI1_D21
nti
4 5 6 7 0/1 I/O 5 6 7 I/O 5 6 7 0/1 2 3 4 6 7 0/1 2 3 4 6 7
29
al
I/O I/O I/O

BALL# Pin Name
PH22 LCD1_D22 E2 ATADACK KP_OUT2
A10
Function
0/1 2 3 4 7 0/1 2 3 4 5 5
Type
I/O
Reset State
SDC1_CMD
PH23 LCD1_D23 E3 ATACS0 KP_OUT3
SDC1_CLK CSI1_D23
PH24
LCD1_CLK
E3 ATACS1 KP_OUT4
E4
nfi
SDC1_D1
PH26 5 7 2
CSI1_FIELD
LCD1_HSYNC
ATAIORDY KP_OUT6
F3
Co
PH27 F4 ATAIOW KP_OUT7 A20 B20 A19 PI0 PI1 NC PI2 NC
CSI1_HSYNC
LCD1_VSYNC
CSI1_VSYNC
de
SDC1_D0
PH25 5 7 2
CSI1_PCLK LCD1_DE
KP_OUT5
ATAIORDY
SDC1_D2
SDC1_D3
nti
7 0/1 2 3 I/O 4 0/1 3 I/O 4 0/1 3 I/O 4 5 7 0/1 2 3 4 5 7 0/1 2 0/1 2 0/1
30
al
I/O I/O I/O I/O I/O
CSI1_D22

BALL# Pin Name
NC B19 A18 B18 A17 B17 A16 B16 PI3 PWM1 PI4
A10
Function
2 0/1 2 0/1 2 0/1 2 0/1 2 0/1 2 2 2 2 3 6 2 3 6 2 3 6 2 3 6 0/1 2 3 4 6 0/1 2 3 4 6
31
Type
Reset State
I/O I/O
PI5
SDC3_CLK
PI6
SDC3_D0
PI7
SDC3_D1
PI8
SDC3_D2
PI9
SDC3_D3
PI10
C17
D17
nfi
EINT23
PI12 0/1 C16
Co
EINT25 PI14
A18
D16
B18
de
SPI0_CS0 EINT22
PI11
UART5_TX
SPI0_CLK UART5_RX
SPI0_MOSI EINT2 PI13
UART6_TX
SPI0_MISO
UART6_RX
SPI0_CS1 TCLKIN0 EINT26 PI15
PS2_SCK1
SPI1_CS1 PS2_SDA1 TCLKIN1 EINT27
nti
I/O I/O I/O 0/1 0/1 0/1 I/O 0/1 I/O I/O 0/1 I/O I/O I/O
al
I/O I/O
SDC3_CMD

BALL# Pin Name
PI16
A17
A10
Function
0/1 2 3 6 2 3 6 0/1 2 3 6 2 3 6 2 3 6 2 3 6 0/1
Type
I/O
Reset State
SPI1_CS0 UART2_RTS EINT28 PI17 SPI1_CLK UART2_CTS EINT29 PI18 SPI1_MOSI UART2_TX EINT30 PI19 SPI1_MISO UART2_RX EINT31 PI20 PS2_SCK0 HSCL PI21
B17
A16
B16
E14
nfi
UART7_RX HSDA NC
GND T9 W8 UBOOT_SEL JTAG_SEL TEST T10 0/1 0
E13
de
0/1 I/O
UART7_TX
PS2_SDA0
Co
F5 NMI# C14 RESET# N20 N21 P20 P21
H16
DM0 DP0 DP1 DM1
nti
0/1 I/O 0/1 I/O I I I/O I/O A A IO IO PWR GND PWR GND PWR GND
32
0 0 0/1 0/1 0 0 0 0 0/1 0/1
L16 L14 L15 L13
UVCC_C UGND_C UVCC_T UGND_T
al
I/O pull-up pull-up pull-up pull-down -
I/O

BALL#
K16 K14 R20 R21 Y22 AA22 Y23 AA23 AC23 AC22 Y21 Y20 AA21 AC21 AC20 W20 V20 T19 W21 AB21 AB20 U19 W19 Y19 V19
A10
Pin Name
ULVDD ULGND DM2 DP2
XP_TP XN_TP YP_TP YN_TP
Function
Type
PWR GND IO IO
Reset State
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MIC1OUTN MIC1OUTP FMINR FMINL VMIC MICIN2 MICIN1 VRA1 VRA2 VRP AVCC
nti
0 0 0 0 0 0 0 0 0 0 0 0 0
33
de
LINEINR LINEINL AGND HPR HPL HPGND HPVCC HPL HPCOMFB
LRADC0 LRADC1 TVOUT0 TVOUT1 TVOUT2 TVOUT3 AI AI AO AO AO AO PWR GND VCC33_TVOUT GND33_TVOUT
Co
AB22 AC16 AB16 AC17 AB17 W15 W18 AC18 AB18 AA17 Y17 W16
nfi
AA20 AC19 Y19 AB23
NC NC NC NC NC
al
AI AI AI -
AI

BALL#
Y18 W17 AA18 AA16 Y16 V23 V22 U23 U22 T23 T22 W23 W22 T13 P13/R13/P14 R23 R22 P22 P23 R14/T14 T20 T21 U21 U20
A10
Pin Name
NC NC NC NC NC TX0P_HDMI TX0N_HDMI TX1P_HDMI TX1N_HDMI TX2P_HDMI TX2N_HDMI TXCP_HDMI TXCN_HDMI VP_HMDI GND_HDMI SCL_HDMI SDA_HDMI HPD_HDMI CEC_HDMI NC NC NC NC NC NC NC NC
Function
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Type
Reset State
P19/R19
M16/M15 N15/N16 F1 M14/N13 F2
Co
K8 N23 N22 P16 P15 R16/T16/R15/T15
nfi
V21
CLK32K_OUT RTC_VDD CLK24M_IN
de
NC NC
CLK32K_IN 0 0 0 0 0 0 0 0 GND A A PWR A A PWR CLK24M_OUT
NC
PLLVP25
PLLGND
H8/H9/H10 J8/J9/J10 J14/H15

34
VCC(8)
nti
0 PWR -
al

BALL#
N19 H19/J19 G5/H5/L5/M5/ R5/T5/ W5/W6/W7/Y7/ VCC_ DRAM (10) 0 PWR -
A10
Pull Up/Down
-
Pin Name
VCC_CARD VCC_NAND(2)
Function
0 0
Type
PWR PWR
Reset State
-
Buffer Strength (mA)

-
J5/k5/N5/P5/ U5/V5/Y7/ Y8/G3/G4 L8/L9/K9/K10/ T8/R9/R10/ K15/J15/J16 J12/J13/H11/ H12/H13/H14 H11/H12/H13/H14 J12/J14 T8/R9/R10 L8/L9/K9/K10 K15/J15/J16 L10/L11/L12/ K11/K12/K13/ J11/M10/M11/ M12/M13/N11/N12/ P11/P12/R11/R12/ T11/T12 W12/W13/W14 W9/W10/W11 F19 E18 VDD26 VDDCPU(6) VDD(10) GND_DRAM (10) 0
nti
0 PWR 0 GND 0 PWR GND 0
35
VDD_INT(10)
nfi
GND(19) VCC_ LVDS (3) GND_LVDS (3) VCC_CSI0 VCC_CSI1
de
-
Co
al
GND -

5.2.
A10
Multiplexing Characteristics
Table 5-2. provides a description of the A10 multiplexing on the FBG441 package. Table 5-2 Multiplexing Characteristics
Multi2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 ERXD3 ERXD2 ERXD1 ERXD0 ETXD3 ETXD2 ETXD1 ETXD0 ERXCK
Multi3 SPI1_CS0 SPI1_CLK
Multi4
UART2_RTS
SPI1_MOSI
SPI1_MISO SPI1_CS1 SPI3_CS0
ERXERR ERXDV EMDC
PA12
PA13 PA14
Co
PA16 PA17 ECOL ETXERR
PA15
nfi
EMDIO UART6_TX ETXEN UART6_RX UART7_TX ETXCK ECRS UART7_RX CAN_TX CAN_RX
36
de
SPI3_CLK SPI3_MOSI SPI3_MISO SPI3_CS1 UART1_TX UART1_RX UART1_RTS UART1_CTS UART1_DTR UART1_DSR UART1_DCD UART1_RING Port A(PA) Multiplex Function Select Table
nti
UART2_CTS UART2_TX UART2_RX
al
Multi5 Multi6
Port A(PA)
Multiplex Function Select Multi 7

Port B(PB) Multi2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 TWI0_SCK TWI0_SDA Multi3 Multiplex Function Select Multi4 Multi5 Multi6
A10
Multi7
IR0_TX IR0_RX I2S_MCLK I2S_BCLK I2S_LRCK I2S_DO0 I2S_DO1 I2S_DO2 I2S_DO3 I2S_DI SPI2_CS1 SPI2_CS0 AC97_MCLK AC97_BCLK AC97_SYNC AC97_DO
NC
Co
TWI2_SDA PB22 UART0_TX PB23 UART0_RX
nfi
SPI2_MOSI JTAG_DO0 JTAG_DI0 SPI2_MISO TWI1_SCK TWI1_SDA TWI2_SCK IR1_TX IR1_RX Port B(PB) Multiplex Function Select Table
37
SPI2_CLK
de
AC97_DI NC NC JTAG_MS0 JTAG_CK0
nti
al
PWM0

Port C(PC) Multi2 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 NWE# NALE NCLE NCE1 NCE0 NRE# NRB0 NRB1 NDQ0 NDQ1 NDQ2 NDQ3 NDQ4 NDQ5 NDQ6 NDQ7 NWP SDC2_CMD SDC2_CLK SDC2_D0 SDC2_D1 SDC2_D2 SDC2_D3 Multi3 SPI0_MOSI SPI0_MISO SPI0_CLK Multiplex Function Select Multi4 Multi5 Multi6
A10
Multi7
Co
NCE6 NCE7 PC23
nfi
NCE2 NCE3 NCE4 NCE5 SPI2_CS0 SPI2_CLK SPI2_MOSI SPI2_MISO SPI0_CS0 Port C(PC) Multiplex Function Select Table
38
de
nti
al

Port D(PD) Multi2 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 LCD0_D0 LCD0_D1 LCD0_D2 LCD0_D3 LCD0_D4 LCD0_D5 LCD0_D6 LCD0_D7 LCD0_D8 LCD0_D9 LCD0_D10 LCD0_D11 Multi3 LVDS0_VP0 LVDS0_VN0 LVDS0_VP1 Multiplex Function Select Multi4 Multi5 Multi6
A10
Multi7
LVDS0_VP2 LVDS0_VN2 LVDS0_VPC
LVDS0_VNC LVDS0_VP3
LVDS0_VN3 LVDS1_VP0
LCD0_D12 LCD0_D13 LCD0_D14 LCD0_D15 LCD0_D16 LCD0_D17 LCD0_D18 LCD0_D19 LCD0_D20 LCD0_D21 LCD0_D22 LCD0_D22
Co
LCD0_CLK LCD0_DE PD25 PD26 PD27 LCD0_HSYNC LCD0_VSYNC
nfi
LVDS1_VPC LVDS1_VNC LVDS1_VP3 LVDS1_VN3 CSI1_MCLK SMC_VPPEN SMC_VPPPP SMC_DET SMC_VCCEN SMC_RST SMC_SLK SMC_SDA Port D(PD) Multiplex Function Select Table
39
de
LVDS1_VP1 LVDS1_VN1 LVDS1_VP2 LVDS1_VN2
LVDS1_VN0
nti
al
LVDS0_VN1

Port E(PE) Multi2 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 TS0_CLK TS0_ERR TS0_SYNC TS0_DVLD TS0_D0 TS0_D1 TS0_D2 TS0_D3 TS0_D4 TS0_D5 TS0_D6 TS0_D7 Multi3 CSI0_PCLK CSI0_MCLK CSI0_HSYNC Multiplex Function Select Multi4 Multi5 Multi6
A10
Multi7
CSI0_D0 CSI0_D1 CSI0_D2 CSI0_D3 CSI0_D4 CSI0_D5 CSI0_D6 CSI0_D7
TS0_CLK TS0_ERR
TS0_SYNC
TS0_DVLD TS0_D0 TS0_D1 TS0_D2 TS0_D3 TS0_D4 TS0_D5 TS0_D6 TS0_D7
Co
TS0_CLK TS0_ERR PE25 PE26 TS0_SYNC PE27 PE28 PE29 TS0_DVLD TS0_D0 TS0_D1
nfi
CSI0_D0 CSI0_D1 CSI0_D2 CSI0_D3 CSI0_D4 CSI0_D5 CSI0_D6 CSI0_D7 CSI0_PCLK CSI0_MCLK CSI0_HSYNC CSI0_VSYNC CSI0_D0 CSI0_D1
40
de
CSI0_PCLK CSI0_MCLK CSI0_HSYNC CSI0_VSYNC
nti
al
CSI0_VSYNC

PE30 PE31 TS0_D2 TS0_D3 CSI0_D2 CSI0_D3 Port E(PE) Multiplex Function Select Table
A10
Port F(PF) Multi2 PF0 PF1 PF2 PF3 PF4 PF5 SDC0_D1 SDC0_D0 SDC0_CLK SDC0_CMD SDC0_D3 SDC0_D2 Multi3
Multiplex Function Select Multi4 JTAG_MS1 JTAG_DI1 Multi5 Multi6 Multi7
UART0_TX JTAG_DO1
Port F(PF) Multiplex Function Select Table
Port G(PG) Multi2 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9
de
Multi3 Multi4 CSI1_PCLK SDC1_CMD SDC1_CLK SDC1_D0 SDC1_D1 CSI1_MLCK CSI1_HSYNC CSI1_VSYNC CSI1_D0 CSI1_D1 CSI1_D2 CSI1_D3 CSI1_D4 CSI1_D5 SDC1_D2 SDC1_D3 UART3_TX UART3_RX UART3_RTS UART3_CTS
41
nti
UART0_RX JTAG_CK1 Multiplex Function Select Multi5 Multi6 Multi7 CSI0_D8 CSI0_D9 CSI0_D10 CSI0_D11 CSI0_D12 CSI0_D13
TS1_CLK TS1_ERR
Co
TS1_D4 TS1_D5
nfi
TS1_DVLD TS1_D0 TS1_D1 TS1_D2 TS1_D3
TS1_SYNC
Port G(PG) Multiplex Function Select Table
al

Port H (PH) Multi2 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 PH9 PH10 PH11 PH12 PH13 PH14 PH15 PH16 PH17 PH18 PH19 PH20 PH21 PH22 PH23 PH25 PH26 PH27 LCD1_D0 LCD1_D1 LCD1_D2 LCD1_D3 LCD1_D4 LCD1_D5 LCD1_D6 LCD1_D7 LCD1_D8 LCD1_D9 LCD1_D10 LCD1_D11 LCD1_D12 LCD1_D13 LCD1_D14 LCD1_D15 LCD1_D16 LCD1_D17 LCD1_D18 LCD1_D19 LCD1_D20 LCD1_D21 LCD1_D22 LCD1_D23 Multi3 ATAA0 ATAA1 ATAA2 ATAIRQ ATAD0 ATAD1 ATAD2 ATAD3 ATAD4 ATAD5 ATAD6 ATAD7 ATAD8 ATAD9 Multi4 UART3_TX UART3_RX UART3_RTS UART3_CTS UART4_TX UART4_RX UART5_TX Multi5 Multi6 EINT0 EINT1 EINT2 EINT3 EINT4 EINT5 EINT6 EINT7 EINT8 EINT9 Multiplex Function Select
A10
Multi7 CSI1_D0 CSI1_D1 CSI1_D2 CSI1_D3 CSI1_D4 CSI1_D5 CSI1_D6 CSI1_D7 CSI1_D8 CSI1_D9 CSI1_D10 CSI1_D11 CSI1_D12 CSI1_D13 CSI1_D14 CSI1_D15 CSI1_D16 CSI1_D17 CSI1_D18 CSI1_D19 CSI1_D20 CSI1_D21 CSI1_D22 CSI1_D23 CSI1_PCLK CSI1_FIELD CSI1_HSYNC
de
KP_IN3 PS2_SCK1 PS2_SDA1 KP_IN4 KP_IN5 KP_IN6 KP_IN7 SMC_RST ATAD10 ATAD11 ATAD12 ATAD13 ATAD14 ATAD15 SMC_DET KP_OUT0 KP_OUT1 CAN_TX SMC_SDA ATAOE ATADREQ ATADACK ATACS0 ATACS1 ATAIORDY ATAIOR CAN_RX KP_OUT2 KP_OUT3 KP_OUT4 KP_OUT5 KP_OUT6 SDC1_D0 SDC1_D1 SDC1_D2
42
nfi
LCD1_CLK LCD1_DE LCD1_HSYNC
Co
Port H(PH) Multiplex Function Select Table
nti
UART5_RX KP_IN0 KP_IN1 KP_IN2 EINT10 EINT11 EINT12 EINT13 EINT14 EINT15 EINT16 EINT17 EINT18 EINT19 EINT20 EINT21 SDC1_CMD SDC1_CLK SMC_VPPEN SMC_VPPPP SMC_VCCEN SMC_SLK
al

Port I(PI) Multi2 PI0 PI1 PI2 PI3 PI4 PI5 PI6 PI7 PI18 PI19 PI10 PI11 PI12 NC NC NC Multi3 Multiplex Function Select Multi4 Multi5 Multi6
A10
Multi7
SDC3_CMD SDC3_CLK SDC3_D0 SDC3_D1 SDC3_D2 SDC3_D3 SPI0_CS0 SPI0_CLK
UART5_TX
SPI0_MOSI
de
UART6_TX
43
UART5_RX
Port I(PI) Multiplex Function Select Table
5.3.
Power and Miscellaneous Signals
Co
nfi
-I = Input -O = Output -Z = High-impedance -A = Analog - PWR = Power - GND = Ground 4. Pin #: Associated ball(s) number
Many signals are available on multiple pins according to the software configuration of the multiplexing options. 1. Signal Name: The signal name 2. Description: Description of the signal 3. Type: type = Pin type for this specific function:
nti
al
EINT22 EINT23 EINT24
PWM1

5.3.1.
A10
Power Domain Signal Description

Table 5-3 Power Domain Signal Description
Signal Name TV-OUT DAC Power

TV-VCC TV-GND HPVCC HPVCC_IN HPGND VMIC TV-OUT Power Supply TV-OUT Ground
Description
Pin Name
TV-VCC TV-GND HPVCC
Ball#
R14 N12 Y14
Audio DAC Power

Audio output DAC Power Supply Audio output DAC Power Supply Audio output DAC Ground Microphone ADC Power Supply
Audio ADC Power USB Power

UVCC0 ULVDD0 UVCC_C UVCC_T ULVDD1 UGND0 ULGND0 UGND_C UGND_T ULGND1 USB0 Digital Power Supply
nti
VMIC UVCC0 ULVDD0 UVCC_C UVCC_T UGND0 ULGND0 UGND_C UGND_T ULGND1 RTC_VDD PLL_VDD PLL_GND ULVDD1 VDD(13) GND(13)
44
USB0 PHY Analog Power Supply USB1 PHY Analog Power Supply USB1/2 Digital Power Supply USB0 PHY Analog Ground USB0 Digital Ground
USB2 PHY Analog Power Supply
de
USB1 PHY Analog Ground USB2 PHY Analog Ground USB1/2 Digital Ground RTC Power Supply PLL Power Supply
RTC Power
RTC_VDD PLL_VDD PLL_GND
nfi
PLL Ground Core Chip Power Supply Core Chip Ground
PLL Power
Core Power
Co
VDD GND
al
HPVCC_IN HPGND W14 N11 V17 P17 T16 P16 R16 U16 K12 L13 L12 M13 M12 V13 V20 N13 H8\J8\ K8\K9\ K10\J10\ H10\H9\ J9\M8\ M9\N8\ N9 L8\L9\ L10\M10\ N10\L11\ K11\J11\ H11\J12\ J13\H13\

Signal Name Description Pin Name
A10
Ball#
H12
IO Power
VCC
IO Power Supply
nti
Card VCC AVCC(1) AGND(1)
45
Card Power
Card VCC Card Power Supply
NAND Power
NAND_VCC NAND Flash Power Supply
de
DRAM Power
DRAM_VCC
DRAM Power Supply
nfi
DRAM Ground LVDS Power Supply LVDS Ground Analog Power Supply Analog Ground
DRAM_GND
LVDS Power
LVDS_VCC
Co
Analog Power
AVCC AGND
LVDS_GND
al
VCC(10) H7\J7 U12 NAND_VCC(2) DRAM_VCC(10) DRAM_GND(10) LVDS_VCC(1) LVDS_GND(1) P18 K13 Y19 M11
K7\L7\ P7\P8\
M7\N7\ P9\P10\
G10\G7
H16\G16\ G15\F16\ F15\E16\ E15\E14\ F14\E13 K15\K14\ J14\H14\ G14\G13\ G12\G11\ F12\F11

5.3.2.
A10
Miscellaneous Signal Description

Table 5-4 Miscellaneous Signal Description
Signal Name JTAG Interface

JTAG_SEL0 JTAG_SEL1 JTAG_MS0 JTAG_CK0 JTAG_DO0 JTAG_DI0 JTAG_MS1 JTAG_CK1 JTAG_DO1 JTAG_DI1 JTAG port Select bit0 JTAG port Select bit1 JTAG Mode Select JTAG Clock JTAG test DataOutput JTAG test Data Input JTAG Mode Select JTAG Clock JTAG test DataOutput JTAG test Data Input
Description
Type
I I
Pin Name
JTAG0# JTAG1# PB14
Ball#
R8 R9
JTAG Port 0
JTAG Port 1
nti
I I O I AI AO AI AO AI I I I A A A A
46
Clock
HOSCI HOSCO LOSCI LOSCO
Main 24MHz crystal Input for internal OSC 32K768Hz crystal Input for RTC
de
Main 24MHz crystal Output for internal OSC 32K768Hz crystal Output for RTC System Reset
Reset
RESET#
FIQ
NMI#
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External Fast Interrupt Request Boot Mode Select Test Pin(Pull down Internal default) Bias of the CPU connect a 200Kohm Resistor to ground =AVCC=3.0V =1.5V =0V
Boot Test
TEST
BOOT_SEL
Others
BIAS VRP
Co
VRA1 VRA2
al
I I PB15 O I PB16 PB17 PF0 PF5 PF3 PF11 HOSCI HOSCO LOSCI LOSCO RESET# NMI# BOOTS TEST BIAS VRP VRA1 VRA2
P11
R11 T11
U11 V11
V12 W11 Y12 W20 Y20 Y13 W13 T12 R12 P12 G6 Y18 W19 W18 V18

Signal Name Description Type Pin Name
A10
Ball#
E11\E12\ F13\H15\ J15\J16\ K16\L14\ L15\L16\ L17\L18\ L19\L20\
NC
Not Connect
nti
Parameter Min
-20 TBD TBD TBD 2.7 1.0 2.7 1.3 2.7 2.7 3.0 2.7 1.2 1.2
47
6.1.
Absolute Maximum Ratings
The absolute maximum ratings (shown in Table 6-1) define limitations for electrical and thermal stresses. These limits prevent permanent damage to the A10.
Symbol
TS II/O VESD VCC
nfi
Storage Temperature In/Out current for input and output ESD stress voltage DC Supply Voltage for I/O DC Supply Voltage for Analog Part DC Supply Voltage for DRAM Part DC Supply Voltage for USB PHY DC Supply Voltage for TV-OUT DAC DC Supply Voltage for Audio DAC DC Supply Voltage for PLL DC Supply Voltage for RTC DC Supply Voltage for LRADC
Note: Absolute maximum ratings are not operating ranges. Operation at absolute maximum ratings is not guaranteed. Table 6-1 Multiplexing Characteristics
de
HBM(human body model) CDM(charged device model)
6.
Electrical Characteristics
Co
VDD VCC_ANALOG VCC_DRAM VCC_USB VCC_TV VCC_HP VDD_PLL VDD_RTC VCC_LRADC
DC Supply Voltage for Internal Digital Logic
al
NC(27) NC
M14\M15\ M16\M17\ M18\N16\ N17\N18\ R15\U17\ U18\V16\ V19
Max
125 TBD TBD TBD 3.3 1.3 3.3 2.0 3.3 3.3 3.0 3.3 1.3 1.3
Unit
C mA VESD V V V V V V V V V V

6.2.
A10
Recommended Operating Conditions

All A10 modules are used under the operating Conditions contained in Table 6-2. Table 6-2 Recommended Operating Conditions
Symbol
Ta GND VCC VDD VCC_ANALOG VCC_DRAM VCC_USB VCC_TV VDD_RTC
Parameter
Operating Temperature[Commercial] Operating Temperature[Extended] Ground DC Supply Voltage for I/O DC Supply Voltage for Analog Part DC Supply Voltage for DRAM Part DC Supply Voltage for USB PHY DC Supply Voltage for RTC
Min
-25 -40 0
Typ
0
Max
+85 +85 0
Unit
C C V V V V
DC Supply Voltage for Internal Digital Logic
nti
TBD 3.3 TBD 3.3 TBD 1.25
DC Supply Voltage for TV-OUT DAC
6.3.
DC Electrical Characteristics
Table 6-3 summarized the DC electrical characteristics of A10.
Symbol
VIH VIL VHYS IIH IIL VOH VOL IOZ CIN COUT
de
Parameter
48
Table 6-3 DC Electrical Characteristics
High-level input voltage Low-level input voltage Hysteresis voltage
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High-level input current Low-level input current High-level output voltage Low-level output voltage Tri-State Output Leakage Current Input capacitance Output capacitance
Co
6.4.
-
Oscillator Electrical Characteristics
The A10 contains two oscillators: a 24.000 MHz oscillator and a 32.768kHz oscillator. Each oscillator requires a specific crystal. The A10 device operation requires the following two input clocks: The 32.768kHz frequency is used for low frequency operation. The 24.000MHz frequency is used to generate the main source clock of the A10 device.
al
TBD 3.3 TBD TBD 1.2V 3.0 1.5 TBD TBD TBD TBD TBD TBD TBD TBD
V V V
Min
Typ
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Max
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Unit
V V mV uA uA V V uA pF pF
TBD
TBD TBD TBD
TBD TBD TBD TBD TBD TBD

6.4.1.
A10
24MHz Oscillator Characteristics
The 24.0MHz crystal is connected between the HOSCI (amplifier input) and HOSCO (amplifier output). Table 6-4 lists the 24.MHz crystal specifications. Table 6-4 24MHz Oscillator Characteristics
Symbol
1/(tCPMAIN) tST Startup Time
Parameter
Crystal Oscillator Frequency Range Frequency Tolerance at 25 C Oscillation Mode Maximum change over temperature range
Min
Typ
24.000
Max
Unit
MHz ms ppm ppm uW pF pF % pF pF M
CL CL1,CL2 RS CM CSHUT RBIAS
Equivalent Load capacitance Series Resistance(ESR) Duty Cycle Motional capacitance Shunt capacitance Internal bias resistor
nti
30 50
PON
Drive level
Internal Load capacitance(CL1=CL2)
6.4.2.
32.768kHz Oscillator Characteristics
Symbol
tST
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Parameter
Crystal Oscillator Frequency Range Startup Time Frequency Tolerance at 25 C Oscillation Mode Maximum change over temperature range Drive level Equivalent Load capacitance Internal Load capacitance(CL1=CL2) Duty Cycle Series Resistance(ESR) Motional capacitance Shunt capacitance Internal bias resistor
49
The 32.768kHz crystal is connected between the LOSCI (amplifier input) and LOSCO (amplifier output). Table 6-5 lists the 32.768kHz crystal specifications. Table 6-5 32.768kHz Oscillator Characteristics
de
1/(tCPMAIN)
Co
PON CL RS CL1,CL2 CM CSHUT RBIAS
al
-50 +50 Fundamental -50 +50 50 70
Min
-50
Typ
32.768
Max
Unit
MHz ms
+50 +50 50
ppm ppm uW pF pF % pF pF M
Fundamental -50 30 50
70

6.5. 6.6.
A10
Power up/down and Reset Specifications This section includes specification for the following:
Power-up sequence Power-down sequence
6.6.1.
Power-up Sequence
The external voltage regulator and other power-on devices must provide the processor with a specific sequence of power and resets to ensure proper operation. Figure 6-x shows this sequence and is detailed in Table 6-x
6.6.2.
Power-down Sequence
The sequence indicated in Figure 6-x and detailed in Table 6-x is the required timing parameters for power-dow
The clock controller provides management for clock generation, division, distribution, synchronization and gating. It consists of 7PLLs, 24MHz crystal, an on-chip RC Oscillator and a 32768Hz low power crystal Oscillator. The 24MHz crystal Oscillator is mandatory and generates input clock source for PLLs and main digital blocks, while it is recommended to use low-power and accurate 32768Hz crystal Oscillator for RTC.
Co
50
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7.
Clock Controller
de
nti
al

7.1.
A10
Clock Tree Diagram
Co
51
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de
nti
al

Figure 2.Bus Clock Generation Part I
32KHZ OSC24M CPU-CLK PLL1 Divider 00:/1 01:/2 10:/3 11:/4 Divider 00:/1 01:/2 10:/4 11:/8 Divider 00:/2 01:/2 10:/4 11:/8
A10
AXI-CLK
AHB-CLK
APB0-CLK
PLL6/6 OSC24M PLL6 APB1-CLK CLK_OUT= CLK_IN/(M*N) M:1-32 N:1/2/4/8
32KHZ NAND-CLK MS-CLK SD0/1/2/3-CLK TS-CLK SS-CLK SPI0/1/2/3-CLK IR0/1-CLK CLK_OUT= CLK_IN/(M*N) M:1-16 N:1/2/4/8
OSC24M PLL6
PLL5
PLL6
PLL2
8X
32KHz OSC24M
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USB-CLK NC DE-BE0/1/FE0/1/MP-CLK CLK_OUT= CLK_IN/M M:1-16 VE-CLK/N N:1-8 LCD-CH0-CLK
USB-PLL
AHB-CLK
Co
PLL7 PLL5
PLL4
PLL3
de
IIS-CLK NC CLK_OUT= CLK_IN/*N N:1/2/4/8 IIS-CLK-OUT NC KEYPAD-CLK CLK_OUT= CLK_IN/(M*N) M:1-32 N:1/2/4/8 USB-CLK-OUT NC BE-CLK-OUT VE-CLK-OUT
PLL5
PATA-CLK CLK_OUT= CLK_IN/(M*N) M:1-32 N:1/2/4/8
nti
SPI0/1/2/3-CLK-OUT IR0/1-CLK-OUT PATA-CLK-OUT KEYPAD-CLK-OUT DE-BE0/1/FE0/1/MP-CLK-OUT IEP-CLK-OUT IEP-CLK LCD-CH0-CLK-OUT
NAND-CLK-OUT MS-CLK-OUT SD0/1/2/3-CLK-OUT TS-CLK-OUT SS-CLK-OUT
PLL3x1
PLL7x1 PLL3x2 PLL7x2
52
al
APB1-CLK-OUT
TWI/UART/PS2/CAN/SC R

Figure 3.Bus Clock Generation Part II
PLL3x1 PLL7x1 PLL3x2 PLL7x2 PLL3x1 PLL4 PLL5 PLL6
PLL2
A10
LCD0/1-CH1-CLK2 CLK_OUT= CLK_IN/M M:1-16
LCD0/1-CH1-CLK2
LCD0/1-CH1-CLK1 CLK_OUT = CLK_IN/M M:1/2
LCD0/1-CH1-CLK1-OUT
CSI-ISP-CLK CLK_OUT= CLK_IN/M M:1-16
CSI-ISP-CLK-OUT
AUDIOCODEC-CLK
PLL6
NC
PLL3
TVD-CLK
PLL7
OSC24M
PLL3x1 PLL7x1 PLL3x2 PLL7x2
PLL4 PLL5
OSC24M
Co
PLL3(1x) PLL7(1x)
PLL3(2x) PLL7(2x) PLL3 PLL4
PLL5
PLL7
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ACE-CLK CLK_OUT= CLK_IN/M M:1-16 CSI0/1-CLK CLK_OUT= CLK_IN/M M:1-32 MALI400-CLK(Max 381MHz) CLK_OUT= CLK_IN/M M:1-16
de
AVS-CLK AVS-CLK-OUT HDMI-CLK CLK_OUT= CLK_IN/M M:1-16 HDMI-CLK-OUT ACE-CLK-OUT CSI0/1-CLK-OUT MALI400-CLK-OUT
nti
AUDIOCODEC-CLK-OUT NC TVD-CLK-OUT
53
al

7.2.
A10
PLL Diagram
8.
8.1.1.
PWM
The output of the PWM is a toggling signal whose frequency and duty cycle can be modulated by its programmable registers. Each channel has a dedicated internal 16-bit up counter. If the counter reaches the value stored in the channel period register, it resets. At the beginning of a count period cycle, the PWMOUT is set to active state and count from 0x0000. The PWM divider divides the clock(24MHz) by 1-4096 according to the pre-scalar bits in the PWM control register. In PWM cycle mode,the output will be a square waveform,the frequency is set to the period register. In PWM pulse mode, the output will be a positive pulse or a negative pulse.
8.1.2. Signal Name

PWM0 PWM1
PWM Signal Description
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Description
54
Table 8-1 PWM Signal Description
nti
Type
O O
PWM output for port 0
9.
9.1.
Co
The chip implements 6 timers. Timer 0 and 1 can take their inputs from internal RC oscillator, external 32768Hz crystal or OSC24M. They provide the operating systems scheduler interrupt. They are designed to offer maximum accuracy and efficient management, even for systems with long or short response time. They provide 24-bit programmable overflow counter and work in auto-reload mode or no-reload mode. Timer 2 is used for OS to generate a periodic interrupt. The Watchdog timer is a timing device that resumes the controller operation after malfunctioning due to noise and system errors. The watchdog timer can be used as a normal 16-bit interval timer to request interrupt service. The watchdog timer generates a general reset signal.
The Real Time Clock (RTC) can be used as a calendar. RTC can operate using the backup battery while the system
power is off. Although power is off, backup battery can store the time by Second, Minute, Hour (HH-MM-SS), Day,
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Timer Controller
Overview
PWM output for port 1
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Pin Name
PB2 PI3
Overview
Ball#
B1 G5
A10
Month, and Year (YY-MM-DD) data. It has a built-in leap year generator and an independent power pin (RTCVDD). The Alarm generates an alarm signal at a specified time in the power-off mode or normal operation mode. In normal operation mode, both the alarm interrupt and the power management wakeup are activated. In power-off mode, the power management wakeup signal is activated.
10.1.
Overview
10.2.
Signal Name
EINT0 EINT1 EINT2 EINT3 EINT4 EINT5 EINT6 EINT7 EINT8 EINT9
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Description
External Interrupt source 0 External Interrupt source 1 External Interrupt source 2 External Interrupt source 3 External Interrupt source 4 External Interrupt source 5 External Interrupt source 6 External Interrupt source 7 External Interrupt source 8 External Interrupt source 9 External Interrupt source 10 External Interrupt source 11 External Interrupt source 12 External Interrupt source 13
55
External Interrupt Signal Description

Table10-1 External Interrupt Signal Description
de
Type
I I I I I I I I I I I I I I
The Interrupt Controller is featured as following: Support 95 vectored nIRQ interrupt 4 programmable interrupt priority levels Fixed interrupt priority of the same level Support Hardware interrupt priority level masking Programmable interrupt priority level masking Generates IRQ and FIQ Generates Software interrupt One external NMI interrupt source
nti
The Interrupt Controller in A10 can handle individually maskable interrupt sources up to 95. With the 4-level programmable interrupt priority, developer can define the priority for each interrupt source, permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated.
Co
EINT10 EINT11 EINT12 EINT13
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Pin Name
PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PE24 PE25 PC19 PC20
10.
Interrupt Controller
Ball#
T19 T20 R19 R20 P19 P20 N19 N20 M19 M20 T1 T2 C10 G9

Signal Name
EINT14 EINT15 EINT16 EINT17 EINT18 EINT19 EINT20 EINT21 EINT22 EINT23 EINT24 EINT25 EINT26 EINT27 EINT28 EINT29 EINT30 EINT31
A10
Type
I I I I I I I I I I I
Description
External Interrupt source 14 External Interrupt source 15 External Interrupt source 16 External Interrupt source 17 External Interrupt source 18 External Interrupt source 19 External Interrupt source 20 External Interrupt source 21 External Interrupt source 22 External Interrupt source 23 External Interrupt source 24 External Interrupt source 25 External Interrupt source 26 External Interrupt source 27 External Interrupt source 28 External Interrupt source 29 External Interrupt source 30 External Interrupt source 31
Pin Name
PC21 PC22 PB3 PB9 PB10 PB11 PB18 PB19 PB20 PB21 PH0 PH1 PH2 PH3 PI4 PI5 PI6 PI7
Ball#
F9 E9 G4 E3 E2 E1 T3 T4 P1 P2
nti
I I I I I I I
56
de
11.
11.1.
DMA Controller
Overview
Many peripherals on the A10 use direct memory access (DMA) transfers. There are two kinds of DMA, namely, Normal DMA and Dedicated DMA. For Normal DMA, ONLY one channel can be activated and the sequence is determined by the priority level. For Dedicated DMA, at most 8-channels can be activated at the same time as long as there is conflict of their source or destination. Both Normal DMA and Dedicated DMA can support 8-bit/16-bit/32-bit data width. The data width of Source and Destination can be different, but the address should be consistently aligned. Although the increase mode of Normal DMA should be address aligned, there is no need for its byte counter always goes in multiple. The Dedicated DMA can only transfer data between DRAM and modules. DMA Source Address, Destination Address can be modified even if DMA transfers have started.
Co
12.
12.1.
The NFC is the NAND Flash Controller which supports all NAND/MLC flash memory available in the market. New type flash can be supported by software re-configuration. The NFC can support 8 NAND flash with 1.8/3.3 V voltage supply. There are 8 separate chip select lines (CE#) for connecting up to 8 flash chips with2 R/B signals. Copyright 2011 Allwinner Technology. All Rights Reserved.
nfi
Overview
NAND Flash Controller
al
C6 D6 E6 F6 D3 A2 T7 U7
A10
The On-the-fly error correction code (ECC) is built-in NFC for enhancing reliability. BCH is implemented and it can detect and correct up to 64 bits error per 512 or 1024 bytes data. The on chip ECC and parity checking circuitry of NFC frees CPU for other tasks. The ECC function can be disabled by software. The data can be transferred by DMA or by CPU memory-mapped IO method. The NFC provides automatic timing control for reading or writing external Flash. The NFC maintains the proper relativity for CLE, CE# and ALE control signal lines. Three kind of modes are supported for serial read access. The conventional serial access is mode 0 and mode 1 is for EDO type and mode 2 for extension EDO type. NFC can monitor the status of R/B# signal line. Block management and wear leveling management are implemented in software.
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Signal Name
NCE[7:0] NWE NRD NRB[1:0] NALE NCLE NWP ND[7:0]
12.2.
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NAND FLASH Chip Select bit NAND FLASH Chip Write Enable NAND FLASH Chip Ready/Busy bit NAND FLASH Chip Read Enable NAND FLASH Chip Write Protect NAND FLASH Data bit
57
The NAND Flash Controller (NFC) includes the following features: Supports all SLC/MLC/TLC flash and EF-NAND memory available in the market Software configure seed for randomize engine Software configure method for adaptability to a variety of system and memory types Supports 8-bit Data Bus Width Supports 1024, 2048, 4096, 8192, 16384 bytes size per page Supports 1.8/3.3 V voltage supply Flash Up to 8 flash chips which are controlled by NFC_CEx# Supports Conventional and EDO serial access method for serial reading Flash On-the-fly BCH error correction code which correcting up to 64 bits per 512 or 1024 bytes Corrected Error bits number information report ECC automatic disable function for all 0xff data NFC status information is reported by its registers and interrupt is supported One Command FIFO External DMA is supported for transferring data Two 256x32-bit RAM for Pipeline Procession Support SDR, DDR and Toggle NAND Support self debug for NFC debu
NAND Flash Controller Signal Description

Table 12-1. NAND Flash Controller Signal Description
de
Description
nti
Type
O I O O O O O I/O
NAND FLASH Chip Address Latch Enable NAND FLASH Chip Cammand Latch Enable
al

13.1.
A10
SD3.0 Controller
SD 3.0 Overview
The SD3.0 controller can be configured either as a Secure Digital Multimedia Card controller, which simultaneously supports Secure Digital memory (SD Memo), UHS-1 Card, Secure Digital I/O (SDIO), Multimedia Cards (MMC), eMMC Card and Consumer Electronics Advanced Transport Architecture (CE-ATA). The SD3.0 controller includes the following features: Supports Secure Digital memory protocol commands (up to SD3.0) Supports Secure Digital I/O protocol commands Supports Multimedia Card protocol commands (up to MMC4.3) Supports CE-ATA digital protocol commands Supports eMMC boot operation and alternative boot operation Supports UHS-1card voltage switching and DDR R/W operation Supports Command Completion signal and interrupt to host processor and Command Completion Signal disable feature Supports one SD (Verson1.0 to 3.0) or MMC (Verson3.3 to 4.3) or CE-ATA device Supports hardware CRC generation and error detection Supports programmable baud rate Supports host pull-up control Supports SDIO interrupts in 1-bit and 4-bit modes Supports SDIO suspend and resume operation Supports SDIO read wait Supports block size of 1 to 65535 bytes Supports descriptor-based internal DMA controller Internal 16x32-bit (64 bytes total) FIFO for data transfer Support 3.3 V and 1.8V IO pad
13.2.
Co
Signal Name
SDCx_CLK SDCx_CMD SDCx_D[3:0]
SDCx=SDC[3:0]
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SDx/SDIOx/MMCx Output Clock SDx/SDIOx/MMCx Cmmand Line SDx/SDIOx/MMCx Data bit
58
SD3.0 Controller Signal Description

Table 13-1. SD3.0 Controller Signal Description
de
Description
nti
al
Type
O I/O I/O

14.1.
A10
Two Wire Interface

Overview
14.2.
TWI Controller Signal Description
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Signal Name
TWIx_SCK TWI-BUS Clock for Channel x TWIx_SDA TWI-BUS Data for Channel x
TWIx=TWI[2:0]
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Description
59
The 2-Wire Controller includes the following features: Software-programmable for Slave or Master Support Repeated START signal Support Multi-master systems Support 10-bit addressing with 2-Wire bus Performs arbitration and clock synchronization Own address and General Call address detection Interrupt on address detection Supports speeds up to 400Kbits/s (fast mode) Support operation from a wide range of input clock frequencies
Table 14-1. TWI Controller Signal Description
Co
15.1.
15.
SPI Interface
Overview
The SPI is the Serial Peripheral Interface which allows rapid data communication with fewer software interrupts. The SPI module contains one 64x8 receiver buffer (RXFIFO) and one 64x8 transmit buffer (TXFIFO). It can work at two modes: Master mode and Slave mode. It includes the following features: Full-duplex synchronous serial interface Master/Slave configurable Four chip selects to support multiple peripherals for SPI0 and SPI1 has one chip select 8-bit wide by 64-entry FIFO for both transmit and receive data Copyright 2011 Allwinner Technology. All Rights Reserved.
nti
Type
I/O I/O
al
This 2-Wire Controller is designed to be used as an interface between CPU host and the serial 2-Wire bus. It can support all the standard 2-Wire transfer, including Slave and Master. The communication to the 2-Wire bus is carried out on a byte-wise basis using interrupt or polled handshaking. This 2-Wire Controller can be operated in standard mode (100K bps) or fast-mode, supporting data rate up to 400K bps. Multiple Masters and 10-bit addressing Mode are supported for this specified application. General Call Addressing is also supported in Slave mode.

Polarity and phase of the Chip Select (SPI_SS) and SPI Clock (SPI_SCLK) are configurable Dedicated DMA support
A10
15.2.
SPI Controller Signal Description

Table 15-1. SPI Controller Signal Description
SPIx=SPI[2:0]
SPIx_CS0 SPIx_MOSI SPIx_MISO SPIx_CLK
SPIx Chip Select SPIx Master data Out, Slave data In SPIx Master data In, Slave data Out SPIx Clock
16.
16.1.
UART Interface
Overview
Co
The UART is used for serial communication with a peripheral, modem (data carrier equipment, DCE) or data set. Data is written from a master (CPU) over the APB bus to the UART and it is converted to serial form and transmitted to the destination device. Serial data is also received by the UART and stored for the master (CPU) to read back. The UART contains registers to control the character length, baud rate, parity generation/checking, and interrupt generation. Although there is only one interrupt output signal from the UART, there are several prioritized interrupt types that can be responsible for its assertion. Each of the interrupt types can be separately enabled/disabled with the control registers. The UART has 16450 and 16550 modes of operation, which are compatible with a range of standard software drivers. In 16550 mode, transmit and receive operations are both buffered by FIFOs. In 16450 mode, these FIFOs are disabled. The UART supports word lengths from five to eight bits, an optional parity bit and 1, 1 or 2 stop bits, and is fully programmable by an AMBA APB CPU interface. A 16-bit programmable baud rate generator and an 8-bit scratch register are included, together with separate transmit and receive FIFOs. Eight modem control lines and a diagnostic loop-back mode are provided. Interrupts can be generated for a range of TX Buffer/FIFO, RX Buffer/FIFO, Modem Status and Line Status conditions. For integration in systems where Infrared SIR serial data format is required, the UART can be configured to have a software-programmable IrDA SIR Mode. If this mode is not selected, only the UART (RS232 standard) serial data format is available. The UART includes the following features: Compatible with industry-standard 16550 UARTs 64-Bytes Transmit and receive data FIFOs DMA controller interface Software/ Hardware Flow Control Programmable Transmit Holding Register Empty interrupt
60
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de
nti
al
I/O I/O I/O I/O
Signal Name
Description
Type

Support IrDa 1.0 SIR Interrupt support for FIFOs, Status Change
A10
16.2.
UART Controller Signal Description

Table 16-1. UART Controller Signal Description
UARTx=[7:0]
Description
UARTx Transmit Data UARTx Receive Data
UARTx_TX UARTx_RX
17.
17.1.
IR Interface
Overview
Co
17.2.
IRx=IR[1:0]
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Signal Name
IR Transmit Data IR Receive Data
61
Compliant with IrDA 1.1 for MIR and FIR Full physical layer implementation Supports 0.576 Mbit/s and 1.152 Mbit/s Medium Infrared (MIR) physical layer protocol Support 4 Mbit/s FIR physical layer protocol defined by IrDA version 1.4 Support CIR for remote control or wireless keyboard Hardware CRC16 for MIR and CRC32 for FIR Dual 16x8-bits FIFO for data transfer Programmable FIFO thresholds Interrupt and DMA Support
IR Controller Signal Description

Table 17-1. IR Controller Signal Description
de
Description
Fast Infrared Interface (FIR) signals are multiplexed with UART2 signals using a system configuration for a complete infrared interface that supports SIR, CIR, MIR, and FIR modes. The Serial Infrared (SIR) protocol, which supports data rate which supports data rates up to 1.875 Mbit/s is implemented in each UART module. The IR includes the following features:
IRx_TX
IRx_RX
nti
al
Type
O I
Signal Name
Type
O I

18.1.
A10
USB OTG Controller

Overview
The USB2.0 OTG controller (SIE) includes the following features:
18.2.
USB OTG Controller Signal Description

Table 18-1. USB OTG Controller Signal Description
Signal Name
DM0 DP0
de
Description
62
USB0 OTG Data(-)
19.
19.1.
Co
USB Host Controller is fully compliant with the USB 2.0 specification and Enhanced Host Controller Interface (EHCI) Specification, Revision 1.0.The controller supports high-speed, 480-Mbps transfers (40 times faster than USB 1.1 full-speed mode). The USB host controller includes the following features: Including an internal DMA Controller for data transfer with memory. Complies with Enhanced Host Controller Interface (EHCI) Specification, Version 1.0. Support High-Speed (HS, 480-Mbps) Device only, and Supports Full-Speed (FS, 12Mbps) and Low-Speed (LS, 1.5Mbps) Device through a HS USB HUB. Support only 1 USB Root Port.
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USB HOST Controller
Overview
USB0 OTG Data(+)
nti
Complies with USB 2.0 Specification Support High-Speed (HS, 480-Mbps), Full-Speed (FS, 12-Mbps), and Low-Speed (LS, 1.5-Mbps) in Host mode and support High-Speed (HS, 480-Mbps), Full-Speed (FS, 12-Mbps) in Device mode 64-Byte Endpoint 0 for Control Transfer (Endpoint0) Support up to 5 User-Configurable Endpoints for Bulk , Isochronous, Control and Interrupt bi-directional transfers (Endpoint1, Endpoint2, Endpoint3, Endpoint4, Endpoint5)
al
Type
AIO AIO
The USB OTG is dual-role controller, which supports both Host and device functions. It can also be configured as a Host-only or Device-only controller, full compliant with the USB 2.0 Specification. It can support high-speed (HS, 480-Mbps), full-speed (FS, 12-Mbps), and low-speed (LS, 1.5-Mbps) transfers in Host mode. It can support high-speed (HS, 480-Mbps), and full-speed (FS, 12-Mbps) in Device mode.

19.2.
A10
USB HOST Controller Signal Description

Table 19-1. USB Host Controller Signal Description USBx Host2.0=USB[1:0] Host2.0
Signal Name
DM1 DP1 DM2 DP2 USB1 HOST Data(-) USB1 HOST Data(+) USB2 HOST Data(-) USB2 HOST Data(+)
Description
Type
AIO AIO AIO
20.1.
Overview
Co
20.2.
Signal Name
I2S_MCLK I2S_BCLK I2S_LRCK I2S_DO[3:0] I2S_DI
It includes the following features: I2S or PCM configured by software Full-duplex synchronous serial interface Configurable Master / Slave Mode operation Support Audio data resolutions of 16, 20, 24 I2S Audio data sample rate from 8Khz to 192Khz I2S Data format for standard I2S, Left Justified and Right Justified I2S support 8 channel output and 2 channel input PCM supports linear sample (8-bits or 16-bits), 8-bits u-law and A-law compressed sample One 128x24-bits FIFO for data transmit, one 64x24-bits FIFO for data receive Programmable FIFO thresholds Support Interrupt and DMA Two 32-bits Counters for AV sync application
nfi
I2S Main Clock(system clock) I2S serial Bit Clock I2S serial Data Output bit I2S serial Data Input
63
Digital Audio Signal Description

Table 20-1. Digital Audio Controller Signal Description
de
Description
The Digital Audio Interface can be configured as I2S interface or PCM interface by software. When configured as I2S interface, it can support the industry standard format for I2S, left-justified, or right-justified. When configured as PCM, it can be used to transmit digital audio over digital communication channels. It supports linear 13, 16-bits linear, 8-bit u-law or A-law compressed sample formats at 8K samples/sec, and can receive and transmit on any selection of the first four slots following PCM_SYNC.
I2S Left or Right channel select clock(frame clock)
nti
20.
Digital Audio Interface
al
AIO
Type
O I/O I/O O I

21.1.
A10
AC97 Interface
Overview
nfi
Signal Name
AC97 Codec Input Mclk Digital Audio Sample rate/sync Digital Audio Serial Data Input Digital Audio Serial Data Onput
21.2.
AC97 Signal Description
de
Description
64
AC97 Interface includes below features: Compliant with AC97 2.3 component Specification Full-duplex synchronous serial interface Support 2 channels, TX (stereo),RX (PCM stereo, MIC mono optional) Variable Sampling Rate AC97 Codec Interface support, up to 48KHz Support 2 channel and 6 channel audio data output Support DRA mode Support Only one primary Codec Channels support mono or stereo samples of 16(standard), 18(optional) and 20(optional) bit wide. One 9620bits FIFO and one 3220-bits FIFO for data transfer Programmable FIFO thresholds Support Interrupt and DMA
Table 21-1. AC97 Controller Signal Description
AC97_MCLK AC97_BCLK AC97_DO AC97_DI AC97_SYNC
Digital Audio Serial Clock Provided by AC97 Codec
nti
Co
22.
22.1.
Audio Codec
Overview
The embedded Audio Codec is a high-quality stereo audio codec with headphone amplify. The audio codec is featured as following: On-chip 24-bits DAC for play-back Copyright 2011 Allwinner Technology. All Rights Reserved.
al
Type
O I O I O
The AC97 interface supports AC97 revision 2.3. AC97 Controller uses audio Controller link (AC-link) to communicate with AC97 Codec. In transmission mode, Controller sends the stereo PCM data to Codec. The external digital-to-analog converter (DAC) in the Codec converts the audio sample to an analog audio waveform. In receiving mode, Controller receives the stereo PCM data and the mono Microphone data from Codec then stores in memories.

On-chip 24-bits ADC for recorder Support analog/ digital volume control Support 48K and 44.1K sample family Support 192K and 92K sample Support FM/ Line-in/ Microphone recorder Stereo headphone amplifier that can be operated in capless headphone mode Support to automatic change from Virtual Ground to True Ground to protect headphone amplifier
A10
22.2.
Audio Codec Signal Description

Signal Name
HPL HPR HPCOM HPCOM_FB FMINL FMINR LINEINL LINEINR MICINL MICINR
Table 22-1. Audio Codec Signal Description
Description
Audio DAC(24bit) output for Left channel ofHeadphone Audio DAC(24bit) amplifier output
Audio DAC(24bit) output for Right channel of Headphone
Audio DAC(24bit) amplifier Feedback
Audio ADC(24bit) Input for Left channel of FM radio Audio ADC(24bit) Input for Left channel of Line In Audio ADC(24bit) Input for Right channel of Line In
de
65
Audio ADC(24bit) Input for Right channel of FM radio
Audio ADC(24bit) Input for Left channel of Microphone Audio ADC(24bit) Input for Right channel of Microphone
23.
23.1.
LRADC is 6-bits resolution for key application. The LRADC can work up to maximum conversion rate of 250Hz. The LRADC is featured as following Support APB 32-bits bus width Support Interrupt Support Hold Key and General Key Support Single Key and continue key mode 6-bits Resolution Voltage input range between 0 to 2V Sample Rate up to 250Hz
Co
nfi
LRADC
Overview
nti
A A
al
Type
AO AO AI AI AI AI AI AI

23.2.
A10
LRADC Signal Description

Table 23-1. LRADC Signal Description
Signal Name
LRADC[1:0]
Description
Low Resolution ADC0 input(6bit)
Type
AI
24.
24.1.
Keypad Interface
Overview
The Key Pad Interface block in A10 facilitates communication with external keypad devices. The ports can provide up to 8 rows and 8 columns. The events of key press or key release are delivered to the CPU by an interrupt. To prevent the switching noises, keypad interface comprise of internal debouncing filter. The Keypad Interface includes the following features:
Interrupt for key press or key release Internal debouncing filter to prevent the switching noises
24.2.
Keypad Signal Description

Signal Name
nfi
Keypad Interface Row data Keypad Interface Column0 data
de
Description
66
Table 24-1. Keypad Signal Description
KP_IN[7:0]
nti
KP_OUT[7:0]
Co
25. Touch Panel
25.1.
Overview
The TP controller can be configured either as a 4-wire resistive touch screen controller or a 12-bit resolution A/D converter. As a 4-wire resistive touch screen controller, it supports dual touch detection. As an A/D converter, it can locate of single touch through two times of A/D conversion. The TP controller is featured as following: 12 bit SAR type A/D converter 4-wire I/F Copyright 2011 Allwinner Technology. All Rights Reserved.
al
Type
I O

Dual Touch Detection Touch-pressure measurement (Support program set threshold) Sampling frequency: 2MHz (max) Support both Single-Ended and Ratiometric Conversion of Touch Screen Inputs TACQ up to 262ms Support Median and averaging filter which can reduce noise Pen down detection, with programmable sensitivity Support X, Y change function
A10
25.2.
Touch Panel Signal Description

Signal Name
X[2:1] Y[2:1]
Table 25-1. Touch Panel Signal Description
Touch Pane ADC input(11bit) Touch Pane ADC input(11bit)
26.1.
Port Description
Co
27.

The chip has 8 ports for multi-functional input/out pins. They are shown below: Port A(PA): 18 input/output port Port B(PB): 24 input/output port Port C(PC): 25 input/output port Port D(PD): 28 input/output port Port E(PE) : 12 input/output port Port F(PF) : 6 input/output port Port G(PG) : 12 input/output port Port H(PH) : 28 input/output port Port I(PI) : 22 input/output port Port S(PS) : 84 input/output port for DRAM controller For various system configurations, these ports can be easily configured by software. All these ports (except PS) can be configured as GPIO if multiplexed functions not used. 32 external PIO interrupt sources are supported and interrupt mode can be configured by software.
27.1.
8 bits input data Support CCIR656 protocol for NTSC and PAL
67
nfi
Feature
Camera sensor interface
de
26.
Port Controller
nti
Description
al
Type
AI AI

3 parallel data paths for image stream parsing Received data double buffer support Parsing bayer data into planar R, G, B output to memory Parsing interlaced data into planar or tile-based Y, Cb, Cr output to memory Pass raw data direct to memory All data transmit timing can be adjusted by software
A10
27.2.
Table 27-1. Camera sensor Signal Description
Signal Name CSI0

CSI0_PCK CSI0_MCK CSI0_HSYNC CSI0_VSYNC CSI0_D[7:0]
Description
Camera Sensor Pixel Clock
nti
68
Camera Sensor Clock Output
Camera Sensor Horizontal Synchronization Camera Sensor Verizontal Synchronization Camera Sensor Data bit 07
CSI1
CSI1_D[23:0] CSI1_PCLK CSI1_FIELD CSI1_HSYNC CSI1_VSYNC
Camera Sensor Data bit 023
de
Digital Image Pixel Clock input
CMOS Sensor Horizontal Synchronization CMOS Sensor Verizontal Synchronization
28.
28.1.
Co

TCON in A10 is of high flexibility in timing configuration as well as LCD module compatibility. System clock SCLK: 270297MHz Programmable IO standard by VCCIO(3.3v/2.5v/1.8v) 3 input source: 2 DE sources and one DMA source Support simultaneous display (different picture/video) for both LCD and TV Support HV-DE-Sync(digital parallel RGB) input LCD panels(Max 1024*1024 resolution, 24-bit color) Support HV-DE-Sync(digital serial RGB, both delta and stripe panel) input LCD panels(Max 680*1024 resolution, up to true color) Support TTL(digital RGB) input LCD panels(Max 1024*1024 resolution, 18-bit color) Support Analog RGB input LCD panels(Max 1024*1024 resolution, 3 channel 6bit DAC output ) Support 18/16/9/8bit 8080 CPU I/F panels(Max 1024*1024 resolution)
nfi
Overview
Universal LCD/TV Timing Controller
al
Type
I O I I I I I I
Camera sensor Signal Description

CCIR656 output interface for LCD panel or TV encoder Up to full HDTV timing for TV encoder and HDMI transmitter Internal line scaling and Gamma correction 4 interrupts for programmer
A10
28.2.
LCD Signal Description

Signal Name
LCDx_CLK LCDx_DE LCDx_HSYNC LCDx_VSYNC LCDx_D[23:0] LCD RGB Pixel Clock LCD RGB Data Enable
Description
LCD RGB Horizontal Synchronization LCD RGB Verizontal Synchronization LCD Pixel Data bit 023 LVDS Output Data+ for Channelx LVDS Output Data- for Channelx
nti
69
LVDSx_VP[3:0] LVDSx_VN[3:0]
29.
29.1.
Mixer Processor
Overview
Color format support ARGB 8888/4444/1555 RGB565 MONO 1/2/4/8 bpp Palette 1/2/4/8 bpp (input only) 22/420 Any format convert function Buffer block size Up to 8192*8192 pixels Support Memory scan order option Support Clipping ROP2 Line / Rectangle / Point Block fill ROP3 BitBLT PatBLT
Co
nfi
Mixer processor is a 2D graphics engine of high performance, and 2D image can be widely customized due to its high flexibility in configuration.
de
al
Type
O O O O O O O
Table 28-1. LCD Signal Description LCDx=LCD[1:0]; LVDSx=LVDS[1:0]

StretchBLT ROP4 MaskBLT Rotation 90/180/270 degree Support mirror Alpha blending Support Plane & Pixel alpha Support Output alpha configurable Support Color key Scaling 4*4 taps 32 phase Support color space convert
A10
29.2.
Block diagram
Co
29.2.1.
nfi
Layer rotation and mirroring control
Each layer data can be realized rotation and mirror operation function, total 8 operation according 8 control code, reference the following diagram.
70
de
nti
al
A10
Control code: Normal
30.
30.1.

TV Encoder
Feature
Co
30.2.
Signal Name
TV_OUT[3:0] TV_VCC TV_GND
Multi-standard support for NTSC-M, NTSCJAPAN,PAL (B, D, G, H, I, M, N,Combination N)@27M clock Support 480P, 576P@54M clock Support 720P,1080i@74.25M clock Support 1080P@148.5M clock Video input data port supports: CCIR-656 4:2:2 8-bit parallel input format Video output data port supports: 4 X12-bit DAC data output, Composite(CVBS) and Component S-video(Y/C) or Component YUV or RGB
Analog signal output copyright protection Programmable 4 X DAC data path Plug status auto detecting
nfi
TV Analog Output(12bit DAC0..3) TVDAC Analog Power TVDAC Analog Ground
71
TV-OUT Signal Description

Table 30-1. TV-OUT Signal Description
de
Description
Control code: AXY
AY
nti
XY
al
X Y AX
Type
AO
Allwinner Technology CO., Ltd. 31. Declaration
A10
This product datasheet is the original work and copyrighted property of Allwinner Technology (Allwinner). Reproduction in whole or in part must obtain the written approval of Allwinner and give clear acknowledgement to the copyright owner. The information furnished by Allwinner is believed to be accurate and reliable. Allwinner reserves the right to make changes in circuit design and/or specifications at any time without notice. Allwinner does not assume any responsibility and liability for its use. Nor for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Allwinner. This data sheet neither states nor implies warranty of any kind, including fitness for any particular application.
Co
72
nfi
de
nti
al

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Allwinner Technology CO., Ltd. Revision History

Random Access Memory

Pulse Width Modulator

Copyright 2011 Allwinner Technology. All Rights Reserved.

Allwinner Technology CO., Ltd.

developed by the SD Card Association for use in portable devices.

dual-role controller, which supports both 13 USB OTG USB On-The-Go

Low Resolution Analog to Digital Converter

Touch Panel Controller Transport Stream

Copyright 2011 Allwinner Technology. All Rights Reserved.

Host and device functions and is full

media audio format.

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6.4.1. 6.4.2. 6.5. 6.6.

Copyright 2011 Allwinner Technology. All Rights Reserved.

Power Domain Signal Description.................................................................................. 44 Miscellaneous Signal Description .................................................................................. 46

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DMA Controller ........................................................................................................................... 56 Overview ............................................................................................................................... 56

12.1. 12.2. 13.

Overview ............................................................................................................................... 56 NAND Flash Controller Signal Description ............................................................................ 57

13.1. 13.2. 14.

14.1. 14.2. 15.

15.1. 15.2. 16.

17.1. 17.2. 18.

Overview ............................................................................................................................... 60 UART Controller Signal Description ...................................................................................... 61

NAND Flash Controller............................................................................................................... 56

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Overview ............................................................................................................................... 64 AC97 Signal Description........................................................................................................ 64

22.1. 22.2. 23.

23.1. 23.2. 24.

Overview ............................................................................................................................... 65 LRADC Signal Description .................................................................................................... 66

24.1. 24.2. 25.

25.1. 25.2. 26.

Port Controller ............................................................................................................................ 67 Port Description..................................................................................................................... 67

Camera sensor interface............................................................................................................ 67 Feature .................................................................................................................................. 67

27.1. 27.2. 28.

28.1. 28.2. 29.

Mixer Processor.......................................................................................................................... 69 Overview ............................................................................................................................... 69

Camera sensor Signal Description ........................................................................................ 68

Copyright 2011 Allwinner Technology. All Rights Reserved.

Allwinner Technology CO., Ltd. 1. Introduction

support Open GL ES 2.0 / open VG 1.1

Copyright 2011 Allwinner Technology. All Rights Reserved.

Allwinner Technology CO., Ltd.

Display Output Ability

Dual camera sensor interface (CSI0 supports ISP function)

Copyright 2011 Allwinner Technology. All Rights Reserved.

Display Processing Ability

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TFBGA441package 0.8mm pitch

Copyright 2011 Allwinner Technology. All Rights Reserved.

Allwinner Technology CO., Ltd. 3. Functional Block Diagram

Card Slot0,1 Card Controller0 WIFI

LCD Display &Touch

E-Mac IR Controller ADC

CortexA8 GPU VE Processor

Allwinner Technology CO., Ltd. 4.

Copyright 2011 Allwinner Technology. All Rights Reserved.

Allwinner Technology CO., Ltd.

Figure 4-2 TFBGA441 Pin Map-Top View [Quadrant A]

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