Interfacing Serial RS-232 with FPGA

Introduction
This lab will be an introduction on how to establish an interconnection between PC and FPGA kit through serial RS-232 interface using hyper terminal available on the laptop/PC.

Objective
The objective is to control the frequency of a simple 4-bit counter through RS-232 port using hyperterminal. The counter implemented here is a 4-bit counter operated at five different frequencies. Here to show the user a method to interface a laptop or PC with an FPGA kit using available RS-232 port on the board with appropriate interactive signals. WISHBONE protocol is employed in the present labto establish the communication.

4-bit Counter Design Overview

The 4-bit counter is implemented at five different frequencies using the system clock running at 50 Mhz. The frequencies are
50 Mhz 50 Mhz 50 Mhz 50 Mhz 50 Mhz , , , , , (the frequencies 3 23 24 25 226 2 2 2 2

are chosen to make the counter action visible through the LEDs, except for the highest frequency which is solely to verify the design in the Xilinx Simulator). The frequencies are controlled using input signal FREQUENCY which in turn is controlled using the five keys (1, 2, 3, 4 & 5) on the keyboard. The output of the 4-bit counter is connected to four of the available seven LEDs (LD0, LD1, LD2, LD3). An asynchronous reset is also provided to the design which is connected to one of the sliding switches (SW0). The UART core is taken from http://www.opencores.org/?do=project&who=muart.

RS-232 Serial Interface

1. Characteristics
Uses a 9 pin connector DB-9 (older PCs use 25 pins DB-25 and newer laptops do not have serial port anymore, so a USB to serial converter is required). Allows bidirectional full-duplex communication (the PC can send and receive data at the same time). Can communicate at a maximum speed of roughly 10KBytes/s.

2. DB-9 Connector
DB-9 connector (male) appears as shown in Figure 1.

Figure 1: DB-9 Connector

The pin numbering on the connector is as follows:

Figure 2: Pin Numbering (male connector)

Figure 3: Pin Numbering (female connector)

Pin Description of RS-232 male connector: Pin No. 1 2 3 4 5 6 7 8 9 Name Dir DCD RD TD DTR GND DSR RTS CTS RI IN IN Notes/Description Data Carrier Detect. Raised by DCE when modem synchronized. Receive Data (RD, Rx). Arriving data from DCE.

OUT Transmit Data (TD, Tx). Sending data from DTE. OUT Data Terminal Ready. Raised by DTE when powered on. In autoanswer mode raised only when RI arrives from DCE. IN Ground Data Set Ready. Raised by DCE to indicate ready.

OUT Request To Send. Raised by DTE when it wishes to send. Expects CTS from DCE. IN IN Clear To Send. Raised by DCE in response to RTS from DTE. Ring Indicator. Set when incoming ring detected - used for autoanswer application. DTE raised DTR to answer.

Table 1: Pin Description (male connector) The three important ones among the 9 pins are:

pin 2: RD (receive data). pin 3: TD (transmit data). pin 5: GND (ground).

Using just 3 wires, one can send and receive data.

3. Serial Communication
Data is sent one bit at a time. One wire is used for each direction. Since computers usually need at least several bits of data, the data is serialized before being sent. Data is commonly sent by chunks of 8 bits. The LSB (data bit 0) is sent first, the MSB (bit 7) last.

4. Asynchronous Communication
This interface uses an asynchronous protocol which means that no clock signal is transmitted along with data. The receiver has to have a way to time itself to the incoming data bits. In the case of RS-232, it is done in the following way:

1. Both side of the cable agree in advance on the communication parameters (parameters shown in Figure 4). It is done manually before communication starts (which will be explained later).

Figure 4: Serial Communication Parameters 2. The transmitter sends a "1" when the line is idle. 3. The transmitter sends a "start" (a "0") before each byte is transmitted, so that the receiver can understand that data is coming. 4. After the "start", data comes in with the agreed speed and format, so the receiver can interpret it. 5. The transmitter sends a "stop" (a "1") after each data byte.

For example, a 0x55 byte when transmitted appears in the following way:

Figure 5: 0x55 Byte Transmission Byte 0x55 is 01010101 in binary. But since it is transmitted LSB (bit-0) first, the line toggles like that: 1-0-1-0-1-0-1-0. Another example:

Figure 6: 0xC4 Byte Transmission Here the data is 0xC4, which is difficult to interpret. It an illustration to show how important it is for the receiver to know at which speed the data is sent.

5. Operation Speed
The speed is specified in baud, i.e. how many bits-per-seconds can be sent. For example, 1000 bauds would mean 1000 bits-per-seconds, or that each bit lasts one millisecond. Common implementations of the RS-232 interface (like the one used in PCs) do not allow just any speed to be used. One has to settle to some "standard" speed. Common values are:

1200 bauds. 9600 bauds. 38400 bauds. 115200 bauds.

At 115200 bauds, each bit lasts (1/115200) = 8.7s. If one transmits 8-bit data, it lasts for 8 x 8.7s = 69s. But each byte requires an extra start and stop bit, so one actually needs 10 x 8.7s = 87s. That translates to a maximum speed of 11.5 KBytes per second. At 115200 bauds, some PCs with faulty chips require a "longer" stop bit (1.5 or 2 bits long) which makes the maximum speed drop to around 10.5KBytes per second.

6. Physical Layer
The signals on the wires use a positive/negative voltage scheme.

"1" is sent using -10V (or between -5V and -15V). "0" is sent using +10V (or between 5V and 15V).

So an idle line carries something like -10V.

WISHBONE Protocol
The WISHBONE System-on-Chip (SoC) Interconnect Architecture is a portable interface for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating system-on-a-chip integration

problems. It is accomplished by creating common logical interfaces. This improves the portability and reliability of the system, and results in faster time-to market for the end user. WISHBONE is not an IP core but is a specification for creating IP cores. WISHBONE System-on-Chip Interconnect protocol can be used as an interface to all cores that require interfacing to other cores inside a chip (FPGA, ASIC, etc.). The WISHBONE architecture sits between the PC and UART interface as shown below in Figure 7.
WISHBONE Protocol Serial Communication

PC

UART

FPGA

Figure 7: System Block Diagram The WISHBONE protocol is a set of handshake signals carried out in a systematic exchange fashion in order to maintain synchronization between two systems. The handshake signals and their respective order as used in this protocol are as shown below in Figure 8.

SYSTEM

Tx_int = 1

UART

Rx_int = 1

STB = 1 WR = 1 ADDR = 00 DATA = XX

ACK = 1

STB = 0

ACK = 0 Last ACK signal is not implemented in the WISHBONE State Machine of the present design

Figure 8: WISHBONE Protocol Signal Exchange

Present UART Design Description

This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS-232 line and a WISHBONE bus. It is built to be very small (to fit in small FPGAs), but also efficient. It is not suited to interface a modem as there is no control handshaking (CTS/RTS). It integrates two separate clocks, one for WISHBONE bus, the other for bit stream generation. This has the advantage to let the user operate at any desired frequency (limited only by RS-232 interface) for the baud rate. There are full functionality UARTs available on opencores.com but the full functionality is not required for this lab. For this lab, the proposed light UART will be sufficient. Design supports: 1. WISHBONE interface in 8-bit data bus 2. Two clocks: one for WISHBONE interface, one for RS-232 bit stream generation 3. Baud rate divisor from 1 to 65536 (generic parameter set at integration time) Design does not support: 1. FIFO input/output 2. Control handshaking

IO Ports:
WISHBONE Interface Signals: Width 1 1 2 8 8 1 1 1 Direction Input Input Input Input Output Input Input Output Description Blocks clock input Asynchronous Reset Used for register selection Data input Data output Write or read cycle selection Specifies transfer cycle Acknowledge of a transfer

Port WB_CLK_I WB_RST_I WB_ADDR_I WB_DAT_I WB_DAT_O WB_WE_I WB_STB_I WB_ACK_O

Table 2: WISHBONE Interface Signals Other Internal Signals: Width 1 1 1 Direction Output Output Output Description Transmit Interrupt Receive Interrupt Clock for serialisation/unserialisation

Port IntTx_O IntRx_O BR_CLK_I

Table 3: Other Internal Signals

External (off-chip) Connections: Width 1 1 Direction Output Input Description The serial output signal The serial input signal

Port TxD_PAD_O RxD_PAD_I

Table 4: External Connections Clocks: Source WISHBONE bus User Rates (MHz) Remarks Max Min Resolution Limited None by target host None Table 5: Clocks Description WISHBONE clock Baudrate clock

Name WB_CLK_I BR_CLK_I

Registers: 1. Register List:

Name Receive buffer Transmit buffer Status Reserved Reserved

Address 0 0 1 2 3

Width 8 8 8 8 8

Access R W R

Description Contain byte received Contain byte to transmit Receive buffer full / Transmitter busy

Table 6: Register List 2. Status Register: Bit # 0 Access R Description Transmitter buffer state = IntTx_O pin 0 Busy. Cant accept incoming byte 1 Accept a byte to transmit Receiver buffer state = IntRx_O pin 0 Buffer empty 1 Buffer contain a received byte Table 7: Status Register Reset Value: XXXXXX01b

UART Design Operation

The UART Operation is very basic: Upon a write to the data input bus WB_DAT_I, the core will automatically serialize and emit the byte on the TxD_PAD_O. It will hold IntTx_O low as long as it cannot accept an incoming byte. Therefore a rising edge on IntTx_O can trigger the interrupt line of a microcontroller to emit another byte. Upon reception of a bit stream on RxD_PAD_O, the core will de-serialise the information and assert IntRx_O pin. This announces that the received byte can be read on the data output bus WB_DAT_O. As soon as the byte is read, IntRx_O is negated.

WISHBONE Bus
The design is 8-bit WISHBONE compatible. It doesnt use the WB_CYC_I pin as it will never insert wait states.

Initialization
The design doesnt need to be reset, as it is ready to use upon power on. However, a synchronous assertion of WB_RST_I will abort any pending transmit/receive and will set the core in idle state.

Baudrate Divisor
A generic VHDL parameter allows the user to introduce a divisor between BR_CLK_I clock and the bit stream frequency. In addition, the core inserts a 4 divisor for sampling purpose for the receiver. Thus: Baudrate = Freq(BR_CLK_I) / BRDIVISOR / 4 where BRDIVISOR is the generic parameter. For example to instantiate the component in a VHDL unit, write: U1 : MiniUART generic map (BRDIVISOR => 103) port map (clk, rst, adr, ...); for a division of 103.

Below are given some divisor values for common baudrates: BRDIVISOR Baudrate 2080 1200 1040 2400 520 4800 260 9600 130 19200 65 38400 BR_CLK_I at 10MHz BRDIVISOR Baudrate 192 2400 96 4800 48 9600 32 14400 24 19200 16 28800 8 57600 4 115200 2 230400 1 460800 BR_CLK_I at 1.8432MHz

Baudrate tolerance:
The receiver will accept a slight variation between the expected baudrate and the effective bit stream baudrate that is: Min freq Max freq Nominal Baudrate -2.60% Nominal Baudrate +5.90%

Equivalent in period : Min period Nominal period -5.90% Max period Nominal period +2.60% Going beyond these limits will make the receiver unable to de-serialise correctly (illustrated in Figure 9 ).

Byte 0x42 Start Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Stop

Nominal expected baudrate Max period for the bit stream +2.6% Min period for the bit stream -5.9%

Figure 9: Baudrate Tolerance Margin Illustration

Architecture
The block diagram of the design is as given:
BR_CLK_I

Baudrate Divisor

Receiver
WISHBONE SIGNALS WISHBONE Bus interface

RxD_PAD_I

%4

Transmitter TxD_PAD_O

IntTx_O IntRx_O

Figure 10: Block Diagram of the System Design

Initial Set-up and Output

Connect the Digilent Spartan-3E kit to a laptop/PC as shown below.

Figure 11: USB Connection Then connect the serial port (DCE terminal) available on the FPGA board to the another USB port available on the laptop/PC using a USB-to-Serial converter as shown below.

Figure 12: USB-to-Serial Converter

Figure 13: RS-232 Interface Switch on the board and configure the device using the Xilinx ISE 10.1 tool. Open the hyper terminal as shown below.

Figure 14: Hyper Terminal Path

The following window will pop up.

Figure 15: Hyper Terminal Give an appropriate name and press OK. Then the following window will show up. Select the appropriate com port and press OK.

Figure 16: Com Port Selection

The following window will show up. Make the port settings as shown below or set the baudrate to a desired rate depending on the design parameters. As the baudrate in the present design is configured for 9600 baud, the following settings are been chosen.

Figure 17: Hyper Terminal Settings Once the port settings are made press OK and the following terminal will show up. Now try pressing any of the following five keys: 1, 2, 3, 4 & 5 and observe the change in the frequency of the counter by looking at the four LEDs (LD0, LD1, LD2 & LD3) operation speed.

Figure 18: Output