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#********************************************************* # Analyze and Elaborate the HDL files read_hdl ${myFiles} elaborate ${basename} # Apply Constraints and generate clocks set clock [define_clock -period ${myPeriod_ps} -name ${myClk} [clock_ports]] DEPARTMENT OF ECE M.TECH VLSI DESIGN Page 1
external_delay -input $myInDelay_ps -clock ${myClk} [find / -port ports_in/*] external_delay -output $myOutDelay_ps -clock ${myClk} [find / -port ports_out/*]
#INSERT DESIGN FOR TEST COMMANDS HERE set_attribute dft_scan_style muxed_scan / clocked lssd scan) ;#( Selectig the scan style for the design it can be a muxed scanstyle or ;# (For muxed scan style, specify the pin or port
define_dft shift_enable -name SE -active high -create_port SE which drives the shift_enable pin of the scan flip-flops)
define_dft test_mode -design ${DESIGN} -name TM -active high TM create ;# ( Defining the test mode for the signals which are already coded in the RTL, or test mode will be used to enable the fixing of DFT violations, or test mode is used to configure the data direction control for a bidirectional or tri-state pad) report dft_setup ;# (Report the status of design for test setup )
synthesize -to_generic ;# (Perform an RTL optimization to create a generic netlist to remove all the dont care cells this should be done in order so that the dft rule checker might not be able to check through dont care cells and would result in extra dft violations) check_dft_rules ;#( this command is for Identify all uncontrollable clocks, and any asynchronous set and reset pins that cannot be held to their inactive value during test mode ) report dft_registers ;# (Report the scannable status of the flip-flops in the design) ;#( Specify the scan flip-flop output pin to use
set_attribute dft_scan_output_preference auto /designs/$DESIGN for the scan data path connection)
set_attr dft_scan_map_mode tdrc_pass /designs /$DESIGN ;#( This command is used to control the mapping of flip-flops to scan flip-flops) check_dft_rules > dft_rules.report2 ;#(write in to an out put file the status of design rule violations)
synthesize -incremental -effort high ;#(It converts any all the non scannable flops to scannable flops with fixing of timing violations) define_dft scan_chain -name chain1 -create_ports -sdi tdi -sdo tdo existing chain with the specified input and output scan data ports) ;#( Creates a scan chain or analyzes an
set_attribute dft_identify_internal_test_ clocks true ;#( the tool creates automatically separate test clocks in the same test-clock domain if the design has a clock path that contains multiple input combinational gates inorder to avoid introducing hold time violations in the scan path due to clock skew) set_attr dft_min_number_of_scan_chains 2 /designs/ $DESIGN ;#( Specify the minimum number of scan chains to be created) set_attr dft_mix_clock_edges_in_scan_chains true /designs/ $DESIGN ;#( Specify whether to allow mixing of rising and falling edge-triggered scan flip-flops from the same test-clock domain in the same scan chain) report dft_setup ;#(report the present (up to now) status of design for test) ;#( preview the scan connection) Page 2
:#( The -auto_create_chains option allows the tool to add new chains that
report dft_setup ;#(report the present (up to now) status of design for test) # Sets transition to default values for Synopsys SDC format, # fall/rise 400ps dc::set_clock_transition .4 $myClk # check that the design is OK so far check_design -unresolved report timing lint # Synthesize the design to the target library synthesize -to_mapped # Write out the reports report timing > ${basename}_${runname}_timing.rep report gates > ${basename}_${runname}_cell.rep report power > ${basename}_${runname}_power.rep # Write out the structural Verilog and sdc files write_hdl -mapped > ${basename}_${runname}.v write_sdc > ${basename}_${runname}.sdc #write out the reports of dft for ATPG tools write_atpg -cadence > accu_RTL.atpg ;#(Pin assignment file) write_atpg -stil > accu.stil.atpg report dft_chains > accu_dft.report quit ;#(information about timing ,signals and signal groups) ;#(description of scan chains created)
/usr/software/cadence/cdks/gsclib090_v3.3/vlog o update project o clickok o select Run select on Tasks Tab #(tasks tab is the history ) Select Verification Build Models Test Mode (one window will popup)#(input will be pin definition file) o Test Mode Name ---FULLSCAN #(this is a default mode for an ATPG SI to SO configuration) o Select input pin Assignment file ---accu_RTL.atpg click open #(this is the pin definition file generated in encounter rtl compiler) o Select run Select Verification Verify Test Structures o Select Test Mode Name ----FULLSCAN #(this checks for valid scan chains by tracing back from SO to SI) o Select Run Select Verification Build Models Fault Model (one window will popup) #(so to select a fault model to include different types of faults like ex dynamic faults) o Select Fault Cell Boundary Only o Deselect Include Dynamic Faults o Select Run Select ATPG Create Tests Specific Static Tests Scan Chain (one window will popup) #(the first tests you always create are those that do simple shifting through the scan chains.This is mainly for manufacturing debugs) o Select test mode name --- FULLSCAN o create tests experiment name ---- SCAN_CHAIN_TEST o Click Run Select ATPG Commit Tests (one window will popup) #(this process will apply the vectors generated permanently against the global fault) o Select Test Mode Name ---- FULLSCAN o Select Input Experiment Name ---- SCAN_CHAIN_TEST o Click Run Select ATPG Create Tests Specific Static Tests logic (window popup) #(creation of standard STUCKAT-FAULT model for ATPG patterns) o Select Test Mode Name ---- FULLSCAN o create tests experiment name---SCAN_LOGIC_TEST o select Run Select ATPG Commit Tests (one window will popup) # this process will apply the vectors generated permanently against the faults) o Select Test Mode Name ----FULLSCAN o Select Input Experiment Name ---- SCAN_LOGIC_TEST o Select Run Select ATPG Write Vectors (one window will popup)#(this step is usually for final manufacturing patterns ,these patterns would be finally the vectors you have finalized and commited) o Select Test Mode Name ----FULLSCAN o Set output File Name---- final click Run
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