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ADC Converters
Sampling (continued)
Track & hold circuits T/H combined with summing/difference function T/H circuit incorporating gain & offset cancellation
2 2 1
off S2
on)
Offset NOT cancelled, but not amplified Input-referred offset =(C2/C1) x VOS, & often C2<C1
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 7
on S2
off)
off S2
on)
Offset NOT cancelled, but not amplified Input-referred offset =(C2/C1)xVOS, & C2<C1
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 9
Sample mode (S1, S3, S5 on S2, S4 VC1=Vos VI1 , VC2=Vos-VI3, VC3=0 Vo=Vos
off)
Employs the previously discussed technique to eliminate the problem associated with high common-mode voltage excursion at the input of the opamp
Ref: S. H. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 13
Ref: S. H. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 14
Gain=4C/C=4 Input voltage common-mode level removed common-mode compliance Amplifier offset NOT removed
Ref: S. H. Lewis, et al., A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 15
Operation during offset cancellation phase shown Auxilary inputs added with Amain/Aaux.=10 During offset cancellation phase: Aux. amp configured in unity-gain mode: Vout=Vosmain on CAZ & canceled
offset stored
Ref: H. Ohara, et al., "A CMOS programmable self-calibrating 13-bit eight-channel data acquisition peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp. 930 - 938, December 1987.
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 16
Vout=gm1,2roVin1 + gm3,4roVin2
Ref: H. Ohara, et al., "A CMOS programmable self-calibrating 13-bit eight-channel data acquisition peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp. 930 - 938, December 1987.
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 17
+ -
Voffset
During offset cancellation phase AZ and S1 closed amplified by gm1/gm2 & stored on CAZ Auxiliary amp chosen to have lower gain so that:
Aux. amp charge injection associated with opening of switch AZ reduced by Aaux/Amain=1/10 Insignificant increase in power dissipation resulting from addition of aux. inputs
THD simulated w/o sampling switch boosted clock -45dB THD simulated with sampling switch boosted clock (see figure)
Ref: K. Vleugels et al, A 2.5-V SigmaDelta Modulator for Broadband Communications Applications IEEE JSSC, VOL. 36, NO. 12, DECEMBER 2001, pp. 1887
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 19
VCLK VO
Transition from track to hold: Occurs when device turns fully off VCLK=Vin+VTH Sharp fall-time wrt signal change no aperture error
Time
VCLK
Time
Ref: P. J. Lim and B. A. Wooley, "A high-speed sample-and-hold technique using a Miller hold capacitance," IEEE Journal of Solid-State Circuits, vol. 26, pp. 643 - 651, April 1991.
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 21
In general: Clock fall/rise trade-off between switch charge injection versus aperture error
Ref: P. J. Lim and B. A. Wooley, "A high-speed sample-and-hold technique using a Miller hold capacitance," IEEE Journal of Solid-State Circuits, vol. 26, pp. 643 - 651, April 1991.
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 22
What is ESD?
Electrostatic discharge Example: Charge built up on human body while walking on carpet... Charged objects near or touching IC pins can discharge through on-chip devices Without dedicated protection circuitry, ESD events could be destructive
[http://www.idt.com/docs/AN_123.pdf] [http://www.ce-mag.com/archive/03/ARG/dunnihoo.html]
Equivalent Circuit
Example:
vi R Cj vo CL
-80
-100
-100 10
6
-120 10
6
10
10 10 Input Frequency
10
10
10 10 10 Input Frequency
10
10
ADC Architectures
Slope type converters Successive approximation Flash Time-interleaved / parallel converter Folding Residue type ADCs
Two-step Pipeline
Oversampled ADCs
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 30
Resolution
..
Clock
Counter starts counting @ VRamp=0 Counter stops counting for VIN=VRamp Counter output proportional to VIN
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Disadvantages:
Slow (2N clock pulses for N-bit conversion) Hard to generate precise ramp Need to calibrate ramp slope versus VIN
..
VIN -VREF
Integrator
Vo "0" Clock
Counter
Flip Flop
First: VIN is integrated for a fixed time (2NxTCLK) Vo= 2NxTCLK VIN/intg Next: Vo is de-integrated with VREF until Vo=0 Counter output = 2N VIN /VREF
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 34
Sl
op
Co ns t.
http://www.maxim-ic.com/appnotes.cfm/appnote_number/1041
Integrate Vin for fixed time (TINT), de-integrate with TDe-Int ~ 2NxTCLKxVin/VREF VREF applied Most laboratory DVMs use this type of ADC
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 35
Disadvantage:
Slow (maximum 2x2NxTclk per conversion) Integrator opamp offset results in ADC offset (can cancel) Finite opamp gain gives rise to INL
VIN
T/H
1 MSB
VIN>VDAC?
0 MSB
VREF
DAC
1 [MSB-1] Y
Set DAC[MSB-1]=1
Control Logic
VIN>VDAC?
0 [MSB-1]
Clock
1 [LSB] Y
. . . . . .
VIN>VDAC?
0 [LSB]
DAC[Input]= ADC[Output]
VIN
VDAC/VREF
1
ADC 101000
3/4 5/8 11/16 21/32 41/64
VREF
DAC
1/2
Control Logic
V IN
High accuracy achievable (16+ Bits) Required N clock cycles for N-bit conversion (much faster than slope type) Moderate speed proportional to B (MHz range)
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 38
Out
Vin
To switches
Control Logic
T/H inherent in DAC Operation starts by connecting all top plate to gnd and all bottom plates to Vin To test the MSB all top plate are opened bottom plate of 32C connected to VREF & rest of bottom plates connected to ground input to comparator= -Vin +VREF/2 Comparator is strobed to determine the polarity of input signal if - MSB=1 if + MSB=0 The process continues until all bits are determined
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 39
VREF
Vin
Comparator
Out
Control Logic
VREF
Vin
To order parasitic (Cp) insensitive since top plate driven from initial 0 to final 0 by the global negative feedback Linearity is a function of accuracy of C ratios Possible to add a C ratio calibration cycle (see ref.)
Ref: H. Lee, D. A. Hodges, and P. R. Gray, "A self-calibrating 15 bit CMOS A/D converter," IEEE Journal of Solid-State Circuits, vol. 19, pp. 813 - 819, December 1984.
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 40
1st
Flash ADC
B-bit flash ADC:
DAC generates all possible 2B -1 levels 2B-1 comparators compare VIN to DAC outputs Comparator output:
If VDAC < VIN If VDAC > VIN 0 1 D A C
2B-1 B Encoder Digital Output VREF VIN fs
Comparator outputs form thermometer code Encoder converts thermometer to binary code
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 41
VIN VREF
fs
0 0 1 1 1 1 1
B-bits
Encoder
1 0 1
Time
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Flash Converter
VIN VREF
fs
High complexity: 2B-1 comparators Input capacitance of 2B-1 comparators connected to the input node:
High capacitance @ input node
EECS 247 Lecture 20: Data Converters
Encoder
B-bits Thermometer code
2006 H.K. Page 43
VIN
fs
Comparator input:
Offset Nonlinear input capacitance Kickback noise (disturbs reference) Signal dependent sampling time
Encoder
. . . . .
R R R/2
Digital Output
Comparator output:
Sparkle codes ( 111101000 ) Metastability
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 44
fs
8-bits
R/2 R R
VREF=1V
Encoder
. . . . .
R R R/2
Digital Output
V0 ffset =
3mV = 0.33mV W L
W L = 83 2
2 CGS = CoxW L = 496 fF 3 Total input capacitance: 255 0.496 = 126.5 pF ! Assuming: Cox = 9 fF / 2
Issues: Si area quite large Large input capacitance Since depending on input voltage different number of comparator input transistors would be on/off- total input capacitance varies as input varies Nonlinear input capacitance could give rise to signal distortion
Ref: M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid-State Circuits, vol. 24, pp. 1433 - 1439, October 1989.
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 46
Flash Converter
Comparator Tolerable Maximum Offset versus ADC Resolution
Note: Graph shows offset, note that depending on min acceptable yield, the derived offset numbers are associated with 2 to 6 offset voltage
Assumption: DNL=0.5LSB
102
10
VREF=2V VREF=1V
10-1 4
8 ADC Resolution
10
b3 b2 b1 b0
Output
0 1 1 1
Thermometer code 1-of-n decoding Final encoding NOR ROM Ideally, for each code, only one ROM row is on
Sparkle Codes
VDD
b3 b2 b1 b0
Correct Output: 1000 Problem: Two rows are on Erroneous Output: 0000
Meta-Stability
Different gates interpret metastable output X differently
0 0 0 1 X 1 1 0 1
1000 0000
Ref: C. Portmann and T. Meng, Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters, JSSC August 1996, pp. 1132-40
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 52
Gray Encoding
Thermometer Code T1 0 1 1 1 1 1 1 1 T2 0 0 1 1 1 1 1 1 T3 0 0 0 1 1 1 1 1 T4 0 0 0 0 1 1 1 1 T5 0 0 0 0 0 1 1 1 T6 0 0 0 0 0 0 1 1 T7 0 0 0 0 0 0 0 1 G3 0 0 0 0 1 1 1 1 Gray G2 0 0 1 1 1 1 0 0 G1 0 1 1 0 0 1 1 0 B3 0 0 0 0 1 1 1 1 Binary B2 0 0 1 1 0 0 1 1 B1 0 1 0 1 0 1 0 1
G1 = T1T3 + T5 T7 G2 = T2 T6 G3 = T4
Each Ti affects only one Gi Avoids disagreement of interpretation by multiple gates Protects also against sparkles Follow Gray encoder by (latch and) binary encoder
2006 H.K. Page 53
Number of students
6 5 4 3 2 1 0 33 38 41 43 44 45 46 47 48 49 50
Grade
EECS 247 Lecture 20: Data Converters 2006 H.K. Page 54