ir,

ffi

Experiment,

n
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OB.fECTIVES

BIPOLAR .TI'NCTTON TRAI{SISTOR DC BTASTNG

CONFIGURATIONS

To determine the quiescent operating conditions of fixed-bias emitter-stabilized bias and. volt.age divider bias BrtT configurations

To provide an additional insight into Ehe choice of point of a DC bias circuit using the graphical_ method. an operating
IIiIlf RODUCTORY INFORMAT I ON

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bias supplies. Each of Lhese circuit connections has specific advantages in some applications, but the common-emitter connection is by far the most widely used, part.ly because it is capable of more power gain t.han the others.

Transistors may be connected in three possible arrangements as shown in figure 8.1. These are r (1) common_emitter connection,. (Z) common-base connections,. and (3 ) common-co]l-ect,or connecLion. The connection depends on which t.ransistor terminal it is- connected to both

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(a)

(c)

Figure 8.1 (a)

BASETLA

cornmon

emitter amplif ier; (b) common base arnplifier; common collect.or amplifier
Conf

(c)

il

Experiment Manual Experiment B: B,JT DC Biasing

Page

1 of

igttratir:ns

1"4

!t

il il il

Many voltages and currents in a circuit, cont,aining a transistor are imporLant. in its operat.ion. The notation for operating currents and voltages of Lhe B,JT are present.ed in tab]e 8.1. rn order to distinguish easily a particular voltage or current for d,iscussion or to represent it in ar1 equation, letter symbols have been adopted as symbols for these cj-rcuit parameters. Uppercase l-etters are used for quantities that are constant, while l-owercase letters denote quantit,ies that can vary in va1ue. subscripts are also used to distinguish various circuit parameters that. are symbolized by uppercase and l-owercase l-etLer symbols.

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Table 8.1.
fB

ib
iB

rc
j

J-g

r ceo

Vc,
vce vca
\7 ce
"

il
il1

vcc
Vee

value fnstantaneous value of ac component of base currenL Instantaneous toEal base current Value of dc component of collector current Instantaneous toLal collector currenL Reverse collector-to-base current when emitter is open- c j-rcuited Average voltage beLween co1lector and emitt.er fnstantaneous val-ue of ac component of collectoremitter voltage Instantaneous total colfector-emitter voltage RMS value of ac component of col-Iect-or-emitter voltage,' rms of v.. Supply volt.age for col1ector circuit Supply voltage for base circuit

Transistor Current and Voltage Symbols Va1ue of dc component of base current, its average

fi
ilr ilr

There are generally two methods of evaluating a transistor circuit. The equivalent method, used by the design engineer and sometimes cal1ed the analytical- method, involves many mathematicalcomputations. The graphical method presents a picture of the operating characLeristics of the circuit as Lhe transistor is used with any value of Load resistance. By using Ohm's Law, Kirchoff's Law and the basic power equation you will have a visual presentation of the operational limits of the transistor as specified by Lhe manufacturer. For amplification with arr undistorted output signal and linear voltage gain, the transistor shouLd be biased in Ehe finear or active region. To do this, Lhe base-emitter junction shoufd be forward biased while the base-collector junct.ion shoufd be reverse biased. Biasing esLablishes a certain currenL and voltage condition in a transistor called a dc operating point, quiescent point or Q-point.. For a B.IT, this point is defined bY V6s and Is.
BJT DC Analysis

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f,
!

GR,APHfCAL METHOD

Ir
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,'
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A common-emitter amPlifier as shown in Figure 8.2 Provides high currenL gain; Lypical range of which is from 20 to 200.
Experiment Manual ExperimenL B: BJT DC Biasing Configurations Page 2 of 1"4
BASETLA

Figure 8.2

il

The out.put loop equation of the circuit voltage and current ploL as shown:
T - \r-- f ---vcE \ rc Rc

is a straight line in
(Equation 8.1)

il

-1

Vcc \ + ----/
Rg

il

where: * the ordinate (y-axis) is the collector current Ic * t.he abscissa (x-axis) is the collector-emitter currenL

VcE

il

* the slope is -t/R" * Vcc/Rc is the Y-intercePt

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The st.raight line representing Equation 8.1 can be drawn by ining two extreme PoinLs: d.ef 1' Set Ic = O, Vce = Vcc condition for cut-off 2. Set V6" = Q, Ic = Vcc/Rq condiLion for saLuraLion Equation B. l- is called the "DC load line equation" fot the When Lhis equation is plottsed on Lhe output collector circuit. characLeristic curveB, the resulting straighb line is cal1ed the DC The points shown in Figure B ' 3 and the load line for the circuit. The foad straight line connecting them is cafled the Dc l-oad fine. on the supply voltage, Vcc, and the value of the line depends only colfector resistoi, R6. Furthermore, as long as the DC-operaLing point is within the extreme points defined above, the transistor is oper:ating in the linear region.
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C,

xt.[,

vcc/Rc

DC load line

vcc

Vg3, volts
minimum
maxintum

Figure 8.3 of The foad line is constructed between the point and collector current cofl-ector voltage with Ehe maximum
BASETLA

ExPeriment Manua1 Experiment 8: B,JT DC Biasing Configurations

Page

3 of

14

I
collector voltage with minimum col-]ector current,. From line, you can determine all- of the possible operat.ing the construct.ed points t.hat can be employed.

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ANALYTICAL METHoD

Another method of eval-uating transisEor circuit is the analygical involves the basic transistor formulas. These mar-hemat.ical equations shows the relationship of rg, rc and fE when the transisLor operates in t.he active region.
met'hod Ehat

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where

Applying KCL to t.he transistor,

Ic is t.he col_lector current in milliamperes fB is the base current in microamperes

When the base-emitter junction of the transistor is forward biased, the base-emitter voltage VsB : 0.7 V for NpN , Si transistor (nquation 8.3) Vnn = 0,7 Y for pNp, Si transistor (Eguation 8.4)

rs is the emitter current ," ,,,1"rrr:rlf,.lj'

(Equation 8.2)

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T
T

The relationship between the collector current current due to majority carrier is expressed through the ancl emi-tter common-base short' circuit amplification factor, q. under AC condit.ion, o is defined as the ratio of Lhe change in collector current to the change in emitter current. fn equation form,

on" : 4-"
AIr
Under DC condit.ion, o is def ined as f ol]ows: : IC
CTDC

(Equation 8.5)

IE

(.Equation 8.6) fn transistor

data

The typical val-ue of . o ranges from 0.9 to 0.998 sheeE, o is referred to as hon.

rn solving for the

DC

colfector current in terms of o,

T -Lc - u DC T tE -

(Equation 8.7)

I
I
I

The relationship between the coll-ector current and base current due to majority carriers is expressed Lhrough the common emitter forward current amplification factor, B. under AC condition, p is defined as the ratio of the change in collector current Lo the change in base current.. fn equation form,
BASETI,A Experiment Manual Experiment 8: BJT DC Biasing Configurations

Page

4 of

1-4

il

I
il
il

oo"=ff
Under DC condition, B is defined as follows: IC o pDC = IB

(Equation

B. B)

(Equation 8.9) fn transistor

data

The typical value of B ranges from sheet, F is referred t.o as h"r.

5O

to 400

fn solving for t.he DC col-lector current

j_n

terms of F,

I
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I. :
DC

/J

orl,

(Equation 8.10)

Biasing Configuration

fn this experiment, we will investigate three BJT DC biasing configurations namely the Fixed Bias Circuit., Emitter-Stabilized Bias Circuit and Vo1t.age Divider Bias Circuit.
FTXED BIAS CIRCUTT

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The connection of a fixed bias circuit is For this bias configuration, the base current is shown in figure g.4. held fixed by the base resistance Ra. Therefore, a variation in B and temperature wiII cause a change in the collector current. and colfector-emitter transisEor. For this reason, it can be very difficult. voltage of the to predicr. the exact locat.ion of the e_point on the load 1ine of a Fixed_bias conf igurat.ion.
RC

+Vcc = 20 v
Otrms

Rg

2.2K

I'

56OK Ohms

1r*
'+ vcr

ll,,
Figure 8.4
For a Fixed- Bias circuit,
lD -

the

DC

base current i-s computed as

=

, -V." -V". v". - 0.7 Y "RB

-_=---:-

RB

(Equation 8.11)

BASETLA Experiment Manual_ Experiment B: B,TT DC Biasing Configurations

Page

5 of

r]..*

?
f: ' -.itr'l'-t

10 -b
${z

L4

D,;tlir

,;

r*

'7

j*'*r'

I
ilr"r",

for the

DC cot_lecror_emitter

voltage of the Lransistor resu.lts

f: f,

V"u

=V"" - I" R" =V"c

-flrR"

(Equation B.12)

The DC emitter current is obtained by applying xCL to the transistor,

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il

I, :I" *Iu = fl, +\

(f+1)IB

(Equation 8.13)

The coflector saturat,ion l_eve1 for the transist.or amplifier is obtained by setting Vce t.o 0V,

-V.. '.f'u, -

EI

(Eguation 8.14)

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The maximum colrect.or-emitter voltage for the transi_stor amplifier is the transisror ro !f,::iffi J.rrr:""", "rt-oir. when r" ='-o A rrom
V"u1org/

I I
I
I
I
I
I

Vcc

(Equation 8.15)

EMTTTER-STABTI,IZED BTAS

cIRcuIT

The emitter-stabilized bias emitter resistor, RE to i-mprove configuration in figure 8.5 contains over that of the fixed bias configuration. :1. "trritrty with the addition of variation in the dc currents and voltages R;, there wirl be a small of the transistor even when the temperature and transistor B changes.

I{"C

+vcc = 20 v
Ohms

Rs

L. 8K

560K ohms
+ !r BE_
1-

Jr"
'+
Ycr

RE Ohms

I1'"

Figure 8.5 For an emitter-stabil_ized ca]culat,ed as

BASETLA

bias circuit,

the

base current

1S

Experiment Manua1 Experiment B: B,JT DC niasing Configurations Page 6 of t4

ry
Ir= for rhe
V.. - V". Rn +(/+1)RE
DC cot

v.. - 0.7 V
R" +(/+1)RE

(Equation B.1G)

fla"r"n

lecror_emirter volrage of the transistor results

V"u:V"" - I. R" -IuRu =V"" fl" R" _(F+ I)IBRE (Equarion 8.17)
The collector saturation 1evel" is computed as
rr-V.. clsat) - -------=-

J-'t
(Equation
B. LBJ

R" + -ta a

The maximum collector_emitt.er voltage for the transistor amplifier obtained by driving the t.r.r"i=tor is to cut_off . When f. and fB from equat,ion B.1T is set to 0 A,
V.u1orrl =

V.c

(Equation 8.19)

VoLTAGE DTVIDER BTAS CTRCUTT

rn fixed-bias and emitter-stabir-ized bias configuration, the DC operating collector- current, rsp and the DC operating -correcitr-emitter voltage, Vcne of the transist'or is aepenaeit on B. Since increase in rlmperarure will chanse p is i"T:""1":"""i:i:::'?
" " Voltage Divider bias configuration . .::: " ;j.t. H: srrorn B.d, leve1 of rao changes ,h;a p changes,i;-;;;".e -operating even though rhe the point on rhJ-;". v.,e remains consranrthe ;:#::':l:::i; ir ";;
c

wh

h is

*o

:", "l,.li. jj"T. .'.

r"1i"

lil

r; : :",*"".JI;" Lr".:
+vcc = 2,a v
Ohms

rco

and

"',1;".:;T:'S"":1
Rnt
Ohms

R.C

sOK

.2K 1r"
1 +

?
Y

ltcr

$V'

V'p

L5K

Rga Ohms

v{, ,{&

*.t1'"
I r"
orrms
F r-gure

Page

Experiment Manual Experiment 8: B,tT DC Biasing

BASETLA

8.6

7 of

1"4

Con figurations

For the voltage_divider to figure 8.5, the DC t bias circuit, applying the voltage divider ""e ,o:_tlge of the circuit is computed as

rul_e

V : Vtc Rn' 'B-R,*R,

(Equation 8.20)

Knowing the value

of Vr, VE can be VE:V,

sol-ve using the equation

-Vns =VB -0.7V

(Equation B.2t)

BY Ohm's Iraw,

the

DC

emitter current

r-:fL "RSince
DC

(Equation 8.22)

base current, f" is too small, Ie ! Ic.

The DC coflector-emitter

voltage of the transi-stor resurts to

vru:v"" - I" R" -IuRu =vcc -I"(R. *Ru)

("nr"rion

e.23)

The maximum DC collector divider bias configuration current for .he transistor in a voltage is saturation. From equation 8.23, obtained by a.iri.rg the transistor to when Vqr1._.1 is set to 0 V T-V." ,c1sat1 (Equat,ion . B.Z4) R. . Ru
The maximum collector-emi-tter divider bias configuration is voltage for the transistor in a voltage obtained by driving the t.ransistor cut-off. From equation g.23, when Is to = 0 A, V"oton)

Vcc

(Equation 8.25)

MATERTAIJS REQUIRED

r 1 - DC Regulated power SuppIy t 2 -AnalogVOM/Digital voM r 1-560K0resistor r 1-30Keresistor I 1- l_5Ke resistor r 1- 2-2KA resi.stor . 1 - l_.8KA resistor I 1 - 1.2KA resistor r 1-lKeResistor r 1 - 2N3904 NpN Bipolar .Tunction Transistor r1-CurveTracer r 1 - Breadboard ! Connect,ing Wires
BASETLA Experiment Manuaf Experiment B: B,JT DC Biasing Configurations Page I of 14

PROCEDURE

FTXED-BIAS CTRCUTT

1. Connect, the circuit shown of the resist.ors to be used. in figure B .4 Measure t.he act.ual values RB (measured) = f't\ Vsl Rc (Mesaured) = _j4#2' Measure v"" and rs of the circuit. Note i-t down in table 8.2 3' compute for the r" of the circuit measured Vs, and Rs, Note it -uging equation 8.11. use the down in tabl_e B .2 4' compute for B using equation 8.9. This is value of B will be used for the 2N3904 transislo.ttfr.""girout the experiment.

B=

0-1

transisro'

5. Measure the

"i..".,i?:

"^n:".'ffi H:t;:i:"=*iX
Tabl.e

."*Ji""T.

6 ' compute for the theoreticaf currents of fixed bias circuit values of the DC operating voltages and usi'g introductory information. Note down the the equat.iorr= presented in the values in tabr-e 8.2.

r:t

r-he rixed-bias

Measured value

Theoretical vi-tue

B.2

& difference

fi"""llfX:i.:",

rhe sarurarion levet and cur_off fevel of rhe fixed_

rcsur
vc" (ort)

= f"ucl l"\
n

fa

" ,rW V

2N3904 NpN

7. Using the curve tracer, obtain the characteristic curve of the transistor. pfot it on graph 8.1.

Graph 8.1 Experiment. Manual Experiment B: BJT DC Biasing ConfiguratLons Page 9 of L4

BASETLA

B. Obt.ain t.he DC ]oad l-ine characteristic curve using the equat.ion presentedof the circuit on thej-nformation in the introductory 9. What is the region of operation of the transistor?
EMITTER-STABTLIZED BTAS CTRCUTT

10. Connect the circuit

shown in figure 8.5.

l-1 ' Measure the. DC operating voltages and current of the fi-xed_bias transistor circuit. Not.e dowi the va]ues in t.abf e 8.3 12. compute for the theoreticar varues the DC currenLs of emi-tEer-stabirized bias ofcircui-1 operating voltages and ," rhe inrroducrory inf ormariorr. *o." using Lhe equations down rhe values in :ffi:";:i.
.

Measured vafue

Table

Theoretical

value

& differenee

13. Compute for Lhe sat.urat.ion level and cut-off leve1 of Lhe emitterstabilized bias circuit.
Ic""t
Vce (ort
)

/1.,I -_-=\

"LL/'

74.

What.

is t.he region of operation of t.he transist.or?

shown

VOLTAGE-DTVTDER BTAS CTRCUIT

15. Connect the circuit

in figure 8.6.

1'6 ' Measure the DC operating voltages and divider bias transistoi circuil . Note down .hecurrent. of the voltage_ var.ues in table 8.4. 1"7 ' compute for the theoretical values the currenLs of emi-tter-stabirized bias ofcircuitDC operat.ing voltages and using the equations presented in the introduct.ory informat.ion. Note down the vafues in table 8.4
.

Measured value

Table

Theoretical vafue

tr
:B

& difference

ff

Experiment Manual Experiment B: BJT DC Biasing ConfiguL-ations Page 10 of L4

BASETLA

i
t
a

I
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I
I

18. Compute for the saturation ]evel and cut-off stabilized bias circuit.
fcsat
Vc" (otr)

leve] of the emitter-

ii

= fi;l*K
AL

19

what is the region of operation of the transistor?

il

GUIDE QUESTIONS

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l-. What is the purpose of the DC load l_ine? Describe the ..e,, point. Describe what happens when you increase the varue of road resisLance if t,he collector supply voltage remains constant. 4. What is biasing? 5 ' why is the transistor carled a current-controlr-ed device? 6' would you say that transistors are temperature sensitive? Explain. 7. What is meant by the st.ability factor of a circuit.? 8. What is a? what is What is ya Explain briefly. 9' Answel: the computer Bz simulation probleis in.Exerc:se B..DEsrcN oF BJT DC BTASING CTRCUIT
2. 3'

]I
.;

l
I ;

i
t

i:i

il
I ii
;l rl
rl

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I

li
l}
rii

iJ

1i ir

i i

BASETLA Experiment ManualExperimenE 8: BLTT DC Biasing Configurations Page l-l- of 14

I
Experiment 7: BIPOLAR Preliminary Report
.TI'}TTCTION TRANSISTOR DC BIASING CONFTGURATIONS

Laboratory fnstructor
Date Performed:
Group Leader: Group Members:

Grade:

fnstructor, s Sigiiq,tu.re lrrlz

l l

i4 ti. '-

|'
:

i
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,l
1

Dat.a and Results:

FTXED-BfAS CIRCU]T

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t
I
n
k

1' connect' the circuit shown of the resistors to be used. in figure 8.4. Measure the actua] values RB (measured) = j-q,fK.fL Rc (Mesaured) = --A.*7Tfn2' Measure V"" and rg of the circuit. Note it down in table 8.2 3' compute for the rB of the circuit using equation 8.11. use the measured vus and Rg. Note it down in table d.z' 4' compute for p using equation 8.9. This is varue of B will be used for the 2N3904 transisior throughout -the experiment. B =-__La+::'5' Measure the .DC operating transist.or circuit.. Not.e dor.^in voltages and current. of ,/"nu fixed-bias the values in t.able B .2. 6 ' compute for the theoreticarcurrents of fixed bias circuit. values of the DC operat.ing voltages and using the .qr.tio.r= presented in the introductory information. Note down the values in table 8.2. Table B.2 Measured vafue Theoretical value & difference

5' compute for the saturation r-ever and cut-off level of the fixed_ bias circuit.
rcsar
BASETLA

?"

l|n#
i

Experiment Manuaf Experiment B: B,jf DC Biasing Configurations Page 12 of 1_4

l-8. Compute for the saturation LeveL and cut-off Level of the emiLterstabilized bias circuit
fc"at
Vce =

(ott)

19. What is the region of operation of the transistor?

GUTDE QUES"IONS
1". 1

Describe what happens when you increase the value of r-oad resistance if the collector supply voltage remains constant. 4. What is biasing? 5. why is the transistor car-led. a current,-controlr"ed device? 6. would you say that transistors are temperature sensiti.ve? Explain. 7- what is meant by the stability factor of a circuit? B. What, is cx? Whar is Bz What is y? Explain briefly. 9. computer simulation problems in Exercise B : BJr Dc .#ff;:;".tnt
3.

thra i: rhe purpoee of rhe DC toad tine? Describe the ',e,, point..

.
: r

,.:,i ,irl -,1

jl

.1.11

',,I
1

.,i

+oi

Experiment ManualExperj-ment 8: BJT DC Biasing Configuratjons Page L1 of i"4

BASETLA

t
il il
il il il il
il il
il

il
vcs (otr
l

i
I

f***"

7. Using the curve tracer, obtain the characteristic curve of the 2N3904 NpN transistor. plor-i;-o., graph 8.1.

?t\)

*n/
t

Graph 8.1
8 '" obtain the DC r-oad r-ine using the equation presentedof the circuit. on the characLeristic curve in the introauctory information. 9. what is the region of operation of the transistor?

EMTTTER-STABTLTZED BTAS CIRCUTT

I
t
I
I

1L' Measure the. DC operaLing voltages and current of the fixed_bias t.ransistor circuit. Note Aowi tne values in table 8.3. 72. compute for the theoreticarthe currents of emitter-stabir-ized va]ues ofcircuilDC operating vortages and bias using the equations '" rhe inrroducrorv inf ormarion. lrote down rhe values in iffi:";:i.
Measured value
Tabl.e

Theoretical

val-ue

& difference

13. Compute for the saturation fevel and cut-off stabilized bias circuit.

]eve] of the emitter-

= c i/ft vcB(otr) = flfi t/

rcsat

!4.

What is the region of operation of the traFsistor?

/
Experiment Manual Experiment B: BLTT DC Biasing ConfiguratLons Page 13 of 14
BASETLA

VOLTAGE-DIVIDER B1AS CIRCUTT

1'6 ' Measure the DC operat.ing divider bias transistor circuii. voltages and current of .he voltage_ Note down the varues in table 8.4. L7 - compute for the theoret.icarvar-ues of the DC operating voltages and currents of emitter-stabilized bias circuit using the equations ," Ehe inrroducrory informarion. Nore down rhe vatues i4 i:;i:"::i.

Measured value

Table

lheoret.ical value

& difference

l"B. Compute for the saturation level and cut-off leve1 of the emit,ter_ stabilized bias circuit.
rcsat
vco

=
=

t,*ll /

(orr)

dat/

19

What is the region of operation of the transi st or?

I
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il
rj rj

il
i

i
{
L

fl
Experiment Manual Experiment B: B.TT DC Biasing Configurations Page 14 of t4
BASETLA

$,

:r

il

iI

[- ifi
*
DEsrcN

o"

_ui _),irrr2 "ii*i;,:?.:^f:,,t.;;,;E.:".1:"1:? use a L6 v jc lir^nr, :f - irJ_ NpN siii.o,, uir"f;. ,i*,r"J. ;:,,, circuir ffiff;ff";. ,,:::.JI:l;,i-

Design an emir ?r*A, 7.62v. #'JJ..J

"otI";:riiolr*n

crRcurr

;.

;;.j;:

usins

Z.

l-::iS" a voltage divider bias ci rr,, j + .,^r 2N2222 NpN alri"on rransisro_"il:y1a using a suppry of 24v,
-

, !i::ol?i"' simur.are your cirquit

iff

.::,

i;:ii lil":"J' : iT'' tn."'" "' U -;;;fi.;: +: "; uslns ;;;?:;,

-1'

=:

,.rr.S"r.1fjJJ,.i*rr.