EE 224

Digital Circuit Design MOS Rams

A common logic need is memory

Small amounts of memory are built with latches and flip flops
4Store values used in logic
Registers in microprocessors Cursors in graphics chips

Large amounts of memory require circuit design

4DSP microcode storage
EE 224 notes Morris Jones

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Memory Terms
Word
4A collection of bits that are read/written together
8 bits

Address
4A collection of bits that are used to specify which word in the RAM is to be read or written
EE 224 notes Morris Jones

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Ram terms
Bit or Cell
4A location in the ram that stores digital information. 4A bit is a single binary digit 4Cell stores one bit in 2 level systems. It may store more bits in multi-level systems
All commercial RAMs are single bit per cell types CCDs store data in analog, and are 6 -8 bits/cell
EE 224 notes Morris Jones

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Ram Concepts

10110001 Address 12 words

word Cells This is called a 12 X 8 RAM

Words (8 bits)
EE 224 notes Morris Jones

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Ram Organization
Rows

Address

Decoder

Cells

Bit lines MUX Word

EE 224 notes Morris Jones

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Ram Architecture
Ram organized into Rows and Bits.
4Rows contain one or more words 4Bits are multiplexed to word size

Address is decoded into Row lines

4Uses NOR decode mostly in NMOS
Keeps the transistors small May be clocked and not true CMOS

4CMOS uses mostly NAND decoders

EE 224 notes Morris Jones

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Output MUX
Some address bits may go to output mux
4Select bits in the desired word 4These address bits are often faster than other address bits

Also contains a sense circuit to detect Cell values

4Simple RAM may not have an output MUX
EE 224 notes Morris Jones

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RAM Design Goals

Low Cost Large Bit Size High Speed Easy to manufacture

EE 224 notes Morris Jones

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Cost of A RAM
Memory cells desired

Address Decoder

Overhead not desired by logic customer

EE 224 notes Morris Jones

Sense Amplifiers & MUX

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Ram Cost
P = 2W + 2L A = WL 2W + 2 L Metric = WL Cells = WL L= C W 2W + 2C W

First Order estimate of efficiency comes from perimeter vrs area Perimeter is overhead, and area is valuable cells

C dMetric 2 2CW 2 = =0 dW C 2 2 = 2 C W W= C
EE 224 notes Morris Jones

Metric =

Square RAMS are the most Cost effective! Number of Rows= Number of Bits
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Example
A designer desires a 1024 location by 8 bit RAM. What is the best internal organization for the RAM. Number of Cells = 8 X 1024=>8192 Cells SQRT(8192) =>90.5 Cannot make this work in Powers of 2, pick the closest power of 2 64 Rows, and 128 bits -- or -128 Rows, and 64 bits

EE 224 notes Morris Jones

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Whats in a Cell
vdd vdd vdd

Resistor Style

NMOS Style

CMOS Style

Dynamic Style

EE 224 notes Morris Jones

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Dynamic Cell
Charge is stored on a capacitor
4May be parasitic Capacitance 4Dynamic Rams use this type of Cell

Challenge is to get enough capacitance and keep the cell size quite small Cell has no active gain or VDD path!

EE 224 notes Morris Jones

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NMOS Resistive Cell

Uses NMOS resistive inverters Resistors need large resistance
4RAM will have a large number of bits 4One resistor is always pulled to ground 4There are many Cells

Uses a second highly resistive Poly

4Several Meg Ohms
EE 224 notes Morris Jones

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NMOS Cell
Uses NMOS inverters One always has a path to ground To keep power low, W/L of load must be very small
4Requires a large device

EE 224 notes Morris Jones

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CMOS Cell
2 N and 2 P transistors No static Power Requires both N and P diffusions
4Larger area for spacing

EE 224 notes Morris Jones

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Getting In and out of the Cell

Connect a cell to a bit line with a pass transistor
4N transistor use most of the time 4Gate connects to the word line

Can read out the Cell value Can write in a new Cell value

EE 224 notes Morris Jones

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Connecting to a Bit/Word line

Bit Line

vdd

Word Line

EE 224 notes Morris Jones

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Word Lines
Decode with Nor/Nand structures Run address and not address down side of RAM Connect appropriate phases to transistors May pre-decode 2 bits to 4 to save transistor height
EE 224 notes Morris Jones

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Word Lines
Often, Dynamic decode used
4Follow with inverter if necessiary

Clocked drive often used to prevent decode glitches from getting into the cells
4Ram needs timing generation

Need high drive, and large devices

EE 224 notes Morris Jones

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Bit Lines
A single Bit line goes to a large number of cells Has much load and noise Often there are two bit lines
4Use differential Sense Circuit 4Makes writes easier

EE 224 notes Morris Jones

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Two Bit lines

Bit Line vdd Bit Line

Word Line

EE 224 notes Morris Jones

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Writing the Cell With 2 Bit lines

Normally the Pass Transistors are N Must overcome the P transistors Need a transfer curve that gets the voltage below the N threshold

EE 224 notes Morris Jones

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Pass Transistor Sizing Equation

Vdd CI 0V PN

5V

Target is <VT N
VDS=VGS-VT for P VDS<VGS-VT for N

EE 224 notes Morris Jones

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A simple Ram Cell Design

4/2 4/2

Minimum size devices for cost

8/2 4/2 4/2

Initial Conditions Only

EE 224 notes Morris Jones

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Transfer Curve for Input

EE 224 notes Morris Jones

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Transient Response

EE 224 notes Morris Jones

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Schematic with 128 bits on the Cell

Set M to 127 for other loads on the bit line Ram Cell 1, bit lines 0
EE 224 notes Morris Jones

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Now, simulate with 127 more cells

The Cell resets due to the capacitance being at 0V!!

EE 224 notes Morris Jones

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The Balancing Act

How to write the cell without resetting it!
4Enough DC path that the cell can be set 4Protection from AC resets with the capacitance

EE 224 notes Morris Jones

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Some solutions
Separate Read and Write lines
4Write the Cell with one transistor size 4Read with another transistor
Takes up a lot of area Can buffer the output with a transistor
Often done in multi-rams

Pre-charge the Bit lines for read

4Make the N transistors Large, the P small
Write by overdriving the P, read using N
EE 224 notes Morris Jones

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Some Solutions (Pre-charging)

Make N and P different sizes
4Write by over driving P 4Read by using only the N transistor, and pulling the bit lines high first

Set P and N pass transistor for write condition Set N inverter transistor for read speed Make Pass transistor smaller
EE 224 notes Morris Jones

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Boost the Drive on the N

Lowering VM eases the problems with the P, but worsens the problem with the N on read!!! Take it down near 2V The N Pass and Inverter N will split the voltage.
EE 224 notes Morris Jones

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Beef Ns up to 10/2

10/2
EE 224 notes Morris Jones

127 pass transistors

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Simulation Result with Bigger Ns

20ns read time (It did read though!)

EE 224 notes Morris Jones

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Speeding Up the RAM

Just making the Transistors bigger
4Helps some 4But also increases the load from other Cells 4Increases the cost

Use a differential sense amplifier

4Smaller voltage swing
EE 224 notes Morris Jones

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Speeding up the Ram

Make the Pass transistors minimum size
4This is what is done most often 4Make the P weaker by increasing L

Most rams have Minimum size Pass and use differential sense amplifiers to reduce voltage swing
EE 224 notes Morris Jones

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Bus Conditioner
Sets the Bus to a voltage level the sense amps can work with
vdd bit

bit

Set the Bit Voltage so the Sense amp works the best!

Current source made with a weak N transistor in saturation

EE 224 notes Morris Jones

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A Simple Sense Amp

VDD

Out bit bit

Output needs to be converted to a logic level

EE 224 notes Morris Jones

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Another Sense Amp

Vdd

OUT In In

EE 224 notes Morris Jones

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Sense Amp issues

Speed vrs noise sensitivity Bit line conditions before reading Static power dissipated
4Ram may have hundreds of sense amps

Speed power tradeoff Area and size

4Must fit the pitch of the bit lines from the cells
EE 224 notes Morris Jones

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