Standard Products

UT699 32-bit Fault-Tolerant SPARCTM V8/LEON 3FT Processor

Data Sheet September 6, 2011

FEATURES Implemented on a 0.25mCMOS technology Flexible static design allows up to 66MHz clock rate 89 DMIPS throughput via 66MHz base clock frequency Internally configured clock network On-board programmable timers and interrupt controllers High-performance fully pipelined IEEE-754 FPU Power saving 2.5V core power supply 3.3V I/O compatibility Hardened-by-design flip-flops and memory cells Separate instruction and data cache architecture 10/100 Base-T Ethernet port for VxWorks development Integrated PCI 2.2 compatible core Four integrated multi-protocol SpaceWire nodes with two supporting the RMAP protocol Two CAN-compliant 2.0 bus interfaces Multifunctional memory controller -40oC to +105oC operating case temperature range Operational environment: - Intrinsic total-dose: 100 krad(Si) and 300 krad(Si) - SEL Immune >108 MeV-cm2/mg Packaging options: - 352-pin Ceramic Quad Flatpack, weight 31.5 grams - 484-pin Ceramic Land Grid, Column Grid and Ball Grid Array packages Standard Microcircuit Drawing 5962-08228 - QML Q and V Applications - Nuclear power plant controls - Critical transportation systems - High-altitude avionics - Medical electronics - X-Ray cargo scanning

INTRODUCTION The UT699 is a pipelined monolithic, high-performance, faulttolerant SPARCTM V8/LEON 3FT Processor. The UT699 provides a 32-bit master/target PCI interface, including a 16 bit user I/O interface for off-chip peripherals. A compliant 2.0 AMBA bus interface integrates the on-chip LEON 3FT, SpaceWire, Ethernet, memory controller, cPCI, CAN bus, and programmable interrupt peripherals. The UT699 is SPARC V8 compliant; compilers and kernels for SPARC V8 can therefore be used industry standard development tools. A full software development suite is available including a C/C++ cross-compiler system based on GCC and the Newlib embedded C-library. BCC includes a small run-time kernel with interrupt support and Pthreads library. For multi-threaded applications, a SPARCTM compliant port of the eCos real-time kernel, RTEMS 4.6.5, and VxWorks 6.x is supported.

1.0 Introduction
The UT699 LEON 3FT processor is based upon the industry-standard SPARC V8 architecture. The system-on-chip incorporates the SPARC V8 core and the peripheral blocks indicated below. The core and peripherals communicate internally via the AMBA (Advanced Microcontroller Bus Architecture) backplane. This bus is comprised of the AHB (Advanced High-speed Bus) which is used for high-speed data transfer, and the APB (Advanced Peripheral Bus) which is used for low-speed data transfer.

IEEE754 FPU
MUL/DIV

LEON 3FT
2x4K D-cache 2x4K I-cache

Debug Support Unit

Serial/JTAG Debug Link

4x SpW

PCI Bridge

CAN-2.0

MMU

AHB interface

AMBA AHB AHB Ctrl Memory Controller AHB/APB Bridge UART AMBA APB Timers IrqCtrl I/O port Ethernet MAC

8/32-bits memory bus

512 MB PROM 512 MB I/O Up t o1GB SRAM Up to 1GB SDRAM

Figure 1. UT699 Functional Block Diagram

The LEON 3FT architecture includes the following peripheral blocks: LEON3 SPARC V8 integer unit with 8kB instruction cache and 8kB of data cache IEEE-754 floating point unit Debug support unit UART and JTAG debug links 8/16/32-bit memory controller with EDAC for external PROM and SRAM 32-bit SDRAM controller with EDAC for external SDRAM Timer unit with three 32-bit timers and watchdog Interrupt controller for 15 interrupts in two priority levels 16-bit general purpose I/O port (GPIO) which can be used as external interrupt sources AMBA AHB status register Up to four SpaceWire links with RMAP on channels 3and 4 Up to two CAN controllers Ethernet with support for MII cPCI interface with 8-channel arbiter

2.0 Pin Identification and Description

Pin Function I IS O I/O OD PCI-I PCI-O PCI-I/O PCI-3 2.1. System Signals Pin Number Pin Name Function 352 CQFP SYSCLK RESET ERROR1 WDOG1 I IS OD OD 88 136 142 145 484 CLGA Y20 L19 K19 J19 Description CMOS input CMOS input Schmitt CMOS output CMOS bi-direct CMOS open drain PCI input PCI output PCI bi-direct PCI three-state

Reset Value -----

Description

Main system clock System reset Processor error mode indicator. This is an active low output. Watchdog indicator. This is an active low output.

Notes: 1. This pin is actively driven low and must be tied to VDD through a pull-up resistor.

2.2 Address Bus Pin Number Pin Name Direction 352 CQFP ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] ADDR[7] ADDR[8] ADDR[9] O O O O O O O O O O 1 2 4 5 6 7 9 10 11 12 484 CLGA W5 Y5 W6 AA5 Y6 AB5 W7 AA6 Y7 AA7

Reset Value low low low low low low low low low low

Description

Bit 0 of the address bus Bit 1 of the address bus Bit 2 of the address bus Bit 3 of the address bus Bit 4 of the address bus Bit 5 of the address bus Bit 6 of the address bus Bit 7 of the address bus Bit 8 of the address bus Bit 9 of the address bus

Pin Number Pin Name Direction 352 CQFP ADDR[10] ADDR[11] ADDR[12] ADDR[13] ADDR[14] ADDR[15] ADDR[16] ADDR[17] ADDR[18] ADDR[19] ADDR[20] ADDR[21] ADDR[22] ADDR[23] ADDR[24] ADDR[25] ADDR[26] ADDR[27] O O O O O O O O O O O O O O O O O O 16 17 18 19 21 22 23 24 26 27 28 29 31 32 33 34 38 39 484 CLGA AB6 W8 AB7 Y8 AA8 W9 AB8 Y9 W10 AB9 Y10 AA9 W11 AA10 Y11 AB10 AB11 AA11

Reset Value low low low low low low low low low low low low low low low low low low

Description

Bit 10 of the address bus Bit 11 of the address bus Bit 12 of the address bus Bit 13 of the address bus Bit 14 of the address bus Bit 15 of the address bus Bit 16 of the address bus Bit 17 of the address bus Bit 18 of the address bus Bit 19 of the address bus Bit 20 of the address bus Bit 21 of the address bus Bit 22 of the address bus Bit 23 of the address bus Bit 24 of the address bus Bit 25 of the address bus Bit 26 of the address bus Bit 27 of the address bus

2.3 Data Bus Pin Number Pin Name Direction 352 CQFP DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] I/O I/O I/O I/O I/O I/O I/O 43 45 46 47 48 50 51 484 CLGA W12 W13 Y12 AA13 AA12 AB13 W14

Reset Value high-z high-z high-z high-z high-z high-z high-z

Description

Bit 0 of the data bus Bit 1 of the data bus Bit 2 of the data bus Bit 3 of the data bus Bit 4 of the data bus Bit 5 of the data bus Bit 6 of the data bus

Pin Number Pin Name Direction 352 CQFP DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13] DATA[14] DATA[15] DATA[16] DATA[17] DATA[18] DATA[19] DATA[20] DATA[21] DATA[22] DATA[23] DATA[24] DATA[25] DATA[26] DATA[27] DATA[28] DATA[29] DATA[30] DATA[31] I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 52 53 57 58 59 60 62 63 64 66 67 68 69 71 72 73 74 78 79 80 81 83 84 85 86 484 CLGA AA14 Y13 W15 AB15 Y14 AB14 W16 AA18 Y15 AB16 AA15 AB17 AA16 AA19 W17 AB18 Y16 Y17 AA17 W18 AB19 Y19 AB20 Y18 AA20

Reset Value high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z

Description

Bit 7 of the data bus Bit 8 of the data bus Bit 9 of the data bus Bit 10 of the data bus Bit 11 of the data bus Bit 12 of the data bus Bit 13 of the data bus Bit 14 of the data bus Bit 15 of the data bus Bit 16 of the data bus Bit 17 of the data bus Bit 18 of the data bus Bit 19 of the data bus Bit 20 of the data bus Bit 21 of the data bus Bit 22 of the data bus Bit 23 of the data bus Bit 24 of the data bus Bit 25 of the data bus Bit 26 of the data bus Bit 27 of the data bus Bit 28 of the data bus Bit 29 of the data bus Bit 30 of the data bus Bit 31 of the data bus

2.4 Check Bits Pin Number Pin Name Direction 352 CQFP CB[0] CB[1] CB[2] CB[3] CB[4] CB[5] CB[6] CB[7] 2.5 Memory Control Signals Pin Number Pin Name Direction 352 CQFP WRITE OE IOS ROMS[0] ROMS[1] RWE[0] RWE[1] RWE[2] RWE[3] RAMOE[0] RAMOE[1] RAMOE[2] RAMOE[3] RAMOE[4] RAMS[0] RAMS[1] O O O O O O O O O O O O O O O O 98 99 102 103 104 105 108 109 110 111 112 113 114 115 117 118 484 CLGA V21 U19 T20 V22 U20 U22 T19 T22 T21 V20 R21 R20 R22 R19 P22 P20 I/O I/O I/O I/O I/O I/O I/O I/O 89 90 91 92 93 94 96 97 484 CLGA V19 AA21 Y21 W19 Y22 W20 W22 W21

Reset Value high-z high-z high-z high-z high-z high-z high-z high-z

Description

Bit 0 of EDAC checkbits Bit 1 of EDAC checkbits Bit 2 of EDAC checkbits Bit 3 of EDAC checkbits Bit 4 of EDAC checkbits Bit 5 of EDAC checkbits Bit 6 of EDAC checkbits Bit 7 of EDAC checkbits

Reset Value high high high high high high high high high high high high high high high high

Description

PROM and I/O write enable strobe PROM and I/O output enable I/O area chip select PROM chip select PROM chip select SRAM write enable strobe SRAM write enable strobe SRAM write enable strobe SRAM write enable strobe SRAM output enable SRAM output enable SRAM output enable SRAM output enable SRAM output enable SRAM chip select SRAM chip select

Pin Number Pin Name Direction 352 CQFP RAMS[2] RAMS[3] RAMS[4] READ BEXC BRDY 2.6 SDRAM Pin Number 352 CQFP O O O O O O O O O O 41 124 125 126 128 129 131 132 133 134 484 CLGA AB12 N22 N20 N21 M21 M22 L21 M20 L20 L22 O O O O I I 119 120 123 139 140 141 484 CLGA P21 P19 N19 K20 K22 K21

Reset Value high high high high ---

Description

SRAM chip select SRAM chip select SRAM chip select SRAM, PROM, and I/O read indicator Bus exception Bus ready

Pin Name Direction SDCLK SDRAS SDCAS SDWE SDCS[0] SDCS[1] SDDQM[0] SDDQM[1] SDDQM[2] SDDQM[3] 2.7 CAN 2.0 Interface

Reset Value high high high high high high high high high high SDRAM clock

Description

SDRAM row address strobe SDRAM column address strobe SDRAM write enable SDRAM chip select SDRAM chip select SDRAM data mask SDRAM data mask SDRAM data mask SDRAM data mask

Pin Number Pin Name Direction 352 CQFP CAN_RXD[0] CAN_TXD[0] CAN_RXD[1] CAN_TXD[1] I O I O 146 147 148 150 484 CLGA J20 J22 J21 H22

Reset Value -high -high

Description

CAN receive data CAN transmit data CAN receive data CAN transmit data

2.8 Debug Support Unit (DSU) Pin Number Pin Name Direction 352 CQFP DSUACT DSUBRE DSUEN DSURX DSUTX 2.9 JTAG Interface Pin Number Pin Name Direction 352 CQFP TRST TMS TCK TDI TDO 2.10 Ethernet Interface Pin Number Pin Name Direction 352 CQFP EMDC ERX_CLK EMDIO ERX_COL ERX_CRS ERX_DV ERX_ER ERXD[0] ERXD[1] ERXD[2] O I I/O I I I I I I I 163 166 167 168 169 171 172 173 174 175 484 CLGA E22 D22 D20 E21 E20 D21 C21 C22 B21 C20 I I I I O 156 157 160 161 162 484 CLGA F20 F21 G22 F22 F19 O I I I O 151 152 153 154 155 484 CLGA H19 H20 G19 G20 G21

Reset Value low ---high

Description

DSUmode indicator DSU break DSU enable DSU UART receive data DSU UART transmit data

Reset Value ----undef JTAG reset

Description

JTAG test mode select JTAG clock JTAG test data input JTAG test data output

Reset Value low -high-z --------

Description

Ethernet media interface clock Ethernet RX clock Ethernet media interface data Ethernet collision error Ethernet carrier sense detect Ethernet receiver data valid Ethernet reception error Ethernet receive data Ethernet receive data Ethernet receive data

Pin Number Pin Name Direction 352 CQFP ERXD[3] ETXD[0] ETXD[1] ETXD[2] ETXD[3] ETX_CLK ETX_EN ETX_ER 2.11 General Purpose I/O Pin Number Pin Name Direction 352 CQFP GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 191 192 193 194 196 197 198 199 254 255 256 257 259 260 261 262 484 CLGA B17 C17 A17 D17 C16 D16 C15 D15 C7 B5 D7 A5 D6 C5 C6 D5 I O O O O I O O 176 177 178 179 180 182 184 185 484 CLGA B20 C19 C18 B18 B19 A19 A18 A20

Reset Value -low high low high -low low

Description

Ethernet receive data Ethernet transmit data Ethernet transmit data Ethernet transmit data Ethernet transmit data Ethernet TX clock Ethernet transmit enable Ethernet transmit error. Always driven low.

Reset Value high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z

Description

Bit 0 of general purpose I/O Bit 1 of general purpose I/O Bit 2 of general purpose I/O Bit 3 of general purpose I/O Bit 4 of general purpose I/O Bit 5 of general purpose I/O Bit 6 of general purpose I/O Bit 7 of general purpose I/O Bit 8 of general purpose I/O Bit 9 of general purpose I/O Bit 10 of general purpose I/O Bit 11 of general purpose I/O Bit 12 of general purpose I/O Bit 13 of general purpose I/O Bit 14 of general purpose I/O Bit 15 of general purpose I/O

2.12 SpaceWire Interface Pin Number Pin Name Direction 352 CQFP SPW_CLK SPW_RXS[0] SPW_RXD[0] SPW_TXS[0] SPW_TXD[0] SPW_RXS[1] SPW_RXD[1] SPW_TXS[1] SPW_TXD[1] SPW_RXS[2] SPW_RXD[2] SPW_TXS[2] SPW_TXD[2] SPW_RXS[3] SPW_RXD[3] SPW_TXS[3] SPW_TXD[3] 2.13 UART Interface Pin Number Pin Name Direction 352 CQFP RXD TXD I O 223 224 484 CLGA C12 C11 I I I O O I I O O I I O O I I O O 221 205 206 207 208 212 213 214 215 234 235 236 237 242 243 244 245 484 CLGA A11 A16 A15 B16 B15 A14 A13 B14 B13 A9 A8 B9 B8 A7 A6 B7 B6

Reset Value ---low low --low low --low low --low low

Description

SpaceWire clock SpaceWire receive strobe SpaceWire receive data SpaceWire transmit strobe SpaceWire transmit data SpaceWire receive strobe SpaceWire receive data SpaceWire transmit strobe SpaceWire transmit data SpaceWire receive strobe SpaceWire receive data SpaceWire transmit strobe SpaceWire transmit data SpaceWire receive strobe SpaceWire receive data SpaceWire transmit strobe SpaceWire transmit data

Reset Value -high

Description

UART receive data UART transmit data

2.14 PCI Address and Data Bus Pin Number Pin Name Direction 352 CQFP PCI_AD[0] PCI-I/O 266 484 CLGA AA2

Reset Value high-z

Description

Bit 0 of PCI address and data bus

10

Pin Number Pin Name Direction 352 CQFP PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O 267 268 269 270 272 273 274 279 280 281 284 285 286 287 288 305 306 307 308 309 310 312 313 317 318 321 322 323 324 326 484 CLGA AA3 Y1 Y2 Y3 W1 W2 W3 V2 V3 U1 U2 U3 T1 R2 R1 J1 K2 K1 G1 H3 H2 F1 F2 E1 E2 F3 D1 D2 E3 D3

Reset Value high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z

Description

Bit 1 of PCI address and data bus Bit 2 of PCI address and data bus Bit 3 of PCI address and data bus Bit 4 of PCI address and data bus Bit 5 of PCI address and data bus Bit 6 of PCI address and data bus Bit 7 of PCI address and data bus Bit 8 of PCI address and data bus Bit 9 of PCI address and data bus Bit 10 of PCI address and data bus Bit 11 of PCI address and data bus Bit 12 of PCI address and data bus Bit 13 of PCI address and data bus Bit 14 of PCI address and data bus Bit 15 of PCI address and data bus Bit 16 of PCI address and data bus Bit 17 of PCI address and data bus Bit 18 of PCI address and data bus Bit 19 of PCI address and data bus Bit 20 of PCI address and data bus Bit 21 of PCI address and data bus Bit 22 of PCI address and data bus Bit 23 of PCI address and data bus Bit 24 of PCI address and data bus Bit 25 of PCI address and data bus Bit 26 of PCI address and data bus Bit 27 of PCI address and data bus Bit 28 of PCI address and data bus Bit 29 of PCI address and data bus Bit 30 of PCI address and data bus

11

Pin Number Pin Name Direction 352 CQFP PCI_AD[31] 2.15 PCI Control Signals Pin Number Pin Name Direction 352 CQFP PCI_RST PCI_CLK PCI_C/BE[0] PCI_C/BE[1] PCI_C/BE[2] PCI_C/BE[3] PCI_PAR PCI_FRAME1 PCI_IRDY1 PCI_TRDY1 PCI_STOP1 PCI_DEVSEL1 PCI_IDSEL PCI_REQ PCI_GNT PCI_HOST PCI-I PCI-I PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-I/O PCI-3 PCI-3 PCI-3 PCI-3 PCI-3 PCI-I PCI-O PCI-I PCI-I 265 293 275 289 302 316 290 301 300 299 295 296 315 329 328 330 484 CLGA C3 C2 V1 P2 H1 G2 P1 L1 L2 M1 N1 M2 G3 A4 B2 AB3 PCI-I/O 327 484 CLGA C1

Reset Value high-z

Description

Bit 31 of PCI address and data bus

Reset Value --high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z -high-z --PCI reset input PCI clock input

Description

PCI bus command and byte enable PCI bus command and byte enable PCI bus command and byte enable PCI bus command and byte enable PCI parity checkbit PCI cycle frame indicator PCI initiator ready indicator PCI target ready indicator PCI target stop request PCI device select PCI initialization device select PCI request to arbiter in point to point configuration PCI bus access indicator in point to point configuration PCI host enable input (Connect to SYSEN in PCI bus)

Notes: 1. This pin must be tied to VDD through a pull-up resistor as specified in the PCI Local Bus Specification Revision 2.1 Section 4.3.3.

12

2.16 PCI Arbiter Pin Number Pin Name Direction 352 CQFP PCI_ARB_REQ[0] PCI_ARB_REQ[1] PCI_ARB_REQ[2] PCI_ARB_REQ[3] PCI_ARB_REQ[4] PCI_ARB_REQ[5] PCI_ARB_REQ[6] PCI_ARB_REQ[7] PCI_ARB_GNT[0] PCI_ARB_GNT[1] PCI_ARB_GNT[2] PCI_ARB_GNT[3] PCI_ARB_GNT[4] PCI_ARB_GNT[5] PCI_ARB_GNT[6] PCI_ARB_GNT[7] PCI-I PCI-I PCI-I PCI-I PCI-I PCI-I PCI-I PCI-I PCI-O PCI-O PCI-O PCI-O PCI-O PCI-O PCI-O PCI-O 331 332 337 339 343 344 348 350 333 336 338 342 345 347 349 351 484 CLGA B4 AB4 Y4 T3 P3 M3 K3 C4 B3 AA4 W4 R3 N3 L3 J3 A3

Reset Value --------high-z high-z high-z high-z high-z high-z high-z high-z

Description

PCI arbiter bus request PCI arbiter bus request PCI arbiter bus request PCI arbiter bus request PCI arbiter bus request PCI arbiter bus request PCI arbiter bus request PCI arbiter bus request PCI arbiter bus grant PCI arbiter bus grant PCI arbiter bus grant PCI arbiter bus grant PCI arbiter bus grant PCI arbiter bus grant PCI arbiter bus grant PCI arbiter bus grant

2.17 Power and Ground Pins (352 CQFP) Pin Number Pin Name 352 CQFP VDD 3, 15, 25, 35, 40, 44, 54, 65, 75, 87, 95, 106, 116, 127, 135, 137, 149, 158, 170, 181, 190, 200, 203, 211, 217, 222, 226, 229, 233, 241, 247, 251, 263, 271, 283, 292, 294, 304, 314, 325, 335, 346 484 CLGA B1, B10, B12, B22, E7, E9, E14, E16, F6, F10, F13, F17, G5, G9, G14, H6, H8, H10, H13, H15, J7, J16, J18, K5, K8, K15, K17, L6, M6, N5, N8, N15, N17, P7, P16, P18, R6, R8, R10, R13, R15, T5, T9, T14, U6, U9, U11, U12, U14, U17, V10, V13, AA1, AA22 I/O supply voltage Description

13

Pin Number Pin Name 352 CQFP VSS 8, 20, 30, 42, 49, 61, 70, 82, 107, 130, 138, 159, 183, 187, 195, 204, 216, 219, 225, 230, 238, 246, 250, 258, 264, 278, 282, 303, 311, 334, 352 484 CLGA A1, A12, A22, B11, C8, C10, C13, D4, D9, D14, D18, D19, E4, E6, E10, E13, E17, E19, F4, G4, G8, G11, G12, G15, G17, H4, H7, H16, H18, J2, J4, J9, J14, K4, K10, K13, L7, L11, L12, L17, M7, M11, M12, M17, N4, N10, N13, P4, P9, P14, R4, R7, R16, R18, T2, T4, T8, T15, T17, U4, U10, U13, V4, V5, V8, V11, V12, V15, V18, AB1, AB22 A2, A21, D10, D13, E5, E11, E12, E18, F8, F15, G7, G10, G13, G16, G18, H5, H9, H11, H12, H14, H17, J6, J8, J15, K7, K16, L4, L8, L15, L18, M4, M8, M15, M18, N7, N16, P6, P8, P15, R5, R9, R11, R12, R14, R17, T7, T10, T13, T16, T18, U8, U15, V6, V17, AB2, AB21 A10, C9, C14, D11, D12, E8, E15, F5, F7, F9, F11, F12, F14, F16, F18, G6, H21, J5, J10, J11, J12, J13, J17, K6, K9, K11, K12, K14, K18, L5, L9, L10, L13, L14, L16, M5, M9, M10, M13, M14, M16, M19, N6, N9, N11, N12, N14, N18, P5, P10, P11, P12, P13, P17, T6, T11, T12, U5, U7, U16, U18, U21, V7, V9, V14, V16 D8 N2 I/O supply ground (pins 187/D19 and 264/D4 must be tied to VSS) Description

VDDC

14, 37, 56, 77, 101, 122, 144, 165, 186, 188, 201, 209, 220, 227, 232, 239, 249, 252, 276, 297, 319, 340

Core supply voltage

VSSC

13, 36, 55, 76, 100, 121, 143, 164, 189, 202, 210, 218, 228, 231, 240, 253, 277, 298, 320, 341

Core supply ground

N/C Unused

248 291

This pin must be left floating This pin must be tied to VDD through a 10k pull-up resistor

14

3.0 AC and DC Electrical Specifications

3.1 Absolute Maximum Ratings1 Symbol VDDC VDD VIN PD2 TJ3 JC Description Core supply voltage I/O supply voltage Input voltage any pin Maximum power dissipation permitted @ TC = 105oC Junction temperature Thermal resistance, junction to case 352 CQFP 484 CLGA/CCGA/CBGA TSTG ESDHBM Storage temperature ESD protection (human body model) Class 2 Min -0.3 -0.3 VSS - 0.3 -Max 3.6 4.3 VDD + 0.3 9 Units V V V W

----65 2000

150 5 5 150 --

oC/W

Notes: 1. Stresses greater than those listed in the following table can result in permanent damage to the device. These parameters cannot be violated. 2. Per MIL-STD-883, Method 1012, Section 3.4.1, PD = (TJ(max)-Tc(max))/JC 3. Maximum junction temperature may be increased to 175oC during burn-in and steady-static life testing.

15

3.2 Recommended Operating Conditions VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC) Symbol VDDC VDD VIN TC tR tF Description Core supply voltage I/O supply voltage Input voltage any pin Case operating temperature Rise time, all CMOS and PCI inputs Fall time, all CMOS and PCI inputs Min 2.3 3.0 0 -40 --Max 2.7 3.6 VDD 105 20 20 Units V V V
oC

ns ns

16

3.3 Power Supply Operating Characteristics (pre- and post-radiation) VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC) Symbol IDDC1,2 Description Active core power supply current Conditions VDDC = 2.7V, VDD= 3.6V For 25MHz < fSYSCLK < 66MHz All other clock inputs running at fSYSCLK VDDC = 2.7, VDD = 3.6V For 25MHz < fSYSCLK < 66MHz All other clock inputs running at fSYSCLK VDDC = 2.7V, VDD= 3.6V fSYSCLK = 0MHz, fETH_CLK = 0MHz fPCI_CLK = 0MHz, fSPW_CLK = 0MHz TC = -40oC and 25oC TC = 105oC IDDS Standby I/O power supply quiescent current VDDC = 2.7V, VDD = 3.6V fSYSCLK = 0MHz, fETH_CLK = 0MHz, fPCI_CLK = 0MHz, fSPW_CLK = 0MHz VDDC = 2.7V, VDD = 3.6V fSYSCLK = 66MHz, fETH_CLK = 0MHz fPCI_CLK = 0MHz, fSPW_CLK = 0MHz 300k post rad IPD4 I/O power supply current power-down mode VDDC = 2.7V, VDD = 3.6V fSYSCLK = 66MHz, fETH_CLK = 0MHz fPCI_CLK = 0MHz, fSPW_CLK = 0MHz 20 0.75 mA Max 27 Units mA/MHz

IDD1,3

Active I/O power supply current

0.75

mA/MHz

IDDCS

Standby core power supply current

mA

IPDC4

Core power supply current power-down mode

2.75

mA/MHz

5 0.75 mA/MHz

Notes: 1. During this measurement the processor is executing the Dhrystone benchmark. 2. This measurement includes the contribution due to IDDCS. 3. This measurement includes the contribution due to IDDS. 4. Power-down mode is entered by performing a WRASR instruction wr %g0, %asr19.

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3.4 DC Characteristics for LVCMOS3 Inputs (pre- and post-radiation) (VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC) Symbol VIH VIL VT+ VTVH IIN Description High-level input voltage Low-level input voltage Positive going threshold voltage for Schmitt inputs Negative going threshold voltage for Schmitt inputs Hysteresis voltage for Schmitt inputs Input leakage current VIN = VDD VIN = VSS CIN1 Input pin capacitance f = 1MHz; VDD = 0V, VDDC = 0V 352 CQFP 484 CLGA Conditions Min 0.7VDD --0.3VDD 0.4 --1 --Max -0.3VDD 0.7VDD --1 -19 16 pF Units V V V V V A

Notes: 1. Capacitance is measured for initial qualification and when design changes might affect the input/output capacitance.

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3.5 DC Characteristics for LVCMOS3 Outputs (pre- and post-radiation) (VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC) Symbol VOH1 Description High-level output voltage IOH = -100A IOH = -12mA VOL Low-level output voltage IOL = 100A IOL = 12mA IOZ Three-state output current VO = VDD VO = VSS IOS2 Short-circuit output current VO = VDD; VDD = 3.6V VO = VSS; VDD = 3.6V COUT3 Output pin capacitance f = 1MHz; VDD = 0V, VDDC = 0V 352 CQFP 484 CLGA Conditions Min VDD-0.25 2.4 ---10 -10 --65 --Max -V -0.25 V 0.4 10 10 130 -16 16 pF mA A Units

Notes: 1. Except open-drain output. 2. Supplied as a design limit. Neither guaranteed nor tested. 3. Capacitance is measured for initial qualification and when design changes might affect the input/output capacitance.

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3.6 AC Electrical Characteristics for LVCMOS3 Inputs and Outputs (pre- and post-radiation) (VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC) Symbol fCLK tHIGH tLOW tDSD1 tRSD2 Description System clock frequency System clock high time System clock low time System clock to SDRAM clock propagation delay SDRAM clock rise time fCLK = 66MHz VO transitioning between VOH (min) and VOL (max) fCLK = 66MHz VO transitioning between VOH (min) and VOL (max) fCLK = 66MHz Conditions Min -6.67 6.67 2 -Max 66 --5 2 Units MHz ns ns ns ns

tFSD2

SDRAM clock fall time

--

ns

tJCCSD2

SDRAM clock cycle-cycle jitter

--

500

ps

Notes: 1. Tested as shown in Figure 14. 2. Supplied as a design limit. Neither guaranteed nor tested.

1/fCLK tHIGH SYSCLK tLOW

tDSD SDCLK

tDSD

Figure 2. System Clock and SDCLK Timing Diagram

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3.7 DC Electrical Characteristics for PCI Inputs (pre- and post-radiation) (VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC) Symbol VIH VIL IIN Description High-level input voltage Low-level input voltage Input leakage current VIN = VDD VIN = VSS CIN1 Input pin capacitance f = 1MHz; VDD = 0V, VDDC = 0V 352 CQFP 484 CLGA Conditions Min 0.5VDD ---10 --Max -0.3VDD 10 -19 22 pF Units V V A

Notes: 1. Capacitance is measured for initial qualification and when design changes might affect the input/output capacitance.

3.8 DC Electrical Characteristics for PCI Outputs (pre- and post-radiation) (VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC) Symbol VOH VOL IOZ Description High-level output voltage Low-level output voltage Three-state output current IOH = -500A IOL = 1500A VO = VDD VO = VSS IOS1 Short-circuit output current VO = VDD; VDD = 3.6V VO = VSS; VDD = 3.6V COUT2 Output pin capacitance f = 1MHz; VDD = 0V, VDDC = 0V 352 CQFP 484 CLGA Conditions Min 0.9VDD --10 -10 --130 --Max -0.1VDD 10 10 270 -19 22 pF mA Units V V A

Notes: 1. Supplied as a design guideline. Neither guaranteed nor tested. 2. Capacitance is measured for initial qualification and when design changes might affect the input/output capacitance.

3.9 AC Electrical Characteristics for PCI Inputs (pre- and post-radiation)

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(VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC) Symbol fPCI_CLK tHIGH tLOW Description PCI clock frequency PCI clock high time PCI clock low time Conditions Min -11 11 Max 33 --Units MHz ns ns

1/fPCI_CLK tHIGH PCI_CLK tLOW

Figure 3. PCI Clock Timing Diagram

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4.0 Timing Specifications

4.1 Power Sequencing and Reset (VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC) Symbol tVCD1 tVHBZ1 Description VDD valid to VDDC delay VDD valid to control signals high-z (WRITE, OE, IOS, ROMS[1:0], RWE[3:0], RAMOE [4:0], READ SDWE, and SDCS[1:0]) VDD valid to outputs high-z ([DATA[31:0], CB[7:0], and GPIO[15:0]) tCHBV1 VDDC valid to control signals valid-inactive (WRITE, OE, IOS, ROMS[1:0], RWE[3:0], RAMOE [4:0], READ SDWE, and SDCS[1:0]) VDDC valid to RESET deassert RESET deasserted to outputs valid-active (ROMS[0] and OE) RESET asserted to control signals validinactive (WRITE, OE, IOS, ROMS[1:0], RWE[3:0], RAMOE [4:0], READ SDWE, and SDCS[1:0]) RESET asserted to outputs high-z (DATA[31:0], CB[7:0], and GPIO[15:0])
Notes: 1. Guaranteed by design. 2. Guaranteed by design for control signals.

Conditions VDD > 3.0V; VDDC > 2.30V VDD > 1.5V; VDDC = 0V

Min 0 --

Max -4

Units ns tCLK

VDD > 3.0V; VDDC > 2.30V

--

tCLK

tRESET11 tRESET2 tRESET32

VDDC > 2.30V

4 ---

-12 4

tCLK tCLK tCLK

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SYSCLK VDD 3.3V OV tVCD VDDC 2.5V OV tRESET1 RESET tCHBV tVHBZ Memory Bus Control Signals tVHBZ Tri-State Outputs VALID-ACTIVE tRESET2 VALID-INACTIVE VALID-ACTIVE tRESET3 VALID-INACTIVE tRESET3

Figure 4. Power Sequencing and Reset Timing Diagram 4.1.1. Power Sequencing Proper power sequencing of the UT699 is achieved by bringing up VDD to its recommended minimum operating voltage of 3.0V, and then delaying tVCD clock cycles before bringing up the VDDC supply. If power is applied to the VDDC supply pins while VDD is less than 3.0V, excessive current or damage to the device could occur. 4.1.2 Bus Control and Bi-Direct Fail-Safe Circuitry In order to prevent bus contention on the external memory interface while VDDC is ramping up, the UT699 has functionality to ensure that the bi-direct and memory bus control signals described in Section 4.1 will be in a high-z state tVHBZ clock cycles after VDD reaches 1.5V. The core logic will then put these signals into their valid-inactive states tCHBV clock cycles after VDDC reaches 2.3V. It is recommended that users place pull-up resistors on the indicated output enable, write enable, and chip select pins, and a pulldown resistor on the READ pin, if there will be a significant delay between when VDD and VDDC reach their recommended operating voltages. This will prevent bus capacitance or transients from inadvertently placing these pins in an active state, which could result in external memory devices driving the address and data buses. 4.1.3 Reset Circuitry The reset circuitry is controlled by the core logic; therefore, the circuitry is functional only after VDDC reaches its minimum operating voltage of 2.3V. After VDDC is stable, the system must continue to assert RESET for a minimum of tRESET1 clock cycles before it can be de-asserted. Asserting RESET for less time could result in the RESET signal not being recognized.

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The UT699 will begin fetching code from external memory no more than tRESET2 clock cycles after RESET is de-asserted. Control signals ROMS[0] and OE will be driven to their valid-active states in order for the UT699 to begin fetching code from PROM. During normal operation, the indicated bus control signals will go to a valid-inactive state, and the bi-directs will go to a high-z state, within tRESET3 clock cycles after the assertion of RESET. 4.1.4 Programming Pins GPIO[2:0] Data on pins GPIO[2:0] are latched on the rising edge of reset. The states of these pins determine the data width of the PROM area, and enable EDAC for the PROM area. Chapter 3 of the Users Manual describes the value of these inputs to achieve the required operation. In order for the state of GPIO[2:0] to be properly latched, it is recommended to place pull-up or pull-down resistors on these pins to ensure that the setup and hold timing is met. The states of these pins should be statically set prior to the rising edge of RESET. 4.2 Output Timing Characteristics for Memory Interface, ERROR, and WDOG (VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC) Symbol t11 Description SDCLK to output valid (ADDR[27:0], WRITE, OE, IOS, ROMS[1:0], RWE [3:0], RAMOE [4:0], RAMS[4:0], READ, SDRAS, SDCAS, SDWE, SDCS[1:0], and SDDQM[3:0]) SDCLK to output valid (DATA[31:0] and CB[7:0]) SDCLK to output high-Z (DATA[31:0] and CB[7:0]) SDCLK to signal low (ERROR and WDOG) WRITEor RWE[3:0]to output high-z (DATA [31:0] and CB[7:0]) Skew from first memory output signal transition to last memory output signal transition Min 2 Max 8 Units ns

t21 t31,2 t41 t81,2 t91

2 2 2 2.5 -

8 8 9 2

ns ns ns ns ns

Notes:
1. All outputs are measured using the load conditions shown in Figure 14. 2. High-Z defined as +/-300mV change from steady state.

25

SDCLK t1 t9 All Outputs (Except Bi-Directs and Open-Drains) WRITE and RWE[3:0] t8 t2 DATA[31:0] and CB[7:0] (Bi-Direct Outputs) t4 ERROR and WDOG (Open-Drain Outputs) t3

Figure 5. Memory Interface, ERROR, and WDOG Output Timing Diagram 4.3 Input Timing Characteristics for Memory Interface (VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC) Symbol t51 t61 t72 Description Setup time to SDCLK (DATA[31:0], CB[6:0], BEXC, and synchronous BRDY) Hold time from SDCLK (DATA[31:0], CB[6:0], BEXC, and synchronous BRDY) Asynchronous BRDY pulse width Min 0 1 1.5 Max Units ns ns tCLK

Notes: 1. CB[7] is not used for EDAC and is not tested 2. Guaranteed by design. .

SDCLK t5 All Inputs (Except Async BRDY) t7 Asynchronous BRDY t6

Figure 6. Memory Interface Input Timing Diagram

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4.4 Timing Characteristics for General Purpose Input / Output (GPIO) (VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC) Symbol t101 Description SDCLK to GPIO output valid (GPIO[15:0]) Min 2 Max 8 Units ns

Notes: 1. All outputs are measured using the load conditions shown in Figure 14.

SDCLK t10 GPIO[15:0]

Figure 7. General Purpose I/O Timing Diagram

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4.5 Timing Characteristics SpaceWire Interface (VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC) Symbol t111 t122 t132 t143 t153 t16 SPW_CLK period SPW_CLK to data delay (SPW_TXD[3:0]) SPW_CLK to strobe delay (SPW_TXS[3:0]) Transmit data and strobe bit width variation (SPW_TXD[3:0] and SPW_TXS[3:0]) Receive data and strobe bit width (SPW_RXD[3:0] and SPW_RXS[3:0]) Receive data and strobe edge separation (SPW_RXD[3:0] and SPW_RXS[3:0]) Description Min 5 3 3 UI-6004 2.5 2.5 Max -7 7 UI+600 --Units ns ns ns ps ns ns

Notes: 1. The SPW_CLK frequency must be less than 4x the SYS_CLK frequency. For example, if SPW_CLK is running at 200MHz, the SYS_CLK frequency must be greater than 50MHz. 2. All outputs are measured using the load conditions shown in Figure 14. 3. Applies to both high pulse and low pulse. 4. A unit interval (UI) is defined as the nominal, or ideal, bit width.

t11 SPW_CLK t14 SPW_TXD t14 SPW_TXS t13 t13 t12 t12

Figure 8. SpaceWire Transmit Timing Diagram

t t15 SPW_RXD t16 SPW_RXS t16 t t15

Figure 9. SpaceWire Receive Timing Diagram

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4.6 Timing Characteristics for PCI Interface (VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC) Symbol t171 Description PCI_CLK to output valid (PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR, PCI_FRAME, PCI_IRDY, PCI_TDRY, PCI_STOP, PCI_DEVSEL, PCI_REQ, and PCI_ARB_GNT[7:0]) PCI_CLK to output valid from high-z (PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR, PCI_FRAME, PCI_IRDY, PCI_TDRY, PCI_STOP, and PCI_DEVSEL PCI_CLK to output high-Z (PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR, PCI_FRAME, PCI_IRDY, PCI_TDRY, PCI_STOP, and PCI_DEVSEL Setup time to PCI_CLK (PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR, PCI_FRAME, PCI_IRDY, PCI_TDRY, PCI_STOP, PCI_DEVSEL, PCI_IDSEL, PCI_GNT, and PCI_ARB_REQ[7:0]) Hold time from PCI_CLK (PCI_AD[31:0], PCI_C/BE[3:0], PCI_PAR, PCI_FRAME, PCI_IRDY, PCI_TDRY, PCI_STOP, PCI_DEVSEL, and PCI_IDSEL) PCI_RST active time after power stable PCI_RST active time after PCI_CLK stable PCI_RST active to output float delay Min 2 Max 13 Units ns

t181,2

13

ns

t191,2

--

14

ns

t20

--

ns

t21

--

ns

t223 t233 t243

1 100 --

--40

ms us ns

Notes: 1. All outputs are measured using the load conditions shown in Figure 14. 2. High-Z defined as +/-300mV change from steady state. 3. Guaranteed by design.

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PCI_CLK t17 All Outputs t18 Bi-Direct and Tri-State Outputs t21 t20 All Inputs t19

Figure 10. PCI Timing Diagram

PCI_CLK VDD 3.3V 0V t23 t22 PCI_RST t24 Tri-State Outputs

Figure 11. PCI Reset Timing Diagram

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4.7 Timing Characteristics for Ethernet Interface (VDD = 3.3V + 0.3V; VDDC = 2.5V + 0.2V; TC = -40oC to 105oC) Symbol t251 t262 t272 t281 t294 t304 Description ETX_CLK to output valid (ETXD[3:0], and ETX_EN) Setup time to ERX_CLK (ERX_DV4ERX_ER, and ERXD[3:0]) Hold time from ERX_CLK (ERX_DV4ERX_ER, and ERXD[3:0]) EMDCto output valid (EMDIO) Setup time to EMDC(EMDIO) Hold time from EMDC(EMDIO) fEMDC= 123KHz3; fSYSCLK = 25MHz Conditions Min 2 1 Max 8 -Units ns ns

--

ns

2 10 5

11 ---

ns ns ns

Notes: 1. All outputs are measured using the load conditions shown in Figure 14. 2. ERX_COL and ERX_CRS are asynchronous inputs and are not tested. 3. fEMDC = fSYSCLK / 202. 4. Guaranteed by design.

ETX_CLK t25 All Outputs ERX_CLK t26 All Inputs t27

Figure 12. Ethernet Transmit and Receive Timing

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EMDC t28 EMDIO (Output) t29 EMDIO (Input) t30

Figure 13. Ethernet MDIO Interface Timing 4.8 Test Conditions for Timing Specifications

VDD

VDD

CL

Figure 14. Equivalent Load Circuit for Timing Characteristics Tests CL = 50 pF for ATE test load CL =15 pF for benchtop test load

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5.0 Operational Environment

The UT699 processor includes the following SEU mitigation features: * Register file SEU error-correction of up to 1 error per 32-bit word * Cache memory error-detection of up to 4 errors per tag or 32-bit word * Autonomous and software transparent error handling * No timing impact due to error detection or correction.

Table 1. Operational Environment Parameter

Total Ionizing Dose (TID) Single Event Latchup (SEL) 1, 2 Neutron Fluence
Notes: 1. The UT699 is latchup immune to particle LETs >108 MeV-cm2/mg. 2. Worst case temperature and voltage of TC = +105oC, VDD = 3.6V, VDDC = 2.7V. 3. Contact factory for error rate information.

Limit
3E5 >108 1.0E14

Units
rads(Si) MeV-cm2/mg n/cm2

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6.0 Packaging

Figure 15. 352-lead Ceramic Quad Flatpack with Top-Brazed Leads

34

Figure 16. 484-lead Ceramic Land Grid Array

35

Figure 17. 484-lead Ceramic Column Grid Array

36

Figure 18. 484-lead Ceramic Ball Grid Array

37

7.0 Ordering Information

UT699 LEON 3FT UT699 * * *
Lead Finish: (NOTE 1) (C) = Gold (A) = Hot Solder Dipped or Tinned

Screening Level: (NOTE 2 & 3) (P) = Prototype (Temperature Range: 25oC only) (E) = HiRel (Temperature Range: -40oC to +105oC)

Case Outline: (X) = 352-Ceramic Quad Flat Package, Top Brazed (Z) = 484-Ceramic Land Grid Array (S) = 484-Ceramic Column Grid Array (C) = 484-Ceramic Ball Grid Array

UT699 32-bit LEON 3FT

Notes: 1. Lead finish (A or C) must be specified. 2. Prototype Flow per Aeroflex Manufacturing Flows Document. Devices are tested at 25oC only. Radiation is neither tested nor guaranteed. 3. HiRel Flow per Aeroflex Manufacturing Flows Document. Radiation is neither tested nor guaranteed.

Package Option (X) 352-CQFP (Z) 484-CLGA (S) 484-CCGA (C) 484-CBGA

Associated Lead Finish (C) Gold (C) Gold (A) Hot Solder Dipped (A) Hot Solder Dipped

38

UT699 LEON 3FT: SMD 5962 * 08228 ** * * *

Lead Finish: (NOTE 1) (C) = Gold

Case Outline: (NOTE 2) (X) = 352-Ceramic Quad Flat Package, Top Brazed (Y) = 484-Ceramic Land Grid Array Package Screening Level: (Q) = QML Class Q (V) = QML Class V Device Type: (01) = UT699 (Temperature range: -40oC to +105oC) Drawing Number: 08228 Total Dose: (R) = 1E5 rad(Si) (F) = 3E5 rad(Si) Federal Stock Class Number: No Options

Notes: 1. Lead finish is C (gold) only. 2. Aeroflex offers Column Attachment as an additional service for the Ceramic Land Grid Array (Case outline "Y"). If needed, please ask for COLUMN ATTACHMENT when submitting your request for quotation.

39

Aeroflex Colorado Springs - Datasheet Definition

Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel

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Aeroflex Colorado Springs, Inc., reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties.

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