Introduction

A wide range of static combinational and sequential circuits were introduced in the previous chapters. Static logic circuits allow versatile implementation of logic functions based on static or steady state, behavior of simple nmos or cmos structure. In other words all valid output levels in static gates are associated with steady state operating points of the circuit in question. Hence, a typical static logic gate generates its output corresponding to the applied input voltages after a certain time delay, and it can preserve its output level as long as the power supply is provided. This approach however may require a large number of transistors to implement a function, and may cause a considerable time delay. In high density, high performance digital implementation where reduction of circuit delay and silicon area is major objective, dynamic logic circuits offers several significant advantages over static logic circuits. The operation of all digital logic gates depends on temporary storage of charge in parasitic node capacitance, instead of relying on steady state circuit behavior. This operational property necessity periodic updating of internal node voltage levels, since storage charge in capacitor cannot be retained indefinitely. Consequently, dynamic logic circuits require periodic clock signals in order to control charge refreshing. The capability of temporarily storing the state, i.e., a voltage level, at capacitive node allows us to implement very simple sequential circuits with memory functions. Also, the use of common clock signal throughout the system enables us to synchronize the operation of various circuit blocks. As a result, dynamic circuit techniques lend themselves well to synchronize logic design. Finally, the digital logic implementation of complex function generally requires smaller silicon area than does the static logic implementation. As for the power consumption which increases with the parasitic capacitance, the dynamic circuit implementation in a smaller area will, many cases consumes less power than the static counterpart, despite its use of clock signals.

PRINCIPLES OF PASS TRANSISTOR CIRCUITS Basic principles of pass transistor circuits

The fundamental building blocks of nmos dynamic logic circuits, consisting of an nmos pass transistor driving the gate of another nmos transistor.

Figure.1: nMOS Dynamic D-latch

The pass transistor MP is driven by the periodic clock signal and acts as an access switch to either charge up or charge down the parasitic capacitance CX depending on the input signal Vin. Thus, the two possible operations when the clock signal is active (CK=1) are the logic 1 transfer and the logic 0 transfer. In either case, the output of the depletion load nmos inverter obviously assumes a logic low or a logic high level, depending on the voltage VX. Notice that the pass transistor MP provides the only current path to the intermediate capacitive node X. when the clock signal becomes inactive (CK=1), the pass transistor ceases to conduct and the charge stored in the parasitic capacitance CX, continuous to determine the output level of the inverter.

Logic 1 transfer
Assumes that the soft node voltage is equal to zero inititally, i.e.,VX(t=0)=0 volts. A logic 1 level is applied to the input terminal, which corresponds to Vn=VOH=VDD. Now, the clock signal at the gate of the pass transistor goes from 0 to VDD at t=0. It can be seen that the pas transistor MP starts to conduct as soon as the clock signal becomes active and that MP will operate in saturation throughout this cycle. Since Vgs = Vds. Consequently, Vds>Vgs-Vtn. The circuit to be analyzed for the transfer event can be simplified into the equivalent circuit as shown in Figure.2.

Figure.2: Equivalent circuit for logic 1 transfer

The pass transistor MP operating in the saturation region starts to charge up capacitor CX. Thus,

Integrating the above equation with t from 0t and VX from 0Vx, we have

Therefore,

This equation can be solved for Vx, as follows

The variation of node voltage VX from the above equation is plotted as a function of time as shown in Figure.3.

Figure.3: Variation of node voltage as a function of time during logic 1 transfer.

The voltage rises from its initial value of 0 volts and approaches a limit value for large t, but it cannot exceed its limit value of Vmax=VDD-VTMP. The pass transistor will turn off when Vx=Vmax, since at this point, gate to source voltage will be equal to threshold voltage. Therefore the voltage at node X can never attain the full power supply voltage level of VDD during the logic 1 transfer. The actual value of max possible voltage Vmax at node can be found by taking into account the substrate bias effect for MP.

Thus, the voltage VX which obtained at node X following the logic 1 transfer can be considerably lower than the VDD. Pass transistors in series: The node voltages in the pass transistor chain during logic 1 transfer are as shown in the figure.4

Figure.4: Node voltages in a pass transistors chain during logic 1 transfer.

With threshold voltage of all transistors are same, the node voltage at the end of the pass transistor chain will become one threshold voltage lower than VDD, regardless of number of pass transistors in chain. Pass transistors driving gate of another Pass transistors: Node voltages during the logic 1 transfer, when each pass transistor is driving another pass transistor are as shown in figure.5. In designing nMOS pass transistors logic, one must never drive a pass transistor with the output of another pass transistor.

Figure.5: Node voltages during logic 1 transfer, when each pass transistors is driving another pass transistor.

Logic 0 Transfer
If the that soft node voltage is equal to 1 initially, i.e., Vx(t = 0) = Vmax = (VDD VT,n). Logic 0 level is applied to the input terminal, which corresponds to Vin = 0 V. When CK changes from 0 to 1, MP will be in linear region. The equivalent circuit for logic 0 transfer is shown in figure.6.

Figure.6: Equivalent circuit for logic 0 transfer

The direction of current flow through will be opposite to that during charge-up event.The pass transistor MP operating in the linear region discharges the parasitic capacitor Cx as follows:

Integrating above equation w.r.t. t we get,

Variation of node voltage Vx w.r.t. last equation is plotted as function of time is shown in figure.7.

Figure.7: Variation of node voltage as a function of time during logic 0 transfer

Fall time for the soft node voltage Vx can be calculated from previous equation.

Advantages of pass transistors are: They are not ratiod devices and can be minimum geometry They do not have a path from plus supply to ground, do not dissipate standby power They are used as function block. Charge Storage & Charge Leakage During inactive clock phase (when Ck = 0), the charge leakage from the soft node is shown in figure.8.

Figure.8: Charge leakage from the soft node.

Assume that logic high voltage has transferred to soft node during CK = 1 and now both Vin and CK = 0. The charge stored in Cx will gradually leak away, primarily due to the leakage currents associated with the pass transistor. Gate current of the inverter driver transistor is negligible. Figure.9 shows the simplified cross-section of the nMOS pass transistor, showing the leakage components responsible for draining the soft capacitance Cx.

Figure.9:Cross-section of the nMOS pass transistor.

The leakage current is given by

The certain portion of total soft-node capacitance Cx is due to reverse biased drainsubstrate junction, which is also a function of soft-node voltage Vx. The equivalent circuit used for analyzing the charge leakage process is shown in figure.10.

Figure.10:Analyzing the charge leakage process

VOLTAGE BOOTSTRAPPING
Voltage bootstrapping is a technique used for overcoming threshold voltage drops in digital circuits. Consider the circuit shown in figure.11, where voltage Vx _ VDD, M2 will operate in saturation. When Vin = 0, Vout(max) = Vx - VT2(Vout)

Figure.11: Enhancement-type circuit in which output node is weakly driven.

To overcome threshold voltage drop and to obtain VDD at output node, Vx must beincreased. In figure.12 third transistor M3 is added.

Figure.12: During bootstrapping arrangement to boost Vx, during switching.

The two capacitor Cs and Cboot represent capacitances which dynamically couple the voltage Vx to the ground and to the output. The circuit will produce a high Vx during switching, so threshold voltage can be overcome at the output node. Vx _ VDD + VT2(Vout) Initially Vin = 1, M1 is in linear region & M2 in saturation and output voltage is low. Since ID3 = 0, Vx = VDD - VT3(Vx) If input switches from 1 to 0 at t = 0, M1 turns off and Vout will start to rise. The change in output voltage level will now be coupled to Vx through bootstrap capacitor Cboot. The transient current flowing through Cs and Cboot is

Cs is the sum of parasitic source-to-substrate capacitance of M3 and gate-to-substrate capacitance of M2. To obtain large Cboot in comparison to Cs, an extra dummy transistor is added to the circuit as shown in figure.13. The dummy transistors drain and source terminals are connected together, it acts as an MOS capacitor between Vx and Vout.

Figure.13: Realization of the bootstrapping capacitor with a dummy MOS device.