Abdulkalam Institute of Technological Sciences

Vepalagadda, Kothagudem 507120

Department of Electronics and Communication Engineering
Electronic Circuits Lab Manual
Department of ECE

O =

=
O = = =
= + = + =
= = =
= = =
= = =
K
I
V V
R
K
I
V
R
V V V V
A I I I
A I I
A
m I
I
R
B CC
R
B
RE BE B
B R R
B R
C
B
3125 . 40
480
65 . 5 25
15 . 12
465
65 . 5
65 . 5 5 65 . 0 &
465 15 480
480 15 32 32
15
190
3
1
1
2
2
1 2
1

|
EXPERIMENT- 1

COMMON EMITTER AND COMMON SOURCE AMPLIFIER

AIM: To design CE single stage amplifier with potential divider circuit
using NPN Transistor 2N2923 for the specifications : I
C
= 3 mA, Vce =
10v,| = 190, & I
R1
= 32I
B
.verify DC values (Voltage and current) at various
nodes using MULTISIM.

APPARATUS: - Multisim Soft ware.

DESIGN PROCEDURE:
Vcc = 25V
Select V
RE
V
CE

Select V
RE
= 5V
) 00 . 2 ( 66 . 1
3
5
K select K
m I
V
R
C
RE
E
= = =
& V
RC
=V
CC
-V
CE
-V
RE
=25-10-5=10V
O = = = K
m I
V
R
C
RC
C
33 . 3
3
10
















Electronic Circuits Lab Manual
Department of ECE 2
25V
VCC
Q1
2N2923
R1
40.2kOhm_1%
R2
12kOhm_5%
R3
2.00kOhm_1%
R4
40.2kOhm_1%
V1
0V
V2
0V
V3
0V
V4
0V
2
3
4
7
9
10
11
0
VCC






CIRCUIT DIAGRAM:-
















PROCEDURE:- 1. Rig up the circuit using multisim software and verify
the results using DC operating point analysis (simulate ---- analysis ----- DC
operating point).


Electronic Circuits Lab Manual
Department of ECE 3





2.Rig up the circuit using multisim software and verify the results using DC
transfer characteristic analysis(simulate ---- analysis ----- DC sweep)




















Out put voltage V
CE
variation with V
CC
(0 to 25V)



RESULT:- The CE single stage amplifier is designed. The D.C voltages and
currents at various nodes are observed. The D.C transfer characteristic is
plotted.






Electronic Circuits Lab Manual
Department of ECE 4
EXPERIMENT- 2

COMMON SOURCE AMPLIFIER

AIM: a) To design a single stage FET Common Source amplifier with
potential divider circuit using 2n4861 FET-N channel for the following
specifications: V
DD
= 24V,I
D
= 1ma,V
GS
=2V,V
PMAX
=13V,R
L
=1K.
b) To observe dc operating point, frequency response, DC transfer
characteristic & C.R.O waveforms.

APPARATUS: Multisim soft ware.

DESIGN PROCEDURE:

V
DSmin
= V
Pmax
+ 1 - V
GS

= 13 + 1 - 2
= 12V

) 7 . 4 . . 5 tan (
5
4
1 20
20 4 24
1
4 2 6
) 3 . 6 tan ( 6
1
6
6
2
12 24
2
1
1
2
2
1
1
2
2
min
M e i M to equal or than less is which value dard s Use
M
M
R
V V V
R
V
V
R
M R Select
V V V V V
K value dard s Use K
m I
V
R R
V V
V V
G DD R
R
R
R GS S G
D
RD
S D
DS DD
RD S
O =

=
= = =
=
O =
= = = =
O O = = = =
=

= =








Electronic Circuits Lab Manual
Department of ECE 5


CIRCUIT DIAGRAM:












Electronic Circuits Lab Manual
Department of ECE 6
PROCEDURE:- 1. Rig up the circuit using multisim software and verify
the results using DC operating point analysis (simulate----analysis ---- DC
operating point)

2.Rig up the circuit using multisim software and verify the results using DC
transfer characteristic analysis(simulate ---- analysis ----- DC sweep)







Electronic Circuits Lab Manual
Department of ECE 7
3. Rig up the circuit using multisim software and verify the results using AC
analysis (Simulate ---- analysis ----- AC analysis)


4.Rig up the circuit using multisim software and verify the results using
Oscilloscope

RESULT: The CS single stage amplifier is designed with the given
specifications. The D.C operating point analysis is performed. The
frequency response is plotted and the Band width is found.





Electronic Circuits Lab Manual
Department of ECE 8
V1
0V
V2
0V
V3
0V
R1
32.98kohm
R2
5.1kohm
R3
2.2kohm
R4
516ohm
Q1
BC107BP
12V
VCC
EXPERIMENT- 3

TWO STAGE RC COUPLED AMPLIFIER

Q1) Design a single stage transistor amplifier with potential divider circuit
(using an npn si transistors) with following specifications.
I
C
=1.6ma,V
CE
=7.6v,R
C
=2.2k,V
CC
=12v, I
1
=10I
B
and |=54. Verify the DC
values (Voltage and current) at various nodes using Multisim software


DESIGN: I
B
=I
C
/| = 1.62/54=0.03ma
V
CC
=I
C
(R
C
+R
E
)+V
CE
; 12=1.62(2.2+R
E
)+7.6 ; R
E
=0.516k
V
2
=V
BE
+I
C
R
E
; V
2
=0.7+1.62*0.516=1.536v
V
2
=I
1
R
2
; R
2
=V
2
/(I
1
=10I
B
) ; 1.536/0.3=5.12k
I
1
=V
CC
/(R
1
+R
2
) ; (R
1
+R
2
)=12/0.3=38.1k ; R
1
=38.1-5.12=32.98k

CIRCUIT DIAGRAM:







5

1
8

4
2


0






Electronic Circuits Lab Manual
Department of ECE 9
PROCEDURE: Rig up the circuit using multisim software and verify the
results using DC operating point analysis (simulate analysis DC
operating point)
DC Operating Point (Results)
1 8.05632v
2 928.05352mv
4 1.58077v
Vv1#branch 315.92573a
Vv2#branch 1.79258ma
vcc 12.00000v
vccvcc#branch -2.10851ma

Q2) Design a single stage transistor amplifier with potential divider circuit
(using an npn si transistors) with following specifications.
I
C
=2.32ma,V
CE
=5.7v,R
C
=2.2k,V
CC
=12v, I
1
=10I
B
and |=33. Verify the DC
values (Voltage and current) at various nodes using Multisim software
DESIGN:
I
B
=I
C
/| = 2.32/33=0.07ma
V
CC
=I
C
(R
C
+R
E
)+V
CE
; 12=2.32(2.2+R
E
)+5.7 ; R
E
=0.51k
V
2
=V
BE
+I
C
R
E
; V
2
=0.7+2.32*0.51=1.88v
V
2
=I
1
R
2
; R
2
=V
2
/(I
1
=10I
B
) ; 1.88/0.7=2.68k
I
1
=V
CC
/(R
1
+R
2
) ; (R
1
+R
2
)=12/0.7=17.14k ; R
1
=17.14-2.68=14.46k








Electronic Circuits Lab Manual
Department of ECE 10
CIRCUIT DIAGRAM:
V1
0V
V2
0V
V3
0V
R1
14.46kohm
R2
2.68kohm
R3
2.2kohm
R4
510ohm
Q1
BC107BP
12V
VCC
5
3
2
12
0


PROCEDURE: Rig up the circuit using multisim software and verify the
results using DC operating point analysis (simulate analysis DC
operating point)


DC Operating Point (Results)
1 6.84857v
2 1.19817v
3 1.85869v
vv2#branch 2.34156ma
vcc 12.00000v
vccvcc#branch -3.04290ma
vv1#branch 701.33569a
vv3#branch -7.79614a










Electronic Circuits Lab Manual
Department of ECE 11
Q3) Cascade above two stages and find overall gain (choose C
c
=4.7f,
C
e
=470f, h
fe
=50) find the frequency response, DC operating points and
parameter sweep of load resister.

ANALYSIS:
Stage-2: AI
2
= -h
fe
/(1+h
oe
R
L2
) ; -50/(1+2/40) = -47.62
R
i2
= h
ie
+h
re
AI
2
R
L2
;1.1+2.5e-4*-47.62*2 = 1.076k;
Av
2
= -AI
2
*R
L2
/R
i2
; -47.62*2/1.076 = -88.51
Stage-1: R
L1
= 2.2k||14.2||2.5||1.076 = 0.54k
AI
1
= -50/(1+0.54/40) = -49.3
R
i1
= 1.1+2.5e-4*-49.3*0.54 = 1.106k
Av
1
= -49.3*0.54/1.106 = -24.07
Overall gain Av = Av
1
*Av
2
= 24.07*88.51= 2130.4
Avs = Av*R
i
/(R
i
+R
S
) ; R
i
= 1.106||33||5.1= 0.88k
=2130.4*0.88/(0.88+15) =118
CIRCUIT DIAGRA

























Rs
15kOhm_5%
C1
4.7uF
R2
5.1kOhm_5%
Rc1
2.2kOhm_5%
Re1
510Ohm_5%
C2
470uF
C3
4.7uF
R12
14.0kOhm_1%
R22
2.55kOhm_1%
Re2
470Ohm_5%
Rc2
2.2kOhm_5%
C5
47uF
V1
1mV
0.71mV_rms
1000Hz
0Deg
12V
VCC
C4
470uF
R10
22kOhm_5%
A B
T
G
XSC1
R1
33kOhm_5%
Q3
BC107BP
Q1
BC107BP
1 2
0
9
VCC
14
3
5
10
11
15
Electronic Circuits Lab Manual
Department of ECE 12



Note: In above two stage CE amplifier, all resistor values are same as trainer
kit values.

PROCEDURE:1. Rig up the circuit using multisim software and verify the
results using DC operating point analysis (simulate------- analysis -------
DC operating point and AC analysis)

DC Operating Point (Results)
Node no Voltage
2 1.57966
9 8.01593
15 926.65516m
5 1.83114
11 1.16896
10 6.54642










Electronic Circuits Lab Manual
Department of ECE 13



2. Rig up the circuit using multisim software and verify the results using
Parameter Sweep(Simulate------ analysis ------- Parameter sweep)




RESULTS: Observed the DC voltages/currents for single stage and two stage
amplifiers. It is observed that Two stage amplifier gives a mid band gain of
1220.It is also observed that as load resistance is nearer to R
C2
, the out put
voltage is decreasing, since net load resistance is decreasing.

















Electronic Circuits Lab Manual
Department of ECE 14






EXPERIMENT- 5


RC PHASE SHIFT OSCILLATOR
AIM:
a) Design RC phaseshift oscillator to have resonant frequency of 6KHz.
Assume R
1
= 100k, R
2
= 22K, R
C
= 4 K ,R
E
=1K & V
CC
= 12V.
b) Obtain h
fe
for the above designed value for A
V
> - 29, R 2 R
C
.

APPARATUS: Multisim software.

DESIGN PROCEDURE:

a) Let R = 10K

) tan ( 1 962 . 0
10
4
4 6 6 10 2
1
4 6 2
1
dard s Select nF nF
K
K
K K
C
R
R
K When
K R
f
C
C
r
~ =
+
=
=
+
=
t
t


nF C K R 1 ; 10 = =


1 . 97
4
29
23 )
=
+ = > n oscillatio sustained for K
K
hfe b




Electronic Circuits Lab Manual
Department of ECE 15

CIRCUIT DIAGRAM:

Q2
2N2222A
R1
100kohm
R2
22kohm
R3
4kohm
R4
1kohm
12V
VCC
C1
10uF
C2
10uF
A
B
T G
XSC1
C3
100uF
C4
1.0nF
C5
1.0nF
C6
1.0nF
R5
10kOhm_5%
R6
10kOhm_5%
R7
10kOhm_5%
4
6 7
VCC
10
11
0
9
12












Electronic Circuits Lab Manual
Department of ECE 16


PROCEDURE: Rig up the circuit using multisim software and verify the
results using Oscilloscope.






RESULT: RC phase shift oscillator with f
r
=6KHz is designed. The value of
h
fe
for the designed value is computed.











Electronic Circuits Lab Manual
Department of ECE 17