Document 1

Release 11.1 - xst L.
33 (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.11 secs
--> Parameter xsthdpdir set to xst

--> Reading design: mul_array_nbit_top.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
*
Synthesis Options Summary
*
=========================================================================
---- Source Parameters
Input File Name
: "mul_array_nbit_top.prj"
Input Format
: mixed
Ignore Synthesis Constraint File
: NO
---- Target Parameters
Output File Name
Output Format
Target Device
: "mul_array_nbit_top"
: NGC
: xc5vlx50t-3-ff1136
---- Source Options

Top Module Name
Automatic FSM Extraction
FSM Encoding Algorithm
Safe Implementation
FSM Style
RAM Extraction
RAM Style
ROM Extraction
Mux Style
Decoder Extraction
:
:
:
:
:
:
:
:
:
:
mul_array_nbit_top
YES
Auto
No
lut
Yes
Auto
Yes
Auto
YES
1
Priority Encoder Extraction

Shift Register Extraction
Logical Shifter Extraction
XOR Collapsing
ROM Style
Mux Extraction
Resource Sharing
Asynchronous To Synchronous
Use DSP Block
Automatic Register Balancing
:
:
:
:
:
:
:
:
:
:
YES
YES
YES
YES
Auto
YES
YES
NO
auto
No
---- Target Options

LUT Combining
Reduce Control Sets
Add IO Buffers
Global Maximum Fanout
Add Generic Clock Buffer(BUFG)
Register Duplication
Slice Packing
Optimize Instantiated Primitives
Use Clock Enable
Use Synchronous Set
Use Synchronous Reset
Pack IO Registers into IOBs
Equivalent register Removal
:
:
:
:
:
:
:
:
:
:
:
:
:
auto
off
YES
100000
32
YES
YES
NO
Auto
Auto
Auto
auto
YES
---- General Options

Optimization Goal
Optimization Effort
Power Reduction
Library Search Order
Keep Hierarchy
Netlist Hierarchy
RTL Output
Global Optimization
Read Cores
Write Timing Constraints
Cross Clock Analysis
Hierarchy Separator
Bus Delimiter
Case Specifier
Slice Utilization Ratio
BRAM Utilization Ratio
DSP48 Utilization Ratio
Verilog 2001
Auto BRAM Packing
Slice Utilization Ratio Delta
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Area
2
NO
mul_array_nbit_top.lso
NO
as_optimized
Yes
AllClockNets
YES
NO
NO
/
<>
maintain
100
100
100
YES
YES
5
=========================================================================
=========================================================================
*
HDL Compilation
*
=========================================================================
Compiling vhdl file "D:/altera/test/pipo_nbit.vhd" in Library work.
Architecture arc_pipo of Entity pipo_nbit is up to date.
Compiling vhdl file "D:/altera/test/mul_array_nbit.vhd" in Library work.
2
Architecture arch_mul_array_nbit of Entity mul_array_nbit is up to date.

Compiling vhdl file "D:/altera/test/mul_array_nbit_top.vhd" in Library work.
Entity <mul_array_nbit_top> compiled.
Entity <mul_array_nbit_top> (Architecture <arc_mul_array_nbit_top>) compiled.
=========================================================================
*
Design Hierarchy Analysis
*
=========================================================================
Analyzing hierarchy for entity <mul_array_nbit_top> in library <work>
(architecture <arc_mul_array_nbit_top>) with generics.
mul_len = 32
Analyzing hierarchy for entity <pipo_nbit> in library <work> (architecture
<arc_pipo>) with generics.
reg_len = 32
Analyzing hierarchy for entity <mul_array_nbit> in library <work> (architecture
<arch_mul_array_nbit>) with generics.
n = 32
Analyzing hierarchy for entity <pipo_nbit> in library <work> (architecture
<arc_pipo>) with generics.
reg_len = 64
=========================================================================
*
HDL Analysis
*
=========================================================================
Analyzing generic Entity <mul_array_nbit_top> in library <work> (Architecture
<arc_mul_array_nbit_top>).
mul_len = 32
Entity <mul_array_nbit_top> analyzed. Unit <mul_array_nbit_top> generated.
Analyzing generic Entity <pipo_nbit.1> in library <work> (Architecture
<arc_pipo>).
reg_len = 32
Entity <pipo_nbit.1> analyzed. Unit <pipo_nbit.1> generated.
Analyzing generic Entity <mul_array_nbit> in library <work> (Architecture
<arch_mul_array_nbit>).
n = 32
Entity <mul_array_nbit> analyzed. Unit <mul_array_nbit> generated.
Analyzing generic Entity <pipo_nbit.2> in library <work> (Architecture
<arc_pipo>).
reg_len = 64
Entity <pipo_nbit.2> analyzed. Unit <pipo_nbit.2> generated.
=========================================================================
*
HDL Synthesis
*
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <pipo_nbit_1>.
Related source file is "D:/altera/test/pipo_nbit.vhd".
3
Found 32-bit register for signal <reg_out>.

Summary:
inferred 32 D-type flip-flop(s).
Unit <pipo_nbit_1> synthesized.
Synthesizing Unit <mul_array_nbit>.

Related source file is "D:/altera/test/mul_array_nbit.vhd".
WARNING:Xst:646 - Signal <ps<0><0>> is assigned but never used. This unconnected
signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ps<32><0>> is never used or assigned. This
unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <pp<32>> is never used or assigned. This unconnected
signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <pc<0><31>> is assigned but never used. This
WARNING:Xst:1780 - Signal <pc<1><31>> is never used or assigned. This
4
unconnected signal will be trimmed during

WARNING:Xst:1780 - Signal <pc<22><31>> is
Summary:
inferred 960 Xor(s).
Unit <mul_array_nbit> synthesized.
the optimization process.

never used or assigned. This
Synthesizing Unit <pipo_nbit_2>.

Related source file is "D:/altera/test/pipo_nbit.vhd".
Found 64-bit register for signal <reg_out>.
Summary:
inferred 64 D-type flip-flop(s).
Unit <pipo_nbit_2> synthesized.
Synthesizing Unit <mul_array_nbit_top>.

Related source file is "D:/altera/test/mul_array_nbit_top.vhd".
Unit <mul_array_nbit_top> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Registers
32-bit register
64-bit register
# Xors
1-bit xor2
1-bit xor3
:
:
:
:
:
:
3
2
1
992
32
960
=========================================================================
=========================================================================
*
Advanced HDL Synthesis
*
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Registers
Flip-Flops
# Xors
1-bit xor2
1-bit xor3
:
:
:
:
:
128
128
992
32
960
=========================================================================
=========================================================================
*
Low Level Synthesis
*
=========================================================================
Optimizing unit <mul_array_nbit_top> ...
Optimizing unit <pipo_nbit_1> ...
Optimizing unit <mul_array_nbit> ...
Optimizing unit <pipo_nbit_2> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block mul_array_nbit_top, actual
ratio is 5.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers
Flip-Flops
: 128
: 128
=========================================================================
=========================================================================
*
Partition Report
*
=========================================================================
Partition Implementation Status
------------------------------No Partitions were found in this design.
------------------------------=========================================================================
*
Final Report
*
=========================================================================
Final Results
RTL Top Level Output File Name
: mul_array_nbit_top.ngr
Top Level Output File Name
: mul_array_nbit_top
6
Output Format
Optimization Goal
Keep Hierarchy
: NGC
: Area
: NO
Design Statistics
# IOs
: 130
Cell Usage :
# BELS
: 1458
#
LUT2
: 14
#
LUT4
: 437
#
LUT5
: 17
#
LUT6
: 990
# FlipFlops/Latches
: 128
#
FDC
: 128
# Clock Buffers
: 1
#
BUFGP
: 1
# IO Buffers
: 129
#
IBUF
: 65
#
OBUF
: 64
=========================================================================
Device utilization summary:
--------------------------Selected Device : 5vlx50tff1136-3
Slice Logic Utilization:

Number of Slice LUTs:
Number used as Logic:
1458
1458
out of
out of
28800
28800
5%
5%
Slice Logic Distribution:

Number of LUT Flip Flop pairs used:
Number with an unused Flip Flop:
Number with an unused LUT:
Number of fully used LUT-FF pairs:
Number of unique control sets:
1458
1458
0
0
1
out of
out of
out of
1458
1458
1458
100%
0%
0%
130
130
128
out of
480
27%
out of
32
3%
IO Utilization:
Number of IOs:
Number of bonded IOBs:
IOB Flip Flops/Latches:
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs:
--------------------------Partition Resource Summary:
---------------------------
No Partitions were found in this design.

---------------------------
=========================================================================
7
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
| Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk
| BUFGP
| 128
|
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
--------------------------------------------------------------------------+------------------------+-------+
Control Signal
| Buffer(FF name)
| Load |
-----------------------------------+------------------------+-------+
rst
| IBUF
| 128
|
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -3
Minimum
Minimum
Maximum
Maximum
period: 22.478ns (Maximum Frequency: 44.488MHz)

input arrival time before clock: 0.929ns
output required time after clock: 2.775ns
combinational path delay: No path found
Timing Detail:
-------------All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 22.478ns (frequency: 44.488MHz)
Total number of paths / destination ports: 2502661502205 / 64
------------------------------------------------------------------------Delay:
22.478ns (Levels of Logic = 47)
Source:
inreg1/reg_out_29 (FF)
Destination:
outrg1/reg_out_63 (FF)
Source Clock:
clk rising
Destination Clock: clk rising
Data Path: inreg1/reg_out_29 to outrg1/reg_out_63
Gate
Net
Cell:in->out
fanout
Delay
Delay Logical Name (Net Name)
---------------------------------------- -----------FDC:C->Q
51
0.396
0.942 inreg1/reg_out_29
(inreg1/reg_out_29)
LUT6:I0->O
3
0.086
0.369 rca_n/_or06911 (rca_n/pc<2><29>)
LUT4:I3->O
2
0.086
0.365 rca_n/Mxor_ps<3><29>_xo<0>1
(rca_n/ps<3><29>)
LUT6:I5->O
3
0.086
0.369 rca_n/_or07531 (rca_n/pc<4><28>)
LUT4:I3->O
3
0.086
0.444 rca_n/Mxor_ps<5><28>_xo<0>1
8
(rca_n/ps<5><28>)
LUT4:I2->O
(rca_n/ps<6><27>)
LUT4:I3->O
(rca_n/ps<7><26>)
LUT4:I3->O
(rca_n/ps<8><25>)
LUT4:I3->O
(rca_n/ps<9><24>)
LUT4:I3->O
(rca_n/ps<10><23>)
LUT4:I3->O
(rca_n/ps<11><22>)
LUT4:I3->O
(rca_n/ps<12><21>)
LUT4:I3->O
(rca_n/ps<13><20>)
LUT4:I3->O
(rca_n/ps<14><19>)
LUT4:I3->O
(rca_n/ps<15><18>)
LUT4:I3->O
(rca_n/ps<16><17>)
LUT4:I3->O
(rca_n/ps<17><16>)
LUT4:I3->O
(rca_n/ps<18><15>)
LUT4:I3->O
(rca_n/ps<19><14>)
LUT4:I3->O
(rca_n/ps<20><13>)
LUT4:I3->O
(rca_n/ps<21><12>)
LUT4:I3->O
(rca_n/ps<22><11>)
LUT4:I3->O
(rca_n/ps<23><10>)
LUT4:I3->O
(rca_n/ps<24><9>)
LUT4:I3->O
(rca_n/ps<25><8>)
LUT4:I3->O
(rca_n/ps<26><7>)
LUT4:I3->O
(rca_n/ps<27><6>)
LUT4:I3->O
(rca_n/ps<28><5>)
LUT4:I3->O
(rca_n/ps<29><4>)
LUT4:I3->O
(rca_n/ps<30><3>)
LUT4:I3->O
(rca_n/ps<31><2>)
LUT6:I4->O
LUT6:I5->O
LUT6:I5->O
LUT6:I5->O
0.086
0.369
rca_n/Mxor_ps<6><27>_xo<0>1
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.369
0.086
0.440
2
3
3
3
0.086
0.086
0.086
0.086
0.365
0.369
0.369
0.369
rca_n/_or00121
rca_n/_or00141
rca_n/_or00181
rca_n/_or00221
(rca_n/pc<32><2>)
(rca_n/pc<32><3>)
(rca_n/pc<32><5>)
(rca_n/pc<32><7>)
9
LUT6:I5->O
3
0.086
0.369 rca_n/_or00261 (rca_n/pc<32><9>)
LUT6:I5->O
3
0.086
0.369 rca_n/_or02911 (rca_n/pc<32><11>)
LUT6:I5->O
3
0.086
0.369 rca_n/_or02951 (rca_n/pc<32><13>)
LUT6:I5->O
3
0.086
0.369 rca_n/_or03031 (rca_n/pc<32><15>)
LUT6:I5->O
3
0.086
0.369 rca_n/_or03131 (rca_n/pc<32><17>)
LUT6:I5->O
3
0.086
0.369 rca_n/_or03231 (rca_n/pc<32><19>)
LUT6:I5->O
3
0.086
0.369 rca_n/_or03061 (rca_n/pc<32><21>)
LUT6:I5->O
3
0.086
0.369 rca_n/_or03161 (rca_n/pc<32><23>)
LUT6:I5->O
3
0.086
0.369 rca_n/_or03291 (rca_n/pc<32><25>)
LUT6:I5->O
3
0.086
0.369 rca_n/_or03391 (rca_n/pc<32><27>)
LUT6:I5->O
2
0.086
0.365 rca_n/_or03481 (rca_n/pc<32><29>)
LUT6:I5->O
2
0.086
0.365 rca_n/_or03281 (rca_n/pc<32><30>)
LUT6:I5->O
1
0.086
0.000 rca_n/_or03341 (sq<63>)
FDC:D
-0.022
outrg1/reg_out_63
---------------------------------------Total
22.478ns (4.438ns logic, 18.040ns route)
(19.7% logic, 80.3% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
------------------------------------------------------------------------Offset:
Source:
b<31> (PAD)
Destination:
inreg2/reg_out_31 (FF)
Destination Clock: clk rising
Data Path: b<31> to inreg2/reg_out_31
Gate
Net
Cell:in->out
fanout
Delay
---------------------------------------- -----------IBUF:I->O
1
0.694
0.235 b_31_IBUF (b_31_IBUF)
FDC:D
-0.022
inreg2/reg_out_31
---------------------------------------Total
(74.7% logic, 25.3% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
------------------------------------------------------------------------Offset:
Source:
outrg1/reg_out_63 (FF)
Destination:
q<63> (PAD)
Source Clock:
clk rising
Data Path: outrg1/reg_out_63 to q<63>
Gate
Net
Cell:in->out
fanout
Delay
---------------------------------------- -----------FDC:C->Q
1
0.396
0.235 outrg1/reg_out_63
(outrg1/reg_out_63)
OBUF:I->O
2.144
q_63_OBUF (q<63>)
---------------------------------------Total
(91.5% logic, 8.5% route)
10
=========================================================================

-->
Total memory usage is 246832 kilobytes
Number of errors
:
Number of warnings :
Number of infos
:
0 (
35 (
0 (
0 filtered)
0 filtered)
0 filtered)
11

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Release 11.1 - xst L.

Total REAL time to Xst completion: 0.00 secs

Total REAL time to Xst completion: 0.00 secs

---- Source Options

Priority Encoder Extraction

---- Target Options

---- General Options

Architecture arch_mul_array_nbit of Entity mul_array_nbit is up to date.

Found 32-bit register for signal <reg_out>.

Synthesizing Unit <mul_array_nbit>.

unconnected signal will be trimmed during

the optimization process.

Synthesizing Unit <pipo_nbit_2>.

Synthesizing Unit <mul_array_nbit_top>.

Slice Logic Utilization:

Slice Logic Distribution:

No Partitions were found in this design.

period: 22.478ns (Maximum Frequency: 44.488MHz)

Total REAL time to Xst completion: 247.00 secs

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