MSP 430 Afe 252

MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1
www.ti.com SLAS701A NOVEMBER 2010 REVISED MARCH 2011
MIXED SIGNAL MICROCONTROLLER

1
FEATURES
Low Supply Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption Active Mode: 220 A at 1 MHz, 2.2 V Standby Mode: 0.5 A Off Mode (RAM Retention): 0.1 A Five Power-Saving Modes Ultra-Fast Wake-Up From Standby Mode in Less Than 1 s 16-Bit RISC Architecture, up to 12-MHz System Clock Basic Clock Module Configurations Internal Frequencies up to 12 MHz With Two Calibrated Frequencies Internal Very-Low-Power Low-Frequency (LF) Oscillator High-Frequency (HF) Crystal up to 16 MHz Resonator External Digital Clock Source Up to Three 24-Bit Sigma-Delta Analog-to-Digital (A/D) Converters With Differential PGA Inputs 16-Bit Timer_A With Three Capture/Compare Registers Serial Communication Interface (USART), Asynchronous UART or Synchronous SPI Selectable by Software 16-Bit Hardware Multiplier Brownout Detector Supply Voltage Supervisor/Monitor with Programmable Level Detection Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse On-Chip Emulation Module Family Members are Summarized in Table 1. For Complete Module Descriptions, See the MSP430x2xx Family User's Guide, Literature Number SLAU144
DESCRIPTION
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 s. The MSP430AFE2x3 devices are ultra-low-power mixed signal microcontrollers integrating three independent 24-bit sigma-delta A/D converters, one 16-bit timer, one 16-bit hardware multiplier, USART communication interface, watchdog timer, and 11 I/O pins. The MSP430AFE2x2 devices are identical to the MSP430AFE2x3, except that there are only two 24-bit sigma-delta A/D converters integrated. The MSP430AFE2x1 devices are identical to the MSP430AFE2x3, except that there is only one 24-bit sigma-delta A/D converter integrated. Available family members are summarized in Table 1.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 20102011, Texas Instruments Incorporated

SLAS701A NOVEMBER 2010 REVISED MARCH 2011 www.ti.com
Table 1. Family Members (1)

Device Flash (KB) 16 8 4 16 8 4 16 8 4 SRAM (Byte) 512 512 256 512 512 256 512 512 256 EEM SD24_A Converters 3 3 3 2 2 2 1 1 1 16-Bit MPY 1 1 1 1 1 1 1 1 1 Timer_A (2) USART (UART/ SPI) 1 1 1 1 1 1 1 1 1 Clocks HF, DCO, VLO HF, DCO, VLO HF, DCO, VLO HF, DCO, VLO HF, DCO, VLO HF, DCO, VLO HF, DCO, VLO HF, DCO, VLO HF, DCO, VLO I/O Package Type (3) 24-TSSOP 24-TSSOP 24-TSSOP 24-TSSOP 24-TSSOP 24-TSSOP 24-TSSOP 24-TSSOP 24-TSSOP
MSP430AFE253IPW MSP430AFE233IPW MSP430AFE223IPW MSP430AFE252IPW MSP430AFE232IPW MSP430AFE222IPW MSP430AFE251IPW MSP430AFE231IPW MSP430AFE221IPW
1 1 1 1 1 1 1 1 1
3 3 3 3 3 3 3 3 3
11 11 11 11 11 11 11 11 11
(1) (2) (3)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Development Tool Support

All MSP430 microcontrollers include an Embedded Emulation Module (EEM) that allows advanced debugging and programming through easy-to-use development tools. Recommended hardware options include: Debugging and Programming Interface MSP-FET430UIF (USB) MSP-FET430PIF (Parallel Port) Debugging and Programming Interface with Target Board MSP-TS430PW24 Production Programmer MSP-GANG430
Submit Documentation Feedback

Functional Block Diagram

XT2IN XT2OUT DVCC DVSS AVCC AVSS
P1.x 8
P2.x 3
ACLK Basic Clock System+ SMCLK MCLK 16KB 8KB 4KB Flash 512B 512B 256B RAM
Hardware Multiplier (16x16) MPY, MPYS, MAC, MACS
Port P1 8 I/O Interrupt capability Pull-up/ down resistors
Port P2 3 I/O Interrupt capability Pull-up/ down resistors
12MHz CPU incl. 16 Registers
MAB
MDB
Emulation
2BP
Watchdog WDT+ 15/16-bit SD24_A (w/o BUF) 3 Converter 2 Converter 1 Converter
Timer_A3 3 CC Registers
JTAG Interface
USART0 UART or SPI Function
BOR SVS/SVM
Spy-Bi Wire
RST/NMI
Pin Designation, MSP430AFE2x3IPW
A0.0+ A0.0A1.0+ A1.0AVCC AVSS VREF A2.0+ A2.0TEST/SBWTCK RST/NMI/SBWTDIO P1.0/SVSIN/TACLK/SMCLK/TA2
1 2 3 4 5 6 7 8 9 10 11 12 MSP430AFE2x3
24 23 22 21 20 19 18 17 16 15 14 13
P2.0/STE0/TA0/TDI/TCLK P1.7/UCLK0/TA1/TDO/TDI P1.6/SOMI0/TA2/TCK P1.5/SIMO0/SVSOUT/TMS P1.4/URXD0/SD2DO P1.3/UTXD0/SD1DO P1.2/TA0/SD0DO P1.1/TA1/SDCLK DVCC P2.7/XT2OUT P2.6/XT2IN DVSS

A0.0+ A0.0A1.0+ A1.0AVCC AVSS VREF NC NC TEST/SBWTCK RST/NMI/SBWTDIO P1.0/SVSIN/TACLK/SMCLK/TA2

A.
1 2 3 4 5 6 7 8 9 10 11 12 MSP430AFE2x2
24 23 22 21 20 19 18 17 16 15 14 13
P2.0/STE0/TA0/TDI/TCLK P1.7/UCLK0/TA1/TDO/TDI P1.6/SOMI0/TA2/TCK P1.5/SIMO0/SVSOUT/TMS P1.4/URXD0 P1.3/UTXD0/SD1DO P1.2/TA0/SD0DO P1.1/TA1/SDCLK DVCC P2.7/XT2OUT P2.6/XT2IN DVSS
Connect NC pins to analog ground (AVSS)
A0.0+ A0.0NC NC AVCC AVSS VREF NC NC TEST/SBWTCK RST/NMI/SBWTDIO P1.0/SVSIN/TACLK/SMCLK/TA2

B.
1 2 3 4 5 6 7 8 9 10 11 12 MSP430AFE2x1
24 23 22 21 20 19 18 17 16 15 14 13
P2.0/STE0/TA0/TDI/TCLK P1.7/UCLK0/TA1/TDO/TDI P1.6/SOMI0/TA2/TCK P1.5/SIMO0/SVSOUT/TMS P1.4/URXD0 P1.3/UTXD0 P1.2/TA0/SD0DO P1.1/TA1/SDCLK DVCC P2.7/XT2OUT P2.6/XT2IN DVSS
Connect NC pins to analog ground (AVSS)

Table 2. Terminal Functions

TERMINAL NAME A0.0+ A0.0A1.0+ A1.0AVCC AVSS VREF A2.0+ A2.0TEST/SBWTCK RST/NMI/SBWTDIO NO. 1 2 3 4 5 6 7 8 9 10 11 I/O I I I I I/O I I I I DESCRIPTION SD24_A positive analog input A0.0 (1) SD24_A negative analog input A0.0 (1) SD24_A positive analog input A1.0 (not available on MSP430AFE2x1) (1) SD24_A negative analog input A1.0 (not available on MSP430AFE2x1) (1) Analog supply voltage, positive terminal. Must not power up prior to DVCC. Analog supply voltage, negative terminal Input for an external reference voltage/ output for internal reference voltage (can be used as mid-voltage) SD24_A positive analog input A2.0 (not available on MSP430AFE2x2 and MSP430AFE2x1) (1) SD24_A negative analog input A2.0 (not available on MSP430AFE2x2 and MSP430AFE2x1) (1) Selects test mode for JTAG pins on P1.5 to P1.7 and P2.0. The device protection fuse is connected to TEST. Spy-Bi-Wire test clock input for device programming and test. Reset or nonmaskable interrupt input Spy-Bi-Wire test data input/output for device programming and test. General-purpose digital I/O pin Analog input to supply voltage supervisor Timer_A3, clock signal TACLK input SMCLK signal output Timer_A3, compare: Out2 Output Digital supply voltage, negative terminal I/O I/O Input terminal of crystal oscillator General-purpose digital I/O pin Output terminal of crystal oscillator General-purpose digital I/O pin Digital supply voltage, positive terminal. I/O General-purpose digital I/O pin Timer_A3, capture: CCI1A and CCI1B inputs, compare: Out1 output SD24_A bit stream clock output General-purpose digital I/O pin Timer_A3, capture: CCI0A and CCI0B inputs, compare: Out0 output SD24_A bit stream data output for channel 0 General-purpose digital I/O pin Transmit data out - USART0/UART mode SD24_A bit stream data output for channel 1 (not available on MSP430AFE2x1) General-purpose digital I/O pin Receive data in - USART0/UART mode SD24_A bit stream data output for channel 2 (not available on MSP430AFE2x2 and MSP430AFE2x1) General-purpose digital I/O Slave in/master out of USART0/SPI mode SVS: output of SVS comparator JTAG test mode select. TMS is used as an input port for device programming and test. General-purpose digital I/O pin Slave out/master in of USART0/SPI mode Timer_A3, compare: Out2 output JTAG test clock. TCK is the clock input port for device programming and test. General-purpose digital I/O pin External clock input - USART0/UART or SPI mode, clock output - USART0/SPI mode. Timer_A3, compare: Out1 output JTAG test data output port. TDO/TDI data output or programming data input terminal.
P1.0/SVSIN/TACLK/SMCLK/TA2
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I/O
DVSS P2.6/XT2IN P2.7/XT2OUT DVCC P1.1/TA1/SDCLK
13 14 15 16 17
P1.2/TA0/SD0DO
18
I/O
P1.3/UTXD0/SD1DO
19
I/O
P1.4/URXD0/SD2DO
20
I/O
P1.5/SIMO0/SVSOUT/TMS
21
I/O
P1.6/SOMI0/TA2/TCK
22
I/O
P1.7/UCLK0/TA1/TDO/TDI
23
I/O
(1)
It is recommended to short unused analog input pairs and connect them to analog ground. Submit Documentation Feedback 5

Table 2. Terminal Functions (continued)

TERMINAL NAME P2.0/STE0/TA0/TDI/TCLK NO. 24 I/O DESCRIPTION General-purpose digital I/O pin Slave transmit enable - USART0/SPI mode. Timer_A3, compare: Out0 output JTAG test data input or test clock input for device programming and test.
I/O

SHORT-FORM DESCRIPTION CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses and can be handled with all instructions.
Program Counter PC/R0
Stack Pointer
SP/R1 SR/CG1/R2
Status Register
Constant Generator
CG2/R3 R4
General-Purpose Register
R5
R6 R7
General-Purpose Register General-Purpose Register
R8 R9
General-Purpose Register General-Purpose Register
R10 R11
Instruction Set
The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 3 shows examples of the three types of instruction formats; Table 4 shows the address modes.
R12 R13
R14 R15
Table 3. Instruction Word Formats

INSTRUCTION FORMAT Dual operands, source-destination Single operands, destination only Relative jump, unconditional/conditional EXAMPLE ADD R4,R5 CALL R8 JNE OPERATION R4 + R5 R5 PC (TOS), R8 PC Jump-on-equal bit = 0
Table 4. Address Mode Descriptions

ADDRESS MODE Register Indexed Symbolic (PC relative) Absolute Indirect Indirect autoincrement Immediate (1) (2) S = source D = destination S
(1)
(2)
SYNTAX MOV Rs,Rd MOV X(Rn),Y(Rm) MOV EDE,TONI MOV &MEM,&TCDAT MOV @Rn,Y(Rm) MOV @Rn+,Rm MOV #X,TONI
EXAMPLE MOV R10,R11 MOV 2(R5),6(R6)
OPERATION R10 R11 M(2+R5) M(6+R6) M(EDE) M(TONI) M(MEM) M(TCDAT)
MOV @R10,Tab(R6) MOV @R10+,R11 MOV #45,TONI
M(R10) M(Tab+R6) M(R10) R11 R10 + 2 R10 #45 M(TONI)

Operating Modes
The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: Active mode ( AM) All clocks are active. Low-power mode 0 (LPM0) CPU is disabled. ACLK and SMCLK remain active. MCLK is disabled. Low-power mode 1 (LPM1) CPU is disabled ACLK and SMCLK remain active. MCLK is disabled. DCO dc-generator is disabled if DCO not used in active mode. Low-power mode 2 (LPM2) CPU is disabled. MCLK and SMCLK are disabled. DCO dc-generator remains enabled. ACLK remains active. Low-power mode 3 (LPM3) CPU is disabled. MCLK and SMCLK are disabled. DCO dc-generator is disabled. ACLK remains active. Low-power mode 4 (LPM4) CPU is disabled. ACLK is disabled. MCLK and SMCLK are disabled. DCO dc-generator is disabled. Crystal oscillator is stopped.

Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the CPU goes into LPM4 immediately after power up. Table 5. Interrupt Vector Addresses
INTERRUPT SOURCE Power up External reset Watchdog Flash key violation PC out-of-range (1) NMI Oscillator fault Flash memory access violation INTERRUPT FLAG PORIFG RSTIFG WDTIFG KEYV
(2)
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Reset
0FFFEh
15, highest
NMIIFG OFIFG ACCVIFG (2)
(3)
(Non)maskable, (Non)maskable, (Non)maskable
0FFFCh 0FFFAh
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0, lowest
SD24_A
SD24CCTLx SD24OVIFG, SD24CCTLx SD24IFG (2) (4) WDTIFG URXIFG0 UTXIFG0 TA0CCR0 CCIFG
(4)
Maskable
0FFF8h 0FFF6h
Watchdog Timer USART0 Receive USART0 Transmit Timer_A3 Timer_A3 I/O Port P1 (eight flags)
Maskable Maskable Maskable Maskable Maskable Maskable
0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh 0FFE8h 0FFE6h 0FFE4h
TA0CCR1 CCIFG, TA0CCR2 CCIFG, TA0CTL TAIFG (2) (4) P1IFG.0 to P1IFG.7 (2)
(4)
I/O Port P2 (three flags)
P2IFG.0 to P2IFG.2
(2) (4)
Maskable
0FFE2h 0FFE0h
(1) (2) (3) (4)
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from within unused address range. Multiple source flags (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. Interrupt flags are located in the module.

Special Function Registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.
Legend rw rw-0, 1 rw-(0), (1) Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written. It is Reset or Set by POR. SFR bit is not present in device.
Table 6. Interrupt Enable 1

Address 00h 7 UTXIE0 rw-0 WDTIE OFIE NMIIE ACCVIE URXIE0 UTXIE0 6 URXIE0 rw-0 5 ACCVIE rw-0 4 NMIIE rw-0 3 2 1 OFIE rw-0 0 WDTIE rw-0
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. Oscillator fault interrupt enable (Non)maskable interrupt enable Flash access violation interrupt enable USART0: UART and SPI receive interrupt enable USART0: UART and SPI transmit interrupt enable
Table 7. Interrupt Enable 2

Address 01h 7 6 5 4 3 2 1 0
Table 8. Interrupt Flag Register 1

Address 02h 7 UTXIFG0 rw-1 WDTIFG OFIFG RSTIFG PORIFG NMIIFG URXIFG0 UTXIFG0 6 URXIFG0 rw-0 5 4 NMIIFG rw-0 3 RSTIFG rw-(0) 2 PORIFG rw-(1) 1 OFIFG rw-1 0 WDTIFG rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. Flag set on oscillator fault External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up. Power-on reset interrupt flag. Set on VCC power up. Set via RST/NMI-pin USART0: UART and SPI receive interrupt flag USART0: UART and SPI transmit interrupt flag
Table 9. Interrupt Flag Register 2

Address 03h 7 6 5 4 3 2 1 0
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Table 10. Module Enable Register 1

Address 04h 7 UTXE0 rw-0 URXE0 UTXE0 USPIE0 6 URXE0 USPIE0 rw-0 5 4 3 2 1 0
USART0: UART mode receive enable USART0: UART mode transmit enable USART0: SPI mode transmit and receive enable
Table 11. Module Enable Register 2

Address 05h 7 6 5 4 3 2 1 0
Memory Organization
Table 12. Memory Organization
MSP430AFE22x Memory Main: interrupt vector Main: code memory Information memory RAM Peripherals Size Flash Flash Size Flash Size 16-bit 8-bit 8-bit SFR 4 KB 0xFFFF to 0xFFE0 0xFFFF to 0xF000 256 Byte 0x10FFh to 0x1000 256 Byte 0x02FF to 0x0200 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 MSP430AFE23x 8 KB 0xFFFF to 0xFFE0 0xFFFF to 0xE000 256 Byte 0x10FFh to 0x1000 512 Byte 0x03FF to 0x0200 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000 MSP430AFE25x 16 KB 0xFFFF to 0xFFE0 0xFFFF to 0xC000 256 Byte 0x10FFh to 0x1000 512 Byte 0x03FF to 0x0200 0x01FF to 0x0100 0x00FF to 0x0010 0x000F to 0x0000
Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size. Segments 0 to n may be erased in one step, or each segment may be individually erased. Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. Segment A contains calibration data. After reset segment A is protected against programming and erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for an internal digitally controlled oscillator (DCO), a high-frequency crystal oscillator, and an internal very-low-power low-frequency oscillator (VLO). The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 s. The basic clock module provides the following clock signals: Auxiliary clock (ACLK), sourced from the VLO Main clock (MCLK), the system clock used by the CPU Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules Table 13. DCO Calibration Data (Provided From Factory in Flash Information Memory Segment A)
DCO FREQUENCY 8 MHz 12 MHz CALIBRATION REGISTER CALBC1_8MHZ CALDCO_8MHZ CALBC1_12MHZ CALDCO_12MHZ SIZE byte byte byte byte ADDRESS 010FDh 010FCh 010FBh 010FAh
Brownout, Supply Voltage Supervisor

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM) (the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must ensure that the default DCO settings are not changed until VCC reaches VCC(min) . If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
Digital I/O
There are two I/O ports implemented: 8-bit port P1 and 3-bit port P2. All individual I/O bits are independently programmable. Any combination of input, output, and interrupt condition is possible. Edge-selectable interrupt input capability for all eight bits of port P1 and three bits of port P2. Read/write access to port-control registers is supported by all instructions. Each I/O has an individually programmable pullup/pulldown resistor. Because there are only three I/O pins implemented from port P2, bits [5:1] of all port P2 registers read as 0, and write data is ignored.
Watchdog Timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.
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Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 14. Timer_A3 Signal Connections
INPUT PIN NUMBER 24-PIN PW 12 - P1.0 DEVICE INPUT SIGNAL TACLK ACLK SMCLK 12 - P1.0 18 - P1.2 18 - P1.2 TACLK TA0 TA0 DVSS DVCC 17 - P1.1 17 - P1.1 TA1 TA1 DVSS DVCC DVSS ACLK (internal) DVSS DVCC MODULE INPUT NAME TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCR2 TA2 12 - P1.0 22 - P1.6 CCR1 TA1 17 - P1.1 23 - P1.7 CCR0 TA0 18 - P1.2 24 - P2.0 Timer NA MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER 24-PIN PW
USART0
The MSP430AFE2xx devices have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART0 module supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. The maximum operational frequency for the USART0 module is 8 MHz.
Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16x16, 16x8, 8x16, and 8x8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required.
SD24_A
The SD24_A module integrates up to three independent 24-bit sigma-delta A/D converters. Each channel is designed with fully differential analog input pair and programmable gain amplifier input stage. In addition to external analog inputs, an internal VCC sense and temperature sensor are also available.
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Peripheral File Map

Table 15. Peripherals With Word Access
Timer_A3 Capture/compare register 2 Capture/compare register 1 Capture/compare register 0 Timer_A register Capture/compare control 2 Capture/compare control 1 Capture/compare control 0 Timer_A control Timer_A interrupt vector Hardware Multiplier Sum extend Result high word Result low word Second operand Multiply signed + accumulate/operand 1 Multiply + accumulate/operand 1 Multiply signed/operand 1 Multiply unsigned/operand 1 Flash Memory Flash control 3 Flash control 2 Flash control 1 Watchdog Timer+ SD24_A (also see Table 16) Watchdog/timer control General Control Channel 0 Control Channel 1Control Channel 2 Control Channel 0 conversion memory Channel 1 conversion memory Channel 2 conversion memory SD24 Interrupt vector word register TACCR2 TACCR1 TACCR0 TAR TACCTL2 TACCTL1 TACCTL0 TACTL TAIV SUMEXT RESHI RESLO OP2 MACS MAC MPYS MPY FCTL3 FCTL2 FCTL1 WDTCTL SD24CTL SD24CCTL0 SD24CCTL1 SD24CCTL2 SD24MEM0 SD24MEM1 SD24MEM2 SD24IV 0x0176 0x0174 0x0172 0x0170 0x0166 0x0164 0x0162 0x0160 0x012E 0x013E 0x013C 0x013A 0x0138 0x0136 0x0134 0x0132 0x0130 0x012C 0x012A 0x0128 0x0120 0x0100 0x0102 0x0104 0x0106 0x0110 0x0112 0x0114 0x01AE
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Table 16. Peripherals With Byte Access

SD24_A (also see Table 15) Channel 0 Input Control Channel 1 Input Control Channel 2 Input Control Channel 0 Preload Channel 1 Preload Channel 2 Preload Reserved (Internal SD24_A Configuration 1) USART0 Transmit buffer Receive buffer Baud rate Baud rate Modulation control Receive control Transmit control USART control Basic Clock System+ Basic clock system control 3 Basic clock system control 2 Basic clock system control 1 DCO clock frequency control Brownout, SVS Port P2 SVS control register (reset by brownout signal) Port P2 selection 2 Port P2 resistor enable Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input Port P1 Port P1 selection 2 register Port P1 resistor enable Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input Special Function SFR module enable 2 SFR module enable 1 SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1 SD24INCTL0 SD24INCTL1 SD24INCTL2 SD24PRE0 SD24PRE1 SD24PRE2 SD24CONF1 U0TXBUF U0RXBUF U0BR1 U0BR0 U0MCTL U0RCTL U0TCTL U0CTL BCSCTL3 BCSCTL2 BCSCTL1 DCOCTL SVSCTL P2SEL2 P2REN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN P1SEL2 P1REN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN ME2 ME1 IFG2 IFG1 IE2 IE1 0x00B0 0x00B1 0x00B2 0x00B8 0x00B9 0x00BA 0x00BF 0x0077 0x0076 0x0075 0x0074 0x0073 0x0072 0x0071 0x0070 0x0053 0x0058 0x0057 0x0056 0x0055 0x0042 0x002F 0x002E 0x002D 0x002C 0x002B 0x002A 0x0029 0x0028 0x0041 0x0027 0x0026 0x0025 0x0024 0x0023 0x0022 0x0021 0x0020 0x0005 0x0004 0x0003 0x0002 0x0001 0x0000
15

Absolute Maximum Ratings (1)

Voltage applied at VCC to VSS Voltage applied to any pin (2) Diode current at any device terminal Storage temperature, Tstg (3) (1) (2) (3) Unprogrammed device Programmed device -0.3 V to 4.1 V -0.3 V to VCC + 0.3 V 2 mA -55C to 150C -40C to 85C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
(2)
Recommended Operating Conditions (1)
MIN
(1)
NOM
MAX 3.6 3.6
UNIT V V V
VCC
Supply voltage
AVCC = DVCC = VCC
During program execution (3) During program/erase flash memory
1.8 2.2 0 -40
VSS TA fSYSTEM
Supply voltage Operating free-air temperature Processor frequency (maximum MCLK frequency) (1) (2) (see Figure 1)
AVSS = DVSS = VSS VCC = 1.8 V, Duty cycle = 50% 10% VCC = 2.7 V, Duty cycle = 50% 10% VCC 3.3 V, Duty cycle = 50% 10% dc dc dc
85 4.15 9 12
C MHz
(1) (2) (3)
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet. The operating voltage range for SD24_A is 2.5 V to 3.6 V
Legend : 12 MHz System Frequency MHz Supply voltage range during flash memory programming 9 MHz Supply voltage range during program execution
6.5 MHz 4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V
3.6 V
Supply Voltage V
A. B.
Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V. If high frequency crystal used is above 12 MHz and selected to source CPU clock then MCLK divider should be programmed appropriately to run CPU below 8 MHz.
Figure 1. Operating Area
16

Active Mode Supply Current (into DVCC + AVCC) Excluding External Current (1)
PARAMETER TEST CONDITIONS fDCO = fMCLK = fSMCLK = DCO default frequency (approximately 1 MHz), fACLK = fVLO = 12 kHz, Program executes in flash, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 fDCO = fMCLK = fSMCLK = 12 MHz, fACLK = fVLO = 12 kHz, Program executes in flash, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 TA VCC 2.2 V MIN TYP 220 A MAX UNIT
IAM,
1MHz
Active mode (AM) current at 1 MHz
3V
350
IAM,
12MHz
Active mode (AM) current at 12 MHz
3.3 V
4.0
4.5
mA
(1)
All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
Typical Characteristics Active-Mode Supply Current (Into DVCC + AVCC)

5 fDCO = 12 MHz 4.5
4 3.5
Active Mode Supply Current - mA
Active Mode Supply Current - mA
4 3.5 3 2.5 2 1.5 1 0.5 0 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 VCC - Supply Voltage - V fDCO = 1 MHz fDCO = 8 MHz
3 2.5 2 1.5 1 0.5 0 0 2
VCC = 3 V, TA = 85C VCC = 3 V, TA = 25C VCC = 2.2 V, TA = 85C
VCC = 2.2 V, TA = 25C
4 6 8 fDCO - DCO Frequency - MHz
10
12
Figure 2. Active-Mode Current vs VCC, TA = 25C
Figure 3. Active-Mode Current vs DCO Frequency
17

SLAS701A NOVEMBER 2010 REVISED MARCH 2011 www.ti.com (1)
Low-Power-Mode Supply Currents (Into VCC) Excluding External Current

PARAMETER TEST CONDITIONS fMCLK = 0 MHz, fSMCLK = fDCO = DCO default frequency (approximately 1 MHz), fACLK = fVLO = 12 kHz, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 fMCLK = fSMCLK = 0 MHz, fDCO = DCO default frequency (approximately 1 MHz), fACLK = fVLO = 12 kHz, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = fVLO = 12 kHz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = fVLO = 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 TA VCC
MIN
TYP
MAX
UNIT
ILPM0
Low-power mode 0 (LPM0) current (2)
25C
2.2 V
65
ILPM2
25C
2.2 V
22
ILPM3,VLO
25C 25C 85C
2.2 V
0.5 0.1
1.0 0.7 2.5
ILPM4
2.2 V
1.1
(1) (2) (3) (4)
All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. Current for brownout and WDT clocked by SMCLK included. Current for brownout and WDT clocked by ACLK included. Current for brownout included.
Typical Characteristics LPM4 Current

6.0 VCC = 3.6 V VCC = 3 V 5.0
ILPM4 - Low-power Mode Current - A
VCC = 2.2 V 4.0 VCC = 1.8 V
3.0
2.0
1.0
0.0 -40
-20
20
40
60
80
100
120
TA - Temperature - C
Figure 4. ILPM4 -- LPM4 Current vs Temperature
18

Schmitt-Trigger Inputs (Ports Px and RST/NMI)

PARAMETER VIT+ VITVhys RPull CI Positive-going input threshold voltage Negative-going input threshold voltage Input voltage hysteresis (VIT+ - VIT-) Pullup/pulldown resistor (not RST/NMI pin) Input capacitance For pullup: VIN = VSS; For pulldown: VIN = VCC VIN = VSS or VCC TEST CONDITIONS VCC 3V 3V 3V 3V MIN 0.45 VCC 1.35 0.25 VCC 0.75 0.3 20 35 5 TYP MAX 0.75 VCC 2.25 0.55 VCC 1.65 1.0 50 UNIT V V V k pF
Leakage Current (Ports Px)

PARAMETER Ilkg(Px.y) (1) (2) High-impedance leakage current
(1) (2)
TEST CONDITIONS
VCC 3V
MIN
TYP
MAX 50
UNIT nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled.
Outputs (Ports Px)

PARAMETER VOH VOL (1) High-level output voltage Low-level output voltage TEST CONDITIONS IOH(max) = -6 mA (1) IOL(max) = 6 mA (1) VCC 3V 3V MIN TYP VCC 0.2 VSS + 0.2 MAX UNIT V V
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.
Output Frequency (Ports Px)

PARAMETER fPx.y fPort_CLK (1) (2) Port output frequency (with load) Clock output frequency TEST CONDITIONS Px.y, CL = 20 pF, RL = 1 k (1) (2) Px.y, CL = 20 pF
(2)
VCC 3V 3V
MIN
TYP 12 16
MAX
UNIT MHz MHz
A resistive divider with two 0.5-k resistors between VCC and VSS is used as load. The output is connected to the center tap of the divider. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
19

Typical Characteristics Outputs

One output loaded at a time.
TYPICAL LOW -LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOL TAGE
25.0 I OL Typical Low-Level Output Current mA
I OL Typical Low-Level Output Current mA 50.0
TYPICAL LOW -LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOL TAGE

VCC = 3 V P1.0 40.0 TA = 85C 30.0
VCC = 2.2 V P1.0 20.0
TA = 25C TA = 85C
TA = 25C
15.0
10.0
20.0
5.0
10.0
0.0 0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOL Low-Level Output V oltage V
VOL Low-Level Output V oltage V
Figure 5.
Figure 6.
TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE

0.0 I OH Typical High-Level Output Current mA I OH Typical High-Level Output Current mA VCC = 2.2 V P1.0 5.0 0.0
TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE

VCC = 3 V P1.0 10.0
10.0
20.0
15.0
30.0
20.0
TA = 85C TA = 25C 0.5 1.0 1.5 2.0 2.5 VOH High-Level Output V oltage V
40.0
TA = 85C
25.0 0.0
50.0 0.0
TA = 25C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH High-Level Output V oltage V
Figure 7.
Figure 8.
20

www.ti.com SLAS701A NOVEMBER 2010 REVISED MARCH 2011 (2)
POR/Brownout Reset (BOR) (1)

PARAMETER VCC(start) V(B_IT-) Vhys(B_IT-) td(BOR) t(reset) (1) (2) See Figure 9
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST CONDITIONS dVCC/dt 3 V/s dVCC/dt 3 V/s dVCC/dt 3 V/s VCC MIN TYP 0.7 V(B_IT-) 1.42 120 2000 3V 2 MAX UNIT V V mV s s
See Figure 9 through Figure 11 See Figure 9 See Figure 9 Pulse length needed at RST/NMI pin to accepted reset internally
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) + Vhys(B_IT) is 1.8 V. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-). The default DCO settings must not be changed until VCC VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
VCC Vhys(B_IT) V(B_IT) VCC(start)
0 t d(BOR)
Figure 9. POR/Brownout Reset (BOR) vs Supply Voltage
21

Typical Characteristics POR/Brownout Reset (BOR)

2 VCC = 3 V Typical Conditions VCC(drop) V 1.5 1 0.5 0 0.001 VCC(drop) VCC 3V t pw
1 t pw Pulse Width s
1000 1 ns 1 ns t pw Pulse Width s
Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC 2 VCC = 3 V VCC(drop) V 1.5 1 VCC(drop) 0.5 0 0.001 tf = tr 1 t pw Pulse Width s 1000 tf tr Typical Conditions 3V t pw
t pw Pulse Width s
Figure 11. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
22

Supply Voltage Supervisor (SVS) / Supply Voltage Monitor (SVM) (1)

PARAMETER t(SVSR) td(SVSon) tsettle V(SVSstart) dVCC/dt 30 V/ms SVS on, switch from VLD = 0 to VLD 0, VCC =3 V VLD 0
(2)
TEST CONDITIONS dVCC/dt > 30 V/ms (see Figure 12)
MIN
TYP 100 2000 100 12 1.55
MAX
UNIT s s s
VLD 0, VCC/dt 3 V/s (see Figure 12) VCC/dt 3 V/s (see Figure 12) VLD = 1 VLD = 2 to 14 VLD = 15 VLD = 1 VLD = 2 VLD = 3 VLD = 4 VLD = 5 VLD = 6 VCC/dt 3V/s (see Figure 12) VLD = 7 VLD = 8 VLD = 9 VLD = 10 VLD = 11 VLD = 12 VLD = 13 VLD = 14 VCC/dt 3 V/s (see Figure 12), external voltage applied on SVSIN VLD = 15 1.1 3.24 2.69 2.24 1.8
1.7
V mV mV mV
120 15 10 1.9 2.1 2.2 2.3 2.4 2.5 2.65 2.8 2.9 3.05 3.2 3.35 3.5 3.76 (3) 3.7 (3) 1.2 12 1.3 17 3.13 2.6 2.05
Vhys(SVS_IT-) VCC/dt 3 V/s (see Figure 12), external voltage applied on SVSIN
V(SVS_IT-)
ICC(SVS) (1) (2) (3)
(1)
VLD 0, VCC = 3 V
The current consumption of the SVS module is not included in the ICC current consumption data. tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD 0 to a different VLD value somewhere between 2 and 15. The overdrive is assumed to be > 50 mV. The recommended operating voltage range is limited to 3.6 V.
23

Typical Characteristics SVS

Software sets VLD > 0: SVS is active AVCC V(SVS_IT- ) V(SVSstart) V(B_IT- ) VCC(start) Brownout Region Brownout Region Vhys(SVS_IT- ) Vhys(B_IT- ) -
Brownout 1 0 SVS out 1 0 Set PO R 1 0
t d(BOR)
SVS CircuitisActiveFromVLD>toV
CC
< V(B_IT- ) -
td(BOR)
td(SVSon) undefined
td(SVSR)
Figure 12. SVS Reset (SVSR) vs Supply Voltage
VCC 3V
t pw
2 Rectangular D rop 1.5 VCC(min) Triangular D rop 1 1 ns 0.5 VCC 3V t pw 1n s
VCC(min) - V -
0 1 10 100 1000 VCC(min) tf = tr tf tr tpw Pulse Width s
t Pulse Width s
Figure 13. VCC(min) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
24

Main DCO Characteristics

All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:
faverage = 32 fDCO(RSEL,DCO) fDCO(RSEL,DCO+1) MOD fDCO(RSEL,DCO) + (32 MOD) fDCO(RSEL,DCO+1)
DCO Frequency
PARAMETER RSELx < 14 VCC fDCO(0,0) fDCO(0,3) fDCO(1,3) fDCO(2,3) fDCO(3,3) fDCO(4,3) fDCO(5,3) fDCO(6,3) fDCO(7,3) fDCO(8,3) fDCO(9,3) fDCO(10,3) fDCO(11,3) fDCO(12,3) fDCO(13,3) fDCO(14,3) fDCO(15,3) fDCO(15,7) SRSEL SDCO Supply voltage range DCO frequency (0, 0) DCO frequency (0, 3) DCO frequency (1, 3) DCO frequency (2, 3) DCO frequency (3, 3) DCO frequency (4, 3) DCO frequency (5, 3) DCO frequency (6, 3) DCO frequency (7, 3) DCO frequency (8, 3) DCO frequency (9, 3) DCO frequency (10, 3) DCO frequency (11, 3) DCO frequency (12, 3) DCO frequency (13, 3) DCO frequency (14, 3) DCO frequency (15, 3) DCO frequency (15, 7) Frequency step between range RSEL and RSEL+1 Frequency step between tap DCO and DCO+1 Duty cycle RSELx = 14 RSELx = 15 RSELx = 0, DCOx = 0, MODx = 0 RSELx = 0, DCOx = 3, MODx = 0 RSELx = 1, DCOx = 3, MODx = 0 RSELx = 2, DCOx = 3, MODx = 0 RSELx = 3, DCOx = 3, MODx = 0 RSELx = 4, DCOx = 3, MODx = 0 RSELx = 5, DCOx = 3, MODx = 0 RSELx = 6, DCOx = 3, MODx = 0 RSELx = 7, DCOx = 3, MODx = 0 RSELx = 8, DCOx = 3, MODx = 0 RSELx = 9, DCOx = 3, MODx = 0 RSELx = 10, DCOx = 3, MODx = 0 RSELx = 11, DCOx = 3, MODx = 0 RSELx = 12, DCOx = 3, MODx = 0 RSELx = 13, DCOx = 3, MODx = 0 RSELx = 14, DCOx = 3, MODx = 0 RSELx = 15, DCOx = 3, MODx = 0 RSELx = 15, DCOx = 7, MODx = 0 SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO) SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO) Measured at SMCLK output 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 8.6 TEST CONDITIONS VCC MIN 1.8 2.2 3.0 0.06 0.10 0.12 0.15 0.21 0.30 0.41 0.58 0.80 1.15 1.60 2.30 3.40 4.25 5.80 7.80 11.25 15.30 21.00 1.35 1.08 50 13.9 TYP MAX 3.6 3.6 3.6 0.14 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz M Hz MHz MHz MHz MHz ratio ratio % V UNIT
25

Calibrated DCO Frequencies Tolerance

PARAMETER 8-MHz tolerance over temperature (1) 8-MHz tolerance over VCC TEST CONDITIONS BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30C and 3.3V BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30C and 3.3V BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30C and 3.3V BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30C and 3.3V BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30C and 3.3V BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30C and 3.3V TA 0C to 85C VCC 3.3 V MIN 7.76 TYP 8 MAX 8.24 UNIT MHz
30C
2.7 V to 3.6 V
7.76
8.24
MHz
8-MHz tolerance overall 12-MHz tolerance over temperature (1) 12-MHz tolerance over VCC
-40C to 85C
2.7 V to 3.6 V
7.52
8.48
MHz
0C to 85C
3.3 V
11.64
12
12.36
MHz
30C
3.3 V to 3.6 V
11.64
12
12.36
MHz
12-MHz tolerance overall (1)
-40C to 85C
3.3 V to 3.6 V
11.28
12
12.72
MHz
This is the frequency change from the measured frequency at 30C over temperature.
Wake-Up From Lower-Power Modes (LPM3/4)

PARAMETER tDCO,LPM3/4 tCPU,LPM3/4 (1) (2) DCO clock wake-up time from LPM3/4 (1) CPU wake-up time from LPM3/4 (2) TEST CONDITIONS fDCO = DCO default frequency (approximately 1 MHz) VCC 3V MIN TYP 1.5 1 / fMCLK + tDCO,LPM3/4 MAX UNIT s s
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK). Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics DCO Clock Wake-Up Time From LPM3/4
10.00 DCO Wake Time us
RSELx = 0...11 1.00 RSELx = 12...15
0.10 0.10
1.00 DCO Frequency MHz
10.00
Figure 14. Clock Wake-Up Time From LPM3 vs DCO Frequency
26

Internal Very-Low-Power Low-Frequency Oscillator (VLO)

PARAMETER fVLO dfVLO/dT dfVLO/dVCC (1) (2) VLO frequency VLO frequency temperature drift (1) VLO frequency supply voltage drift (2) TA -40C to 85C -40C to 85C 25C VCC 3V 3V 1.8 V to 3.6 V MIN 4 TYP 12 0.5 4 MAX 22 UNIT kHz %/C %/V
Calculated using the box method: [MAX(-40...85C) - MIN(-40...85C)]/MIN(-40...85C)/[85C - (-40C)] Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V)
Crystal Oscillator (XT2) (1)

PARAMETER fXT2,HF0 fXT2,HF1 XT2 oscillator crystal frequency, HF mode 0 XT2 oscillator crystal frequency, HF mode 1 XT2 oscillator crystal frequency, HF mode 2 XT2 oscillator logic-level square-wave input frequency, HF mode TEST CONDITIONS XT2OFF = 0, XT2Sx = 0 XT2OFF = 0, XT2Sx = 1 VCC 1.8 V to 3.6 V 1.8 V to 3.6 V 1.8 V to 2.2 V fXT2,HF2 XT2OFF = 0, XT2Sx = 2 2.2 V to 3.0 V 3.0 V to 3.6 V 1.8 V to 2.2 V XT2OFF = 0, XT2Sx = 3 XT2OFF = 0, XT2Sx = 0 fXT2,HF = 1 MHz, CL,eff = 15 pF OAHF Oscillation allowance for HF crystals (see Figure 15 and Figure 16) XT2OFF = 0, XT2Sx = 1 fXT2,HF = 4 MHz, CL,eff = 15 pF XT2OFF = 0, XT2Sx = 2 fXT2,HF = 16 MHz, CL,eff = 15 pF CL,eff Integrated effective load capacitance, HF mode (2) XT2OFF = 0 (3) XT2OFF = 0, Measured at P1.0/SVSIN/TACLK/SMCLK/TA2, fXT2,HF = 10 MHz XT2OFF = 0, Measured at P1.0/SVSIN/TACLK/SMCLK/TA2, fXT2,HF = 16 MHz
(4)
MIN 0.4 1 2 2 2 0.4 0.4 0.4
TYP
MAX 1 4 10 12 16 10 12 16
UNIT MHz MHz
MHz
fXT2,HF,logic
2.2 V to 3.0 V 3.0 V to 3.6 V
MHz
2700
800
300 1 40 3V 40 3V 30 50 60 300 kHz 50 60 % pF
Duty cycle
fFault,HF (1)
Oscillator fault frequency
XT2OFF = 0, XT2Sx = 3 (5)
(2) (3) (4) (5)
To improve EMI on the XT2 oscillator the following guidelines should be observed: (a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT. (d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and frequencies in between might set the flag. Measured with logic-level input frequency, but also applies to operation with crystals.
27

Typical Characteristics XT2 Oscillator

100000.00 1800.0 1600.0 XT Oscillator Supply Current uA Oscillation Allowance Ohms 10000.00 1400.0 1200.0 1000.0 800.0 600.0 400.0 LFXT1Sx = 1 200.0 10.00 100.00 0.0 0.0 LFXT1Sx = 0 4.0 8.0 12.0 16.0 20.0 Crystal Frequency MHz LFXT1Sx = 2
1000.00
LFXT1Sx = 2 100.00 LFXT1Sx = 1 LFXT1Sx = 0 10.00 0.10 1.00
Crystal Frequency MHz
Figure 15. Oscillation Allowance vs Crystal Frequency, CL,eff = 15 pF, TA = 25C
Figure 16. XT2 Oscillator Supply Current vs Crystal Frequency, CL,eff = 15 pF, TA = 25C
SD24_A, Power Supply and Recommended Operating Conditions

PARAMETER AVCC Analog supply voltage TEST CONDITIONS AVCC = DVCC AVSS = DVSS = 0 V GAIN: 1, 2 ISD24 Analog supply current: 1 active SD24_A channel including internal reference SD24LP = 0, fSD24 = 1 MHz, SD24OSR = 256 SD24LP = 1, fSD24 = 0.5 MHz, SD24OSR = 256 GAIN: 4, 8, 16 GAIN: 32 GAIN: 1 GAIN: 32 3V 0.03 0.03 3V VCC MIN 2.5 800 900 1200 800 900 1 0.5 1.1 MHz A TYP MAX 3.6 1100 UNIT V
fSD24
Analog front-end input clock frequency
SD24LP = 0 (low-power mode disabled) SD24LP = 1 (low-power mode enabled)
28

SD24_A, Input Range (1)

PARAMETER Differential full scale input voltage range TEST CONDITIONS Bipolar mode, SD24UNI = 0 Unipolar mode, SD24UNI = 1 SD24GAINx = 1 SD24GAINx = 2 VID Differential input voltage range for specified performance (2) SD24REFON = 1 SD24GAINx = 4 SD24GAINx = 8 SD24GAINx = 16 SD24GAINx = 32 ZI ZID VI VIC (1) (2) Input impedance (one input pin to AVSS) Differential input impedance (IN+ to IN-) Absolute input voltage range Common-mode input voltage range fSD24 = 1 MHz fSD24 = 1 MHz SD24GAINx = 1 SD24GAINx = 32 SD24GAINx = 1 SD24GAINx = 32 3V 3V 300 100 AVSS - 1 AVSS - 1 VCC MIN -VREF / 2GAIN 0 500 250 125 62 31 15 200 75 400 150 AVCC AVCC k k V V mV TYP MAX +VREF / 2GAIN +VREF / 2GAIN UNIT
VID,FSR
mV
All parameters pertain to each SD24_A channel. The full-scale range is defined by VFSR+ = +(VREF/2)/GAIN and VFSR- = -(VREF/2)/GAIN. If VREF is sourced externally, the analog input range should not exceed 80% of VFSR+ or VFSR-; that is, VID = 0.8 VFSR- to 0.8 VFSR+. If VREF is sourced internally, the given VID ranges apply.
SD24_A, Performance (fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1)

PARAMETER TEST CONDITIONS SD24GAINx = 1 SD24GAINx = 2 G Nominal gain SD24GAINx = 4 SD24GAINx = 8 SD24GAINx = 16 SD24GAINx = 32 EOS EOS/T Offset error Offset error temperature coefficient Common-mode rejection ratio AC power supply rejection ratio Crosstalk SD24GAINx = 1 SD24GAINx = 32 SD24GAINx = 1 SD24GAINx = 32 SD24GAINx = 1, Common-mode input signal: VID = 500 mV, fIN = 50 Hz, 100 Hz SD24GAINx = 32, Common-mode input signal: VID = 16 mV, fIN = 50 Hz, 100 Hz SD24GAINx = 1, VCC = 3 V 100 mV, fVCC = 50 Hz SD24GAINx = 1, VID = 500 mV, fIN = 50 Hz, 100 Hz 3V 3V 4 20 >90 3V >75 3V 3V >80 <-100 dB dB dB 3V VCC MIN TYP 1 1.96 3.86 7.62 15.04 28.35 0.2 1.5 20 100 %FSR ppm FSR/C MAX UNIT
CMRR
AC PSRR XT
29

SD24_A, Temperature Sensor and Built-In VCC Sense

PARAMETER TCSensor VOffset,sensor VSensor VCC,Sense RSource,VCC (1) (2) Sensor temperature coefficient Sensor offset voltage Sensor output voltage (1) (2) VCC divider at input 5 Source resistance of VCC divider at input 5 Temperature sensor voltage at TA = 85C Temperature sensor voltage at TA = 30C fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1 3V TEST CONDITIONS VCC MIN 1.18 -100 420 350 475 402 VCC/1 1 20 TYP 1.32 MAX 100 515 442 UNIT mV mV V k 1.46 mV/C
The following formula can be used to calculate the temperature sensor output voltage: VSensor,typ = TCSensor (273 + T [C]) + VOffset,sensor [mV] Results based on characterization and/or production test, not TCSensor or VOffset,sensor. Measured with fSD24 = 1 MHz, SD24OSRx = 256, SD24REFON = 1.
SD24_A, Built-In Voltage Reference

PARAMETER VREF IREF TC CREF ILOAD tON DC PSR (1) (2) Internal reference voltage Reference supply current Temperature coefficient VREF load capacitance VREF(I) maximum load current Turn-on time DC power supply rejection VREF/VCC TEST CONDITIONS SD24REFON = 1, SD24VMIDON = 0 SD24REFON = 1, SD24VMIDON = 0 SD24REFON = 1, SD24VMIDON = 0 (1) SD24REFON = 1, SD24VMIDON = 0 (2) SD24REFON = 1, SD24VMIDON = 0 SD24REFON = 01, SD24VMIDON = 0, CREF = 100nF SD24REFON = 1, SD24VMIDON = 0, VCC = 2.5 V to 3.6 V 3V 3V 5 100 VCC 3V 3V 3V MIN 1.14 TYP 1.2 200 18 100 200 MAX 1.26 320 50 UNIT V A ppm/C nF nA ms V/V
Calculated using the box method: (MAX(-40...85C) - MIN(-40...85C)) / MIN(-40...85C) / (85C - (-40C)) There is no capacitance required on VREF. However, a capacitance of at least 100 nF is recommended to reduce any reference voltage noise.
SD24_A, Reference Output Buffer

PARAMETER VREF,BUF IREF,BUF CREF(O) ILOAD,Max Reference buffer output voltage TEST CONDITIONS SD24REFON = 1, SD24VMIDON = 1 VCC 3V 3V 470 3V 3V 3V -15 100 1 +15 MIN TYP 1.2 430 650 MAX UNIT V A nF mA mV s
Reference supply + reference output buffer quiescent SD24REFON = 1, SD24VMIDON = 1 current Required load capacitance on VREF Maximum load current on VREF SD24REFON = 1, SD24VMIDON = 1 SD24REFON = 1, SD24VMIDON = 1
Maximum voltage variation vs |ILOAD| = 0 to 1 mA load current tON Turn-on time SD24REFON = 01, SD24VMIDON = 01, CREF = 470 nF
30

SD24_A, External Reference Input

PARAMETER VREF(I) Input voltage range IREF(I) Input current TEST CONDITIONS SD24REFON = 0 SD24REFON = 0 VCC 3V 3V MIN 1.0 TYP 1.25 MAX 1.5 50 UNIT V nA
USART0
PARAMETER fUSART USART clock frequency t() (1) USART0: deglitch time
(1)
TEST CONDITIONS VCC = 3 V, SYNC = 0, UART mode
MIN 150
TYP 280
MAX 8 500
UNIT MHz ns
The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t() to ensure that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD0 line.
Timer_A3
PARAMETER fTA tTA,cap Timer_A3 clock frequency Timer_A3, capture timing TEST CONDITIONS SMCLK, Duty cycle = 50% 10% TA0, TA1 3V 20 VCC MIN TYP fSYSTEM MAX UNIT MHz ns
Flash Memory
PARAMETER VCC(PGM/ERASE) fFTG IPGM IERASE tCPT tCMErase tRetention tWord tBlock, tBlock, tBlock,
0 1-63 End
TEST CONDITIONS
VCC
MIN 2.2 257
TYP
MAX 3.6 476
UNIT V kHz mA mA ms ms cycles years tFTG tFTG tFTG tFTG tFTG tFTG
Program and erase supply voltage Flash timing generator frequency Supply current from VCC during program Supply current from VCC during erase Cumulative program time
(1)
2.2 V/3.6 V 2.2 V/3.6 V 2.2 V/3.6 V 2.2 V/3.6 V TJ = 25C

(2) (2) (2) (2) (2) (2)
1 1 20 104 100 30 25 18 6 10593 4819 105
5 7 10
Cumulative mass erase time Program/erase endurance Data retention duration Word or byte program time Block program time for first byte or word Block program time for each additional byte or word Block program end-sequence wait time Mass erase time Segment erase time
tMass Erase tSeg Erase (1) (2)
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. These values are hardwired into the flash controller's state machine (tFTG = 1 / fFTG).
31

RAM
PARAMETER V(RAMh) (1) RAM retention supply voltage
(1)
TEST CONDITIONS CPU halted
MIN 1.6
MAX
UNIT V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition.
JTAG and Spy-Bi-Wire Interface

PARAMETER fSBW tSBW,Low tSBW,En tSBW,Ret fTCK RInternal (1) (2) Spy-Bi-Wire input frequency Spy-Bi-Wire low clock pulse length Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge (1)) Spy-Bi-Wire return to normal operation time TCK input frequency (2) Internal pulldown resistance on TEST TEST CONDITIONS VCC 3V 3V 3V 3V 3V 3V 15 0 25 60 MIN 0 0.025 TYP MAX 20 15 1 100 10 90 UNIT MHz s s s MHz k
Tools accessing the Spy-Bi-Wire interface must wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before applying the first SBWCLK clock edge. fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse (1)

PARAMETER VCC(FB) VFB IFB tFB (1) Supply voltage during fuse-blow condition Voltage level on TEST for fuse blow Supply current into TEST during fuse blow Time to blow fuse TA = 25C TEST CONDITIONS MIN 2.5 6 7 100 1 MAX UNIT V V mA ms
Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, or emulation feature is possible, and JTAG is switched to bypass mode.
32

APPLICATION INFORMATION Port P1 Pin Schematic: P1.0 Input/Output With Schmitt Trigger
Pad Logic To SVS Mux VLD = 15 P1REN.0 DVSS DVCC P1DIR.0 P1SEL2.0 From Timer_A3 SMCLK P1OUT.0 P1SEL.0 P1IN.0 EN To Timer_A3 D P1IE.0 P1IRQ.0 Q Set P1IFG.0 EN 0 1 1 0 P1.0/SVSIN/TACLK/SMCLK/TA2 Bus Keeper EN 0 1 Direction 0: Input 1: Output 0 1 1
P1SEL.0 P1IES.0
Interrupt Edge Select
Table 17. Port P1 (P1.0) Pin Functions

PIN NAME (P1.x) x P1.0 (I/O) SVSIN (VLD = 15) P1.0/SVSIN/TACLK/SMCLK/TA2 0 Timer_A3.TACLK SMCLK Timer_A3.TA2 (1) X = don't care FUNCTION CONTROL BITS / SIGNALS (1) P1DIR.x I: 0, O: 1 X 0 1 1 P1SEL.x 0 X 1 1 1 P1SEL2.x X X 0 1 0
33

Port P1 Pin Schematic: P1.1 and P1.2 Input/Output With Schmitt Trigger
P1REN.x DVSS DVCC P1DIR.x P1SEL2.x From Timer_A3 From SD24_A 0 1 1 0 Bus Keeper EN EN To Timer_A3 D P1IE.x P1IRQ.x Q Set P1IFG.x EN P1.1/TA1/SDCLK P1.2/TA0/SD0DO 0 1 Direction 0: Input 1: Output 0 1 1 Pad Logic
P1OUT.x P1SEL.x P1IN.x
P1SEL.x P1IES.x
Table 18. Port P1 (P1.1 and P1.2) Pin Functions

PIN NAME (P1.x) x P1.1 (I/O) P1.1/TA1/SDCLK 1 Timer_A3.CCI1A and CCI1B Timer_A3.TA1 SDCLK P1.2 (I/O) P1.2/TA0/SD0DO 2 Timer_A3.CCI0A and CCI0B Timer_A3.TA0 SD0DO (1) X = don't care FUNCTION CONTROL BITS / SIGNAL (1) P1DIR.x I: 0, O: 1 0 1 1 I: 0, O: 1 0 1 1 P1SEL.x 0 1 1 1 0 1 1 1 P1SEL2.x X 0 0 1 X 0 0 1
34

Port P1 Pin Schematic: P1.3 Input/Output With Schmitt Trigger

P1REN.3 DVSS P1DIR.3 DVCC 0 1 USART0 direction
SD24_A data
Pad Logic
0 1 1
1 0
P1OUT.3
Direction 0: Input 1: Output
0 1 1 0
P1SEL2.3 P1SEL.3
USART0 data out
P1.3/UTXD0/SD1DO Bus Keeper EN
P1IN.3 EN Not used D P1IE.3 P1IRQ.3 Q Set P1IFG.3 EN
P1SEL.3 P1IES.3

PIN NAME (P1.x) x P1.3 (I/O) P1.3/UTXD0/SD1DO 3 UTXD0 SD1DO (1) X = don't care FUNCTION CONTROL BITS / SIGNALS (1) P1DIR.x I: 0, O: 1 X 1 P1SEL.x 0 1 1 P1SEL2.x X 0 1
35


P1REN.4 DVSS P1DIR.4 DVCC 0 1 USART0 direction
P1SEL2.4
Pad Logic
0 1 1
1 0
P1OUT.4
0 1 Bus Keeper EN P1.4/URXD0/SD2DO
SD24_A data
P1SEL.4
P1IN.4 EN USART0 data in P1IRQ.4 D P1IE.4 Q Set P1IFG.4 EN
P1SEL.4 P1IES.4

PIN NAME (P1.x) x P1.4 (I/O) P1.4/URXD0/SD2DO 4 URXD0 SD2DO (1) X = don't care FUNCTION CONTROL BITS / SIGNALS (1) P1DIR.x I: 0, O: 1 X 1 P1SEL.x 0 1 1 P1SEL2.x X 0 1
36

Port P1 Pin Schematic: P1.5 to P1.7 Input/Output With Schmitt Trigger

P1REN.x Pad Logic
DVSS P1DIR.x 0 1 USART0 direction 1 0

P1OUT.x
0 1 1
DVCC
Module X out
0 1 1 0
P1SEL2.x P1SEL.x
USART0 data out P1IN.x
Bus Keeper EN
P1.5/SIMO0/SVSOUT/TMS P1.6/SOMI0/TA2/TCK P1.7/UCLK0/TA1/TDO/TDI
EN USART0 data in D P1IE.x P1IRQ.x Q Set P1IFG.x EN
P1SEL.x P1IES.x
To JTAG From JTAG From JTAG From JTAG (TDO)
Table 21. Port P1 (P1.5 to P1.7) Pin Functions

CONTROL BITS / SIGNALS (1) PIN NAME (P1.x) x 5 P1.5/SIMO0/SVSOUT/TMS FUNCTION P1.5 (I/O) SIMO0 SVSOUT TMS 6 P1.6/SOMI0/TA2/TCK P1.6 (I/O) SOMI0 Timer_A3.TA2 TCK 7 P1.7/UCLK0/TA1/TDO/TDI P1.7 (I/O) UCLK0 Timer_A3.TA1 TDO/TDI (1) (2) P1DIR.x I: 0; O: 1 X 1 X I: 0; O: 1 X 1 X I: 0; O: 1 X 1 X P1SEL.x 0 1 1 X 0 1 1 X 0 1 1 X P1SEL2.x X 0 1 X X 0 1 X X 0 1 X JTAG Mode (2) 0 0 0 1 0 0 0 1 0 0 0 1
X = don't care JTAG Mode is not a register bit but signal generated internally when 4-wire JTAG option is selected in IDE
37


P2REN.0 Pad Logic
DVSS P2DIR.0 0 1 USART0 direction

Timer_A3 out
0 1 1
DVCC
1 0
P2OUT.0
0 1 1 0
P2SEL2.0 P2SEL.0
USART0 data out P2IN.0
P2.0/STE0/TA0/TDI/TCLK Bus Keeper EN
EN USART0 data in D P2IE.0 P2IRQ.0 Q Set P2IFG.0 EN
P2SEL.0 P2IES.0
To JTAG From JTAG

CONTROL BITS / SIGNALS (1) PIN NAME (P2.x) x 0 P2.0/STE0/TA0/TDI/TCLK P2.0 (I/O) STE0 Timer_A3.TA0 TDI/TCLK (1) (2) FUNCTION P2DIR.x I: 0; O: 1 X 1 X P2SEL.x 0 1 1 X P2SEL2.x X 0 1 X JTAG Mode (2) 0 0 0 1
X = don't care JTAG Mode is not a register bit but signal generated internally when 4-wire JTAG option is selected in IDE
38

Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger

BCSCTL3.XT2Sx = 11 XT2 off P2.7/XT2OUT
0 XT2CLK 1
P2SEL.7
Pad Logic
P2REN.6 DVSS DVCC P2DIR.6 0 1 Direction 0: Input 1: Output 0 1 1
P2OUT.6 Module X OUT P2SEL.6 P2IN.6
0 1 Bus Keeper EN EN P2.6/XT2IN
Module X IN
D P2IE.6 EN Q Set P2IFG.6 P2SEL.6 P2IES.6 Interrupt Edge Select
P2IRQ.6

Pin Name (P2.x) P2.6/XT2IN x 6 P2.6 (I/O) XT2IN (default) FUNCTION CONTROL BITS / SIGNALS P2DIR.6 I: 0; O: 1 0 P2SEL.6 0 1
39

Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger

BCSCTL3.XT2Sx = 11 P2.6/XT2IN XT2 off
0 XT2CLK 1 From P2.6/XT2IN
P2SEL.6
Pad Logic P2REN.7 DVSS DVCC P2DIR.7 0 1 Direction 0: Input 1: Output 0 1 1
P2OUT.7 Module X OUT P2SEL.7 P2IN.7
0 1 Bus Keeper EN EN P2.7/XT2OUT
Module X IN
D P2IE.7 EN Q Set P2IFG.7 P2SEL.7 P2IES.7 Interrupt Edge Select
P2IRQ.7

PIN NAME (P2.x) P2.7/XT2OUT x 7 P2.7 (I/O) XT2OUT (default) FUNCTION CONTROL BITS / SIGNALS P2DIR.7 I: 0, O: 1 0 P2SEL.7 0 1
40

JTAG Fuse Check Mode

MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V or 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense currents are terminated. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR, the fuse check mode has the potential to be activated. The fuse check current flow only when the fuse check mode is active and the TMS pin is in a low state (see Figure 17). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition).
Time TMS Goes Low After POR TMS
ITF ITEST
Figure 17. Fuse Check Mode Current NOTE The CODE and RAM data protection is ensured if the JTAG fuse is blown.
41

REVISION HISTORY
REVISION SLAS701 SLAS701A Product Preview release Production Data release COMMENTS
42
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2011
PACKAGING INFORMATION
Orderable Device MSP430AFE221IPW MSP430AFE221IPWR MSP430AFE222IPW MSP430AFE222IPWR MSP430AFE223IPW MSP430AFE223IPWR MSP430AFE231IPW MSP430AFE231IPWR MSP430AFE232IPW MSP430AFE232IPWR MSP430AFE233IPW MSP430AFE233IPWR MSP430AFE251IPW MSP430AFE251IPWR MSP430AFE252IPW MSP430AFE252IPWR MSP430AFE253IPW Status
(1)
Package Type Package Drawing TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP PW PW PW PW PW PW PW PW PW PW PW PW PW PW PW PW PW
Pins 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24
Package Qty 60 2000 60 2000 60 2000 60 2000 60 2000 60 2000 60 2000 60 2000 60
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
Samples (Requires Login)
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2011
Orderable Device MSP430AFE253IPWR XMS430AFE253IPWR

(1)
Status
(1)
Package Type Package Drawing TSSOP TSSOP PW PW
Pins 24 24
Package Qty 2000
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
Samples (Requires Login)
ACTIVE OBSOLETE
Green (RoHS & no Sb/Br) TBD
CU NIPDAU Level-1-260C-UNLIM Call TI Call TI
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1

www.ti.com SLAS701A NOVEMBER 2010 REVISED MARCH 2011

MIXED SIGNAL MICROCONTROLLER

Copyright 20102011, Texas Instruments Incorporated

MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1

Table 1. Family Members (1)

MSP430AFE253IPW MSP430AFE233IPW MSP430AFE223IPW MSP430AFE252IPW MSP430AFE232IPW MSP430AFE222IPW MSP430AFE251IPW MSP430AFE231IPW MSP430AFE221IPW

(1) (2) (3)

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Copyright 20102011, Texas Instruments Incorporated

MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1

Functional Block Diagram

Hardware Multiplier (16x16) MPY, MPYS, MAC, MACS

Port P1 8 I/O Interrupt capability Pull-up/ down resistors

Port P2 3 I/O Interrupt capability Pull-up/ down resistors

12MHz CPU incl. 16 Registers

USART0 UART or SPI Function

Pin Designation, MSP430AFE2x3IPW

A0.0+ A0.0A1.0+ A1.0AVCC AVSS VREF A2.0+ A2.0TEST/SBWTCK RST/NMI/SBWTDIO P1.0/SVSIN/TACLK/SMCLK/TA2

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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1

Pin Designation, MSP430AFE2x2IPW

A0.0+ A0.0A1.0+ A1.0AVCC AVSS VREF NC NC TEST/SBWTCK RST/NMI/SBWTDIO P1.0/SVSIN/TACLK/SMCLK/TA2

Connect NC pins to analog ground (AVSS)

Pin Designation, MSP430AFE2x1IPW

A0.0+ A0.0NC NC AVCC AVSS VREF NC NC TEST/SBWTCK RST/NMI/SBWTDIO P1.0/SVSIN/TACLK/SMCLK/TA2

Connect NC pins to analog ground (AVSS)

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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1

Table 2. Terminal Functions

DVSS P2.6/XT2IN P2.7/XT2OUT DVCC P1.1/TA1/SDCLK

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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1

Table 2. Terminal Functions (continued)

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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1

SHORT-FORM DESCRIPTION CPU

General-Purpose Register General-Purpose Register

General-Purpose Register General-Purpose Register

Table 3. Instruction Word Formats

Table 4. Address Mode Descriptions

EXAMPLE MOV R10,R11 MOV 2(R5),6(R6)

OPERATION R10 R11 M(2+R5) M(6+R6) M(EDE) M(TONI) M(MEM) M(TCDAT)

MOV @R10,Tab(R6) MOV @R10+,R11 MOV #45,TONI

M(R10) M(Tab+R6) M(R10) R11 R10 + 2 R10 #45 M(TONI)

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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1

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MSP430AFE2x3 MSP430AFE2x2 MSP430AFE2x1

Interrupt Vector Addresses

NMIIFG OFIFG ACCVIFG (2)

(Non)maskable, (Non)maskable, (Non)maskable

Maskable Maskable Maskable Maskable Maskable Maskable

0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh 0FFE8h 0FFE6h 0FFE4h

I/O Port P2 (three flags)

(1) (2) (3) (4)