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WAP to design all gates

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity gate is port( in_1 : in STD_LOGIC; in_2 : in STD_LOGIC; out_1 : out STD_LOGIC ); end gate;

--}} End of automatically maintained section

architecture and_df of gate is begin out_1 <= in_1 and in_2;

end and_df;

architecture and_bh of gate is signal inter : std_logic_vector(0 to 1); begin inter <= in_1 & in_2; with inter select out_1 <= '1' when "11", '0' when "01", '0' when "10",

'0' when "00", 'X' when others;

end and_bh;

-------------------------------------------------------------------------------

architecture or_df of gate is begin out_1 <= in_1 or in_2;

end or_df;

architecture or_bh of gate is signal inter : std_logic_vector(0 to 1); begin inter <= in_1 & in_2;

out_1 <= '0' when (inter = "00") else '1' when (inter = "01") else '1' when (inter = "10") else '1' when (inter = "11") else 'X';

end or_bh;

-------------------------------------------------------------------------------architecture not_df of gate is

begin out_1 <= not in_1 ;

end not_df;

architecture not_bh of gate is begin process (in_1) begin if (in_1 ='0') then out_1 <= '1'; elsif (in_1 ='1') then out_1 <= '0'; else out_1 <= 'X'; end if;

end process

end not_bh;

--------------------------------------------------------------------------------

architecture xor_df of gate is begin out_1 <= in_1 xor in_2;

end xor_df;

architecture xor_bh of gate is begin process (in_1, in_2) variable inter : std_logic_vector(0 to 1); begin inter := in_1 & in_2; if (inter ="00") then out_1 <= '0'; elsif (inter ="01") then out_1 <= '1'; elsif (inter ="10") then out_1 <= '1'; elsif (inter ="11") then out_1 <= '0'; else out_1 <= 'X'; end if;

end process; end xor_bh;

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architecture nand_df of gate is begin out_1 <= in_1 nand in_2;

end nand_df;

architecture nand_bh of gate is begin

process (in_1, in_2) variable inter : std_logic_vector(0 to 1); begin inter := in_1 & in_2;

case inter is when "00" => out_1 <= '1'; when "01" => out_1 <= '1'; when "10" => out_1 <= '1'; when "11" => out_1 <= '0'; when others => out_1 <= 'X';

end case; end process ;

end nand_bh;

----------------------------------------------------------------------------------

architecture xnor_df of gate is begin out_1 <= in_1 xnor in_2;

end xnor_df;

library IEEE; use IEEE.STD_LOGIC_1164.all;

pac age my_pac is subtype bitvec is bit_vector ( 3 downto 0); function convert_int(ar : bitvec) return integer; end my_pac ;

pac age body my_pac is

function convert_int (ar : bitvec) return integer is variable result : integer:=0; begin for i in 3 downto 0 loop result := result * 2;

WAP for a Pac age containing a function to convert bit array to integer

if (ar(i) = '1') then result := result + 1; end if;

WAP to design a Decoder

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity decoder is port( input : in STD_LOGIC_VECTOR(1 downto 0); output : out STD_LOGIC_VECTOR(3 downto 0) );

end decoder;

--}} End of automatically maintained section

architecture arch_decd_bh1 of decoder is begin with input select output <= "0001" when "00", "0010" when "01", "0100" when "10", "1000" when "11", "XXXX" when others; end arch_decd_bh1;

architecture arch_decd_bh2 of decoder is begin output <= "0001" when (input = "00") else "0010" when (input = "01") else "0100" when (input = "10") else "1000" when (input = "11") else "XXXX"; end arch_decd_bh2;

architecture arch_decd_bh3 of decoder is begin process (input) begin if (input ="00") then output <= "0001"; elsif (input ="01") then

output <= "0010"; elsif (input ="10") then output <= "0100"; elsif (input ="11") then output <= "1000"; else output <= "XXXX"; end if;

end process end arch_decd_bh3;

architecture arch_decd_bh4 of decoder is begin process (input) begin case input is when "00" => output <= "0001"; when "01" => output <= "0010"; when "10" => output <= "0100"; when "11" => output <= "1000"; when others => output <= "XXXX";

end case; end process ;

end arch_decd_bh4;

architecture arch_decd_df of decoder is begin output(0) <= (not input(0)) and (not input(1)) output(1) <= input(0) and (not input(1)) output(2) <= (not input(0)) and input(1); output(3) <= input(0) and input(1) end arch_decd_df; ; ; ;

WAP to design an Encoder

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity encoder is port( input : in std_logic_vector (3 downto 0); output : out std_logic_vector ( 1 downto 0) ); end encoder;

--}} End of automatically maintained section

architecture arch_encd_bh1 of encoder is begin

with input select output <= "00" when "0001",

"01" when "0010", "10" when "0100", "11" when "1000", "XX" when others; end arch_encd_bh1;

architecture arch_encd_bh2 of encoder is begin output <= "00" when (input = "0001") else "01" when (input = "0010") else "10" when (input = "0100") else "11" when (input = "1000") else "XX"; end arch_encd_bh2;

architecture arch_encd_bh3 of encoder is begin process (input) begin if (input ="0001") then output <= "00"; elsif (input ="0010") then output <= "01"; elsif (input ="0100") then output <= "10"; elsif (input ="1000") then output <= "11"; else output <= "XX"; end if;

end process end arch_encd_bh3;

architecture arch_encd_bh4 of encoder is begin process (input) begin case input is when "0001" => output <= "00"; when "0010" => output <= "01"; when "0100" => output <= "10"; when "1000" => output <= "11"; when others => output <= "XX";

end case; end process end arch_encd_bh4; ;

WAP to design a Magnitude Comparator

library IEEE; use IEEE.STD_LOGIC_1164.all;

use my_pac .all;

entity mag_comp is port( input_a : in bitvec; input_b : in bitvec; a_gr : out bit; b_gr : out bit; equal : out bit ); end mag_comp;

--}} End of automatically maintained section

architecture arch_cmp_func of mag_comp is signal int_a, int_b : integer := 0; begin

int_a <= convert_int(input_a); int_b <= convert_int (input_b);

process(int_a, int_b) variable var_a,var_b,var_eq : bit ; begin

var_a := '0'; var_b := '0'; var_eq := '0';

if (int_a < int_b) then var_b := '1';

elsif (int_a > int_b) then var_a := '1'; elsif (int_a = int_b) then var_eq := '1'; else null; end if;

a_gr <= var_a; b_gr <= var_b; equal <= var_eq;

end process;

end arch_cmp_func;

architecture arch_cmp_bh of mag_comp is begin

process(input_a, input_b) variable var_a,var_b,var_eq : bit ; begin

var_a := '0'; var_b := '0'; var_eq := '0';

if (input_a < input_b) then var_b := '1'; elsif (input_a > input_b) then

var_a := '1'; elsif (input_a = input_b) then var_eq := '1'; else null; end if;

a_gr <= var_a; b_gr <= var_b; equal <= var_eq;

end process; end arch_cmp_bh;

WAP to design a Code converter

library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

-- not bit_vector********************************************** entity cd_cnvrt is port( bcd_input : in std_logic_vector(3 downto 0); excess3_output : out std_logic_vector(3 downto 0) );

begin assert (bcd_input <= "1001")

report "bcd number invalid" severity error;

end cd_cnvrt;

--}} End of automatically maintained section

architecture arch_cdcnvrt_bh1 of cd_cnvrt is constant three : std_logic_vector(3 downto 0):= "0011"; begin

excess3_output <= bcd_input + three;

end arch_cdcnvrt_bh1;

architecture arch_cdcnvrt_df of cd_cnvrt is signal cord : std_logic; begin cord <= bcd_input(1) or bcd_input(0);

excess3_output(0) <= not(bcd_input(0)); excess3_output(1) <= (bcd_input(1) and bcd_input(0)) or ((not(bcd_i nput(0))) and (not(bcd_input(1)))); excess3_output(2) <= (not(bcd_input(2)) and cord) or (bcd_input(2) and (not(cord))) ; excess3_output(3) <= bcd_input(3) or (bcd_input(2) and cord);

end arch_cdcnvrt_df ;

architecture arch_cdcnvrt_bh2 of cd_cnvrt is constant three : std_logic_vector(3 downto 0):= "0011";

begin process (bcd_input) begin if (bcd_input <= "1001") then excess3_output <= bcd_input + three; else excess3_output <= "XXXX"; end if; end process;

end arch_cdcnvrt_bh2;

WAP to design a D-Flip Flop

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity dff is port (cloc , input, reset : in std_logic; output : out std_logic); end dff;

architecture dff_behv of dff is begin process (cloc , input, reset) begin if (reset = 0 ) then

output <= 0 ; elsif (cloc event and cloc = 1 ) then

output <= input; end if; end process; end dff_behv;

WAP to design a JK Flip Flop

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity j ff is

q_output, qbar_output : out std_logic); end j ff;

architecture j ff_behv of j ff is signal inter_in : std_logic_vector (0 to 1); signal inter_st : std_logic; begin inter_in <= j_input & _input;

process ( cloc , reset) begin if (reset = inter_st <= 1 ) then 0 ; 1 ) then

elsif (cloc event and cloc = case inter_in is when 01 =>

inter_st <= 0 ; when 10 =>

port (cloc , j_input,

_input, reset : in std_logic;

inter_st <= when 11 =>

1 ;

inter_st <= not (inter_st); when others => null; end case; end if; end process; q_output <= inter_st; qbar_output <= not (inter_st); end j ff_behv;

WAP to design a Counter (8 bit, asynchronus clear, positive edge trigge red with count enable)

Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all;

Entity counter is Port ( clear, cloc , count_en : in bit; Count :out std_logic_vector (7 downto 0)); End counter;

Architecture count_behv of counter is Signal cnt : std_logic_vector (7 downto 0); Begin

Process (clear, cloc ) Begin

If (clear = '0') then Cnt <= (others => '0');

If (count_en ='1') then Cnt <= cnt + 1; End if; End if; End process;

Count <= cnt;

End count_behv;

WAP to design a 4 bit register (positive edge triggered)

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity Register_4 is port( data_in : in STD_LOGIC_VECTOR(3 downto 0); cloc : in STD_LOGIC; clear : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR(3 downto 0) ); end Register_4;

--}} End of automatically maintained section

Elsif (cloc 'event and cloc

='1') then

architecture arch_reg_bh of Register_4 is begin process (cloc ) begin if clear = '0' then data_out <=(others => '0'); elsif clear = '1' then

data_out <= data_in; end if; end if; end process; end arch_reg_bh;

architecture arch_reg_st of register_4 is component dff is port (cloc , input, reset : in std_logic; output : out std_logic); end component;

begin dff_1 : dff port map (cloc , data_in(0), clear, data_out (0)); dff_2 : dff port map (cloc , data_in(1), clear, data_out (1)); dff_3 : dff port map (cloc , data_in(2), clear, data_out (2)); dff_4 : dff port map (cloc , data_in(3), clear, data_out (3)); end arch_reg_st;

if (cloc 'event and cloc

= '1') then

WAP to design Shift Registers

Pac age used in universal shifter program

Library ieee; Use ieee.std_logic_1164;

Pac age my_pac is Type sel is (load, left, right) End my pac ;

Universal Shift register (with asynchronous clear, parallel and serial load capa bility, parallel output)

Library ieee; Use ieee.std_logic_1164.all; Use my_pac .all;

Entity univ_shifter is Port (cloc , clear, s_in : in bit; D_load : in bit_vector (7 downto 0); P_out : out bit_vector (7 downto 0); Sel_shift : in sel); End univ_shifter;

Architecture shift_behv of univ_shifter is Signal temp : bit_vector (7 downto 0); Begin

Process ( clear, cloc ) Begin

If (clear = 0 ) then Temp <= (others => 0 ); Elsif (cloc event and cloc = 1 ) then Case sel_shift is When load => Temp <= d_load; When left => Temp <= temp (6 downto 0) & s_in; When right => Temp <= s_in & temp (7 downto 1); End case; End if; End process;

P_out <= temp;

End shift_behv;

8-bit Shift-Left Register with Positive-Edge Cloc , Serial In, and Serial Out library ieee; use ieee.std_logic_1164.all; entity shift is port(C, SI : in std_logic; SO : out std_logic); end shift; architecture archi of shift is

signal tmp: std_logic_vector(7 downto 0); begin process (C) begin if (C'event and C='1') then for i in 0 to 6 loop tmp(i+1) = tmp(i); end loop; tmp(0) = SI; end if; end process; SO = tmp(7); end archi; 8-bit Shift-Left Register with Negative-Edge Cloc , Cloc Enable, Serial In, and Serial Out library ieee; use ieee.std_logic_1164.all;

entity shift is port(C, SI, CE : in std_logic; SO : out std_logic); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C) begin if (C'event and C='0') then if (CE='1') then for i in 0 to 6 loop tmp(i+1) = tmp(i); end loop; tmp(0) = SI; end if; end if; end process; SO = tmp(7); end archi; 8-bit Shift-Left Register with Positive-Edge Cloc , Asynchronous Clear, Serial I n, and Serial Out . library ieee; use ieee.std_logic_1164.all;

entity shift is port(C, SI, CLR : in std_logic; SO : out std_logic);

end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C, CLR) begin if (CLR='1') then tmp = (others = '0'); elsif (C'event and C='1') then tmp = tmp(6 downto 0) & SI; end if; end process; SO = tmp(7); end archi; 8-bit Shift-Left Register with Positive-Edge Cloc , Synchronous Set, Serial In, and Serial Out library ieee; use ieee.std_logic_1164.all;

entity shift is port(C, SI, S : in std_logic; SO : out std_logic); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C, S) begin if (C'event and C='1') then if (S='1') then tmp = (others = '1'); else tmp = tmp(6 downto 0) & SI; end if; end if; end process; SO = tmp(7); end archi; 8-bit Shift-Left Register with Positive-Edge Cloc , Serial In, and Parallel Out library ieee; use ieee.std_logic_1164 all;

entity shift is port(C, SI : in std_logic; PO : out std_logic_vector(7 downto 0)); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin

process (C) begin if (C'event and C='1') then tmp = tmp(6 downto 0)& SI; end if; end process; PO = tmp; end archi; 8-bit Shift-Left Register with Positive-Edge Cloc , Asynchronous Parallel Load, Serial In, and Serial Out library ieee; use ieee.std_logic_1164.all;

entity shift is port(C, SI, ALOAD : in std_logic; D : in std_logic_vector(7 downto 0); SO : out std_logic); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C, ALOAD, D) begin if (ALOAD='1') then tmp = D; elsif (C'event and C='1') then tmp = tmp(6 downto 0) & SI; end if; end process; SO = tmp(7); end archi; 8-bit Shift-Left Register with Positive-Edge Cloc , Synchronous Parallel Load, S erial In, and Serial Out library ieee; use ieee.std_logic_1164.all;

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -------------------------------------------------------entity ADDER is generic(n: natural :=2); port( A: in std_logic_vector(n-1 downto 0); B: in std_logic_vector(n-1 downto 0); carry: out std_logic; sum: out std_logic_vector(n-1 downto 0)); end ADDER; -------------------------------------------------------architecture behv of ADDER is signal result: std_logic_vector(n downto 0);

begin result <= ('0' & A)+('0' & B); sum <= result(n-1 downto 0); carry <= result(n); end behv; COMPARATOR library ieee; use ieee.std_logic_1164.all; --------------------------------------------------entity Comparator is generic(n: natural :=2); port( A: in std_logic_vector(n-1 downto 0); B: in std_logic_vector(n-1 downto 0); less: out std_logic; equal: out std_logic; greater: out std_logic); end Comparator; --------------------------------------------------architecture behv of Comparator is begin process(A,B) begin if (A<B) then less <= '1'; equal <= '0'; greater <= '0'; elsif (A=B) then less <= '0'; equal <= '1'; greater <= '0'; else less <= '0'; equal <= '0'; greater <= '1'; end if; end process; end behv; ALU library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; --------------------------------------------------entity ALU is port( A: in std_logic_vector(1 downto 0); B: in std_logic_vector(1 downto 0); Sel: in std_logic_vector(1 downto 0); Res: out std_logic_vector(1 downto 0) ); end ALU; --------------------------------------------------architecture behv of ALU is begin process(A,B,Sel) begin case Sel is when "00" => Res <= A + B; when "01" =>

Res <= A + (not B) + 1; when "10" => Res <= A and B; when "11" => Res <= A or B; when others => Res <= "XX"; end case; end process; end behv; MULTIPLIER library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity multiplier is port( num1, num2: in std_logic_vector(1 downto 0); product: out std_logic_vector(3 downto 0)); end multiplier; architecture behv of multiplier is begin process(num1, num2) variable num1_reg: std_logic_vector(2 downto 0); variable product_reg: std_logic_vector(5 downto 0); begin num1_reg := '0' & num1; product_reg := "0000" & num2; -- use variables doing computation -- algorithm is to repeat shifting/adding for i in 1 to 3 loop if product_reg(0)='1' then product_reg(5 downto 3) := product_reg(5 downto 3) + num1_reg(2 downto 0); end if; product_reg(5 downto 0) := '0' & product_reg(5 downto 1); end loop; product <= product_reg(3 downto 0); end process; end behv; LATCH library ieee ; use ieee.std_logic_1164.all; -------------------------------------------entity D_latch is port( data_in: in std_logic; enable: in std_logic; data_out: out std_logic); end D_latch; -------------------------------------------architecture behv of D_latch is begin -- compare this to D flipflop

process(data_in, enable) begin if (enable='1') then -- no cloc signal here data_out <= data_in; end if; end process; end behv; D FLIP FLOP library ieee ; use ieee.std_logic_1164.all; use wor .all; --------------------------------------------entity dff is port( data_in: in std_logic; cloc : in std_logic; data_out: out std_logic); end dff; ---------------------------------------------architecture behv of dff is begin process(data_in, cloc ) begin -- cloc rising edge if (cloc ='1' and cloc 'event) then data_out <= data_in; end if; end process; end behv; JK FLIP FLOP library ieee; use ieee.std_logic_1164.all; ---------------------------------------------entity JK_FF is port ( cloc : in std_logic; J, K: in std_logic; reset: in std_logic; Q, Qbar: out std_logic); end JK_FF; ----------------------------------------------architecture behv of JK_FF is signal state: std_logic; signal input: std_logic_vector(1 downto 0); begin input <= J & K; p: process(cloc , reset) is begin if (reset='1') then state <= '0'; elsif (rising_edge(cloc )) then case (input) is when "11" => state <= not state; when "10" => state <= '1'; when "01" => state <= '0'; when others =>

null; end case; end if; end process; Q<= state; Qbar <= not state; end behv; REGISTER library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; --------------------------------------------------entity reg is generic(n: natural :=2); port( I: in std_logic_vector(n-1 downto 0); cloc : in std_logic; load: in std_logic; clear: in std_logic; Q: out std_logic_vector(n-1 downto 0)); end reg; ---------------------------------------------------architecture behv of reg is signal Q_tmp: std_logic_vector(n-1 downto 0); begin process(I, cloc , load, clear) begin if clear = '0' then -- use 'range in signal assigment Q_tmp <= (Q_tmp'range => '0'); elsif (cloc ='1' and cloc 'event) then if load = '1' then Q_tmp <= I; end if; end if; end process; Q <= Q_tmp; end behv; SHIFT REGISTER library ieee ; use ieee.std_logic_1164.all; --------------------------------------------------entity shift_reg is port( I: in std_logic; cloc : in std_logic; shift: in std_logic; Q: out std_logic); end shift_reg; --------------------------------------------------architecture behv of shift_reg is signal S: std_logic_vector(2 downto 0):="111"; begin process(I, cloc , shift, S) begin -- everything happens upon the cloc changing if cloc 'event and cloc ='1' then if shift = '1' then S <= I & S(2 downto 1); end if;

end if; end process; Q <= S(0); end behv; COUNTER library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ---------------------------------------------------entity counter is generic(n: natural :=2); port( cloc : in std_logic; clear: in std_logic; count: in std_logic; Q: out std_logic_vector(n-1 downto 0)); end counter; ---------------------------------------------------architecture behv of counter is signal Pre_Q: std_logic_vector(n-1 downto 0); begin process(cloc , count, clear) begin if clear = '1' then Pre_Q <= Pre_Q - Pre_Q; elsif (cloc ='1' and cloc 'event) then if count = '1' then Pre_Q <= Pre_Q + 1; end if; end if; end process; Q <= Pre_Q; end behv;

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