Assign 8: 3 to 8 decoder:

Code: --libraries to be used are specified here library IEEE; use IEEE.STD_LOGIC_1164.ALL; --entity declaration with port definitions entity decoder is port( input : in std_logic_vector(2 downto 0); --3 bit input output : out std_logic_vector(7 downto 0) -- 8 bit ouput ); end decoder; --architecture of entity architecture Behavioral of decoder is begin output(0) output(1) output(2) output(3) output(4) output(5) output(6) output(7)

<= (not input(2)) and (not input(1)) and (not input(0)); <= (not input(2)) and (not input(1)) and input(0); <= (not input(2)) and input(1) and (not input(0)); <= (not input(2)) and input(1) and input(0); <= input(2) and (not input(1)) and (not input(0)); <= input(2) and (not input(1)) and input(0); <= input(2) and input(1) and (not input(0)); <= input(2) and input(1) and input(0);

end Behavioral; RTL View:

Simulation:

Assignment 10: 4 bit comparator

Code: --libraries to be used are specified here library IEEE; use IEEE.STD_LOGIC_1164.ALL; --entity declaration with port definitions entity compare is port( num1 : in std_logic_vector(3 downto 0); --input 1 num2 : in std_logic_vector(3 downto 0); --input 2 less : out std_logic; -- indicates first number is small equal : out std_logic; -- both are equal greater : out std_logic -- indicates first number is bigger ); end compare; --architecture of entity architecture Behavioral of compare is begin process(num1,num2) begin -- process starts with a 'begin' statement if (num1 > num2 ) then --checking whether num1 is greater than num2 less <= '0'; equal <= '0'; greater <= '1'; elsif (num1 < num2) then --checking whether num1 is less than num2 less <= '1'; equal <= '0'; greater <= '0'; else --checking whether num1 is equal to num2 less <= '0'; equal <= '1'; greater <= '0'; end if; end process; -- process ends with a 'end process' statement end Behavioral; RTL View:

Simulation:

Assignment 7: 4X1 Multiplexer Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity multiplexer4_1 is port ( i0 : in std_logic; i1 : in std_logic; i2 : in std_logic; i3 : in std_logic;

sel : in std_logic_vector(1 downto 0); bitout : out std_logic ); end multiplexer4_1; architecture Behavioral of multiplexer4_1 is begin process(i0,i1,i2,i3,sel) begin case sel is when "00" => bitout <= i0; when "01" => bitout <= i1; when "10" => bitout <= i2; when others => bitout <= i3; end case; end process; end Behavioral;

RTL View:

Simulation:

The VHDL code of 4 bit parallel adder is given below --PREPARED BY BIJOY LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FA IS PORT(A,B,CIN:IN STD_LOGIC;SUM,COUT:OUT STD_LOGIC); END FA; ARCHITECTURE BEHV OF FA IS BEGIN SUM<=A XOR B XOR CIN; COUT<=(A AND B) OR (B AND CIN) OR (A AND CIN); END BEHV; -- NOW DESIGN A 4 BIT ADDING UNIT BY CASCADING 4 FULL ADDER UNITS --STRUCTURAL BINDING OF UNITS ENTITY FA LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ADDER_4BIT IS PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);C:OUT STD_LOGIC); END ADDER_4BIT; ARCHITECTURE BEHV OF ADDER_4BIT IS SIGNAL TEMP:STD_LOGIC:='0'; SIGNAL CAR:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN FA1:ENTITY WORK.FA PORT MAP(A(0),B(0),TEMP,S(0),CAR(0)); FA2:ENTITY WORK.FA PORT MAP(A(1),B(1),CAR(0),S(1),CAR(1)); FA3:ENTITY WORK.FA PORT MAP(A(2),B(2),CAR(1),S(2),CAR(2)); FA4:ENTITY WORK.FA PORT MAP(A(3),B(3),CAR(2),S(3),C); END BEHV;

--getting output properly --DIRECT INSTANTIATION IS USED