Combinational Logic Implementation: Multi-Level Networks

Implementations of Two-level Logic

Sum-of-products
AND gates to form product terms
(minterms)
OR gate to form sum
Product-of-sums
OR gates to form sum terms
(maxterms)
AND gates to form product
Two-level Logic using NAND Gates
Replace minterm AND gates with NAND gates
Place compensating inversion at inputs of OR gate
Two-level Logic using NAND Gates (contd)
OR gate with inverted inputs is a NAND gate
de Morgan's: A' + B' = (A B)'
Two-level NAND-NAND network
Inverted inputs are not counted
In a typical circuit, inversion is done once and signal distributed
Two-level Logic using NOR Gates
Replace maxterm OR gates with NOR gates
Place compensating inversion at inputs of AND gate
Two-level Logic using NOR Gates (contd)
AND gate with inverted inputs is a NOR gate
de Morgan's: A' B' = (A + B)'
Two-level NOR-NOR network
Inverted inputs are not counted
In a typical circuit, inversion is done once and signal distributed
OR
NAND
NAND
OR AND
NOR
NOR
AND
Two-level Logic using NAND and NOR Gates
NAND-NAND and NOR-NOR networks
de Morgan's law: (A + B)' = A' B'
(A B)' = A' + B'
written differently: A + B = (A' B')
(A B) = (A' + B')'
In other words
OR is the same as NAND with complemented inputs
AND is the same as NOR with complemented inputs
NAND is the same as OR with complemented inputs
NOR is the same as AND with complemented inputs
A
B
C
D
Z
A
B
C
D
Z
NAND
NAND
NAND
Conversion Between Forms
Convert from networks of ANDs and ORs to networks of NANDs and NORs
Introduce appropriate inversions ("bubbles")
Each introduced "bubble" must be matched by a corresponding "bubble"
Conservation of inversions
Do not alter logic function
Example: AND/OR to NAND/NAND
Z = [ (A B)' (C D)' ]'
= [ (A' + B') (C' + D') ]'
= [ (A' + B')' + (C' + D')' ]
= (A B) + (C D)
Conversion Between Forms (contd)
Example: verify equivalence of two forms
A
B
C
D
Z
A
B
C
D
Z
NAND
NAND
NAND
Z = { [ (A' + B')' + (C' + D')' ]' }'
= { (A' + B') (C' + D') }'
= (A' + B')' + (C' + D')'
= (A B) + (C D)
Conversion Between Forms (contd)
Example: verify equivalence of two forms
A
B
C
D
Z
NOR
NOR
NOR
\A
\B
\C
\D
Z
A
B
C
D
E
F
G
X
Multi-level Logic
x = A D F + A E F + B D F + B E F + C D F + C E F + G
Reduced sum-of-products form already simplified
6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!)
25 wires (19 literals plus 6 internal wires)
x = (A + B + C) (D + E) F + G
Factored form not written as two-level S-o-P
1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate
10 wires (7 literals plus 3 internal wires)
Level 1 Level 2 Level 3 Level 4
original
AND-OR
network
A
C
D
B
B
\C
F
introduction and
conservation of
bubbles
A
C
D
B
B
\C
F
redrawn in terms
of conventional
NAND gates
A
C
D
\B
B
\C
F
Conversion of Multi-level Logic to NAND Gates
F = A (B + C D) + B C'
&
&
+
2x2 AOI gate
symbol
&
&
+
3x2 AOI gate
symbol
NAND NAND
Invert
possible implementation
A
B
C
D
Z
AND OR Invert
logical concept
A
B
C
D
Z
AND-OR-Invert Gates
AOI function: three stages of logicAND, OR, Invert
Multiple gates "packaged" as a single circuit block
14
Combinational Logic: Analysis and Design
15
Combinational Circuits
consists of logic gates with outputs that are
determined entirely by the present value of the inputs
(no memory)
Combinatorial circuits might be 2-level logic (SOP,POS) or
multi-level
o1
o2
om
i1
i2
i3 Comb. Logic
Two important procedure
Analysis Given circuit schematic, explain its
behavior
Design Given the specifications, build it
16
Analysis Procedure
1. Label all logic gate outputs and primary inputs
2. Starting from primary inputs, represent outputs in terms of
their input variables
3. Repeat 2, till you reach output
4. Represent primary output(s) in terms of primary inputs
F
2
= AB +AC +BC
T
1
= A +B +C
T
2
= ABC
T
3
= F
2
T
1
F
1
= T
2
+T
3
Simplify the F
1
17
Design Procedure
1. From Specifications, determine the required number of inputs
and outputs
2. Assign a variable to each input and output
3. Derive a truth Table that defines the required relationship
between inputs and outputs
4. Perform logic minimization
5. Draw the logic diagram
18
Design Procedure - Example
Given input bits in BCD, design a circuit to convert inputs to
Excess-3 code outputs
Input BCD Output Excess-3 Code
A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
19
Example K maps
z = D
y = CD +CD
= CD + (C +D)
x = BC +BD +BCD
= B(C +D) +B(C
+D)
w = A +BC +BD
= A +B(C+D)
20
Example Schematic
21
Binary Adder
Adder is an important component in many logic circuits
Half Adder
(CS)
2
= x plus y
S = xy +xy = xy
C = xy
x y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
x y
C S
HA
22
Full Adder
x y z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
(CS)
2
= x plus y plus z
x y
C S
FA
Z
23
Full Adder K Maps & Schematics
0 1
01 00
0 1
0
1
yz
x
0
1
1
0
11 10
S
x
x
y
y
z
z
x
y
x
x
x
y
y
y
z
z
z
0 0
01 00
1 0
0
1
yz
x
1
1
0
1
11 10
S = xyz +xyz + xyz + xyz = xyz
C = xy +xz +yz
S
C
24
Implementation with 2 Half Adders
x y z
S C
FA
c
2
y x
HA
z
C
HA
s
1
c
1
25
Half Subtractor
Produces x -y
D difference
B Borrow
x y B D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
x y
B D
HS
D = xy +xy = S of half adder
B = xy
26
Full Subtractor
x y z B D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
(x -y) z; where z represents a borrow
D = xyz +xyz + xyz + xyz = xyz = S of
full adder
B = xy +xz +yz (same as C of full adder
except x is inverted
27
Parallel Adder
Often, we must add 2 n bit numbers and carry
Classical approach
(2n + 1) inputs and (n+1) outputs
Design a (n+1) output, 2-level (e.g. SOP) design
Problems
Too many gates
Fan-in is too large
Not practical for n>3
Use iterative circuit, reduced complexity
x1 x2 x3 ..xn zin y1 y2 y3 yn O1On,Zout
N-bit Adder
x
y
zin
O
zout
28
Parallel Adder 4 Bit Adder
For n = 4
Inputs 9
Outputs 5
Power, Gnd 2
A 4 bit adder is accommodated in 16 pin package
(MSI)
b
0
a
0
b
1
b
2
b
n-1
a
1
a
2
a
n-1
s
0
s
1
s
2
s
n-1
c
1
c
2
c
3
c
n-1
c
n
. . .
FA FA FA FA
c
0
29
Parallel Adder - Issues
Fewer gates than 2-level implementation, however
significantly slower Rippling effect of carry
For an n bit adder
Propagation delay = (Average FA delay)x(number of bits)
= 2nxd, where d = Average gate delay
a
i
c
i
s
i
b
i

C
i+1
Carry Ripple
A and B inputs change, corresponding changes to
C
IN
inputs ripple through the circuit.
Full Adder
B A C
IN
C
OUT
SUM
Full Adder
B A C
IN
C
OUT
SUM
Full Adder
B A C
IN
C
OUT
SUM
B
1
A
1
B
0
A
0
B
2
A
2
C
IN
= 0
Q
1
Q
0
Q
2
t = 0, A & B change
t = 30 ns, Adder 0
outputs respond
t = 60 ns, Adder 1
outputs respond
t = 90 ns, Adder 2
outputs respond
Carry-Look-Ahead
The accumulated delay in large parallel adders can be prohibitively large.
Example : 16 bits using 30 ns full-adders :
Solution : Generate the carry-input signals directly from the A and B inputs rather
than using the ripple arrangement.
ns 480 ns 30 16 =
Designing a Carry-Look-Ahead Circuit
B A C
IN2
C
OUT
SUM
B A C
IN1
C
OUT
SUM
B A C
IN0
C
OUT
SUM
Q
2
Q
1
Q
0
Carry-look-
ahead logic
B
2
A
2
B
1
A
1
B
0
A
0
( )
( ) | |( )
1 1 1 1 0 0 0 0
1 1 1 1 1
1 2
B A B A B A B A C
B A B A C
C C
IN
IN
OUT IN
+ + + + =
+ + =
=
C
IN
( )
0 0 0 0
0 1
B A B A C
C C
IN
OUT IN
+ + =
=
IN IN
C C =
0
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 33
Carry Lookahead Adders
s(i)
c(i+1)
x(i)
y(i)
c(i)
g(i)
p(i)
So ripple adders can be slow, but we could calculate the carry ins faster, then we
can build a faster adder.
Consider the i-th bit of the adder, and identify two signals, namely the propagate p
i
and generate g
i
:
Write the carry out c
i+1
in terms of the p
i
and g
i
signals
instead.
S(i)=XOR(p(i)+c(i))
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 34
Writing The Carries In Terms of Propagates and Generates
We can consider writing all the carry outs in terms of the p
i
and g
i
signals, but
substitute previously calculated carries as we go
We have written the carries in terms of values all computed when the inputs are
applied to the circuit:
All p
i
and g
i
are computed after 1 gate delay.
All c
i
are then computed after 2 more gate delays, since the are 2-level SOP in
terms of p
i
and g
i
.
s(i)
c(i+1)
x(i)
y(i)
c(i)
g(i)
p(i)
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 35
Carry Lookahead Performance
If we use carry lookahead to generate all of the carries, then our adder will have a
delay of 3 units of gate delay to get c
n
.
What is the penalty to be paid?
The carry lookahead circuit is 2-level logic (SOP) and we should see that
higher numbered carries require more AND gates as well as AND/OR gates
with a large number of inputs.
It becomes impractical (cant get AND/OR gates with large numbers of
inputs).
It becomes expensive in terms of the number of logic gates required.
So, we get better performance, but we pay for it in terms of area and cost of the
circuit implementation.
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 36
Combining Ripple Adders and Carry Lookahead
We can get something better than a ripple adder, but not as good as full carry
lookahead by cascading smaller carry lookahead adders
E.g., consider a 16-bit adder composed of 4, 4-bit carry lookahead adders.
4-CLA 4-CLA 4-CLA 4-CLA
Performance will be 3+2+2+2 = 9 units of gate delay to get c
1
6 (notice a ripple
adder would have required 2(16)+1 = 33 units of delay.
37
Carry Lookahead Logic
38
4 Bit Adder Subtractor
Desirable to use same hardware for both operations
2s complement addition for subtraction
Overflow
Addition/subtraction of 2 n bit numbers may produce n+1 bit
output
Problem if fixed # of bits (n) are allocated for input and output
Must detect its occurrence
d=101-010
d=101+2scom(010)
d=101+1scomp(010)+1
d=101+101+1
d=1011
d=3
M=0, add
M=1, Subtract
M=1, XOR=Complement
M=0, XOR=Pass through
ignore
39
BCD Adder
Binary Sum BCD Sum #
k Z8 Z3 Z2 Z1 C S8 S4 S2 S1
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 2
0 0 0 1 1 0 0 0 1 1 3
0 0 1 0 0 0 0 1 0 0 4
0 0 1 0 1 0 0 1 0 1 5
0 0 1 1 0 0 0 1 1 0 6
0 0 1 1 1 0 0 1 1 1 7
0 1 0 0 0 0 1 0 0 0 8
0 1 0 0 1 0 1 0 0 1 9
0 1 0 1 0 1 0 0 0 0 10
0 1 0 1 1 1 0 0 0 1 11
0 1 1 0 0 1 0 0 1 0 12
0 1 1 0 1 1 0 0 1 1 13
0 1 1 1 0 1 0 1 0 0 14
0 1 1 1 1 1 0 1 0 1 15
40
Binary Sum BCD Sum #
k Z8 Z3 Z2 Z1 C S8 S4 S2 S1
1 0 0 0 0 1 0 1 1 0 16
1 0 0 0 1 1 0 1 1 1 17
1 0 0 1 0 1 1 0 0 0 18
1 0 0 1 1 1 1 0 0 1 19
41
Magnitude Comparator
Classical approach
3 outputs and 2n inputs
Large logic complexity, if n >3
Alternative Approach
2-step process
F
1
(A = B)
F
2
(A > B)
F
3
(A < B)
magnitude
comparator
4
4
A
B

42
Magnitude Comparator
2-step process
1. Define
x
i
( A
i
B
i
) = A
i
B
i
+ A
i
B
i
, 0 < i < 3
2. F
1
= ( A = B) = x
3
x
2
x
1
x
0
F
2
= ( A > B) = ( A
3
> B
3
)
+ (A
3
= B
3
) - (A
2
> B
2
)
+ (A
3
= B
3
) - (A
2
= B
2
) - (A
1
> B
1
)
+ (A
3
= B
3
) - (A
2
= B
2
) - (A
1
= B
1
) - (A
0
> B
0
)
= A
3
B
3
+ x
3
A
2
B
2
+ x
3
x
2
A
1
B
1
+ x
3
x
2
x
1
A
0
B
0
F
3
= A
3
B
3
+ x
3
A
2
B
2
+ x
3
x
2
A
1
B
1
+ x
3
x
2
x
1
A
0
B
0
= ( F
1
+ F
2
)
43
Magnitude Comparator
44
Decoders
Code of n bits can represent 2
n
decode outputs
One output is true at a time
x
y
x y x
x
y x
y
y
y
x
xy

x y D
0
D
1
D
2
D
3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
= D
0
= D
1
= D
2
= D
3
45
Decoders with Enable
If E = 0 all outputs are disabled
Outputs are active low
E x y Y
0
Y
1
Y
2
Y
3
1 X X 1 1 1 1
0 0 0 0 1 1 1
0 1 0 1 0 1 1
1 0 1 1 1 0 1
1 1 1 1 1 1 0
Y
0
Y
1
Y
2
Y
3
E

x
y

Y
0
Y
1
E
y
x
Y
2
Y
3
2
1
2 x 4
2
0
decoder
(enable)
46
Larger Decoders
Larger decoders are built with smaller ones
Special decoders (other than n to 2
n
)
BCD to 7 segment display
47
Function implementation using Decoders
Adder S = (1,2,4,7); C = (3,5,6,7)
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 48
Decoder based realization
Implement the following function using 3 to 8 and 2 to 4 decoders
F= (0,3,5,7)
X
Y
z
m(0)
m(1)
m(4)
m(3)
m(6)
m(5)
m(2)
m(7)
E&CE 223 Digital Circuits and Systems (A. Kennings) Page 49
Decoder based realization
Implement the following function using 3 to 8 and 2 to 4 decoders
F= (0,3,5,7)
X
Y
m(0)
m(1)
m(3)
m(2)
000
011
101
111
Z
0
m(0)
m(1)
m(3)
m(2)
50
Encoders
Does reverse operation to decoder
Constraint only one input is active at a time
Example, Octal to Binary Encoder
Z = D1 +D3 +D5 +D7; y = D2 +D3 +D6 +D7; x = D4 +D5 +D6 +D7
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 x y z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
51
Priority Encoders
Encoder with priority function
Multiple inputs may be true simultaneously
Higher priority input gets the precedence
Inputs Outputs
D
0
D
1
D
2
D
3
x y V
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1
Valid bit, V, indicates one or more inputs are true
at the same time
Higher priority input gets the precedence
52
Priority Encoders - Circuit
x = D
2
+D
3
y = D
3
+D
1
D
2

V = D
0
+D
1
+D
2
+D
3
53
Multiplexers
A Multiplexer has n inputs, one output, and S
(2
s
= n) select (control) inputs
Passes (selects) an input depending on S
54
Function Implementation with Multiplexers
Let F(x,y,z) = (1,2,6,7)
55
Function Implementation with Multiplexers
Let F(w,x,y,z) = (1,2,6,7,10,13)
wxyz
0)0000
1)0001
2)0010
3)0011
4)0100
5)0101
6)0110
7)0111
8)1000
9)1001
10)1010
11)1011
12)1100
13)1101
14)1110
15)1111
0
1
2
3
yz
wx+wx
wx+wx+wx
wx
56
Multiplexers with Tri-stated Gates
57
Book Sections Combination Circuits
Material is covered in Sections 4.1 4.5, 4.7 4.10