IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO.

4, JULY 2008

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A Minimally Switched Control Algorithm for Three-Phase Four-Leg VSI Topology to Compensate Unbalanced and Nonlinear Load
Piyush Lohia, Mahesh Kumar Mishra, Member, IEEE, Kottaisamy Karthikeyan, and Krishna Vasudevan, Member, IEEE

AbstractIn this paper, a minimally switched control algorithm for a three-phase four-leg voltage source inverter topology is proposed for compensation of unbalanced and nonlinear loads. An optimized control technique is necessary for the three-phase four-leg topology, otherwise it requires higher switching operations of the switches in the voltage source inverter for tracking three-phase and neutral currents through conventional hysteresis band control. In the paper, a control technique has been formulated and its effect of reducing the switching frequency over a period of time has been studied and veried. A simulation study of three-phase, four-wire compensated system is carried out using Matlab/Simulink to validate the proposed method. Detailed experimental results presented further conrm the efcacy of the proposed control. Index TermsActive power lter (APF), hysteresis band, interface inductance, switching frequency, voltage source inverter (VSI).
Fig. 1. Three-phase, four-leg VSI topology.

I. INTRODUCTION

N the last few decades, the revolution of power electronics has resulted in increased usage of consumer electronics and power electronic based products in industries. Owing to the wide use of such products, power pollution has been a serious problem in the power distribution system, which has henceforth, put a challenge on clean power supply. Active power lters (APFs) have been developed to solve these problems [1][3]. One of the main constituents of APF (compensator) is the voltage source inverter (VSI). Various kinds of VSI topologies are given in literature [3][14]. These are classied based on the number of phases, types of power converters and modes of operations, etc. In general, these VSIs consist of power switches with anti-parallel diodes, dc storage capacitors, interface inductors and isolation transformers, in case they are used. From comparative study in terms of number of power switches and components of these topologies, it is found that the three-phase four leg VSI topology is best suited for unbalanced and nonlinear load compensation in three-phase four-wire systems [6][10]. This topology is illustrated in Fig. 1. The supply voltages

Manuscript received October 14, 2007; revised February 7, 2008. Published July 7, 2008 (projected). Recommended for publication by Associate Editor B. Wu. P. Lohia is with the Price Water House Cooper, Gurgaon, India (e-mail: piyush.iitm@gmail.com). M. K. Mishra, K. Karthikeyan, and K. Vasudevan are with the Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai 600 036, India (e-mail: karthikeyan@ee.iitm.ac.in; krishna@ee.iitm.ac.in; mahesh@ ee.iitm.ac.in). Digital Object Identier 10.1109/TPEL.2008.925414

are assumed to be balanced and sinusoidal. The load is comprised of unbalanced and non linear loads which draw and from the supply. The load and the load currents , compensator are connected at the point of common coupling , (PCC). The compensator has one dc storage capacitor . Each eight IGBT switches and four interfacing inductors switch has an anti-parallel diode across it as shown in the gure. Three of its legs are connected to three phases at the PCC through interface inductors. The fourth leg is connected to the load neuand supply neutral through an interface inductor tral . When the compensator is working, zero sequence current containing switching frequency components is routed through . This topology is advantageous in terms of the path number of components used and capacity to fully compensate the fundamental reactive component, nonlinearity and unbalance in the load. Unlike the H-bridge VSI topology [11], it does not require any isolation transformer to prevent short circuit of dc storage capacitor. Since there is only one dc capacitor, there is no problem of dc voltage unbalance as in the case of neutral clamped VSI topologies [12][15]. Thus, it combines the advantage of H-bridge and neutral clamped VSI topologies. However, a proper control for this VSI structure has to be worked out. The only problem with this topology is that it requires higher switching operations of the power devices in the VSI to track reference currents, in case three phases and neutral currents are tracked using the conventional hysteresis control. Hence, an attempt has been made to nd a minimal switching technique for this topology for three-phase four-wire system.

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Simulation and experimental studies are carried out and the effect of the proposed method on reducing the average switching frequency has been veried. The proposed algorithm results in a variable switching frequency with time. However, it can be modied to obtain a constant switching frequency as given in [16][18]. II. MINIMAL SWITCHING CONTROL ALGORITHM The concept of minimal switching control algorithm is to minimize changes in gate signals of the switches, which are controlled by hysteresis current control. For the proper operation of the APF, the idea of phase voltage segmentation to compensate load under unbalanced source is discussed in [19]. The hysteresis current control method with minimal switching using phase voltage segmentation for three-phase three-wire system has been presented in [20], [21]. The principle proposed is extended and applied to three-phase four-leg VSI topology in four wire systems in this work. The reference compensator currents can be derived based on any of the control algorithm available in literature [22][25]. The most popular and widely used algorithm is based on instantaneous reactive power theory [22], [23]. However due to simplicity in formulation, the reference compensator currents ( , , ) for the three phases are derived using instantaneous symmetrical component theory [11], [24], [25], which are given as follows: for (1)
Fig. 2. Equivalent circuit: (a) cable, (b) motor coil at 50 Hz, (c) motor coil more than 5 kHz, and (d) bearing.

After compensation, there should not be any current in source . It implies neutral, which means (7) Thus, the reference current for the fourth leg is the negative sum of lter currents or load currents. From the above, it is also evident that the reference lter currents for the three phases and the neutral are not independent and it is therefore not necessary to track all the four currents. Instead, it is sufcient to track only three currents at a time and leave one leg of the inverter uncontrolled by keeping one of the switches on or off. However, the selection of the three controlled currents out of the four reference currents is not trivial and is formulated in the following manner. It is important to note that the hysteresis current controller is used to maintain actual current within a band of current around the reference. It does so by attempting to choose a switch state which brings the voltage across the interfacing inductors to a polarity, which will constraint the current within pre-dened hysteresis band [14]. If one leg of the inverter is uncontrolled and the other three legs are controlled through hysteresis, it is impor, tant to see whether the four interfacing inductor voltages, , and , can be made positive or negative using the remaining switching combinations. This is because, in hysteresis , , current control scheme, the compensator currents, and are kept in a band by increasing and decreasing the current or switching the inductor voltages from positive to negative consecutively. Consider a case when top switch in phase- , is on and bottom switches in phases , and , , , (see Fig. 1) are on ( , and are 0). In the following analysis, the resistances of interfacing inductors are considered to be is replaced by negligible and the dc capacitor with voltage dc supply of volts. Then, the equivalent circuit for this switch state is shown in Fig. 2. , , and The voltages across the interface inductors in phases , , and neutral respectively as shown in Fig. 2, can be obtained from the three independent loop equations as given (8a) (8b) (8c)

is the average or mean value of the load power and where refers to the losses in the VSI. The term is generated by a proportional integral (PI) controller to maintain dc capacto the reference value . This is given itor voltage as follows: (2) where and are the gains of the PI controller. The is updated at every zero crossing of the phase- voltage. The reference current for the fourth leg of the inverter is computed as following. From Fig. 1 (3) Also at the PCC (4) Now, if we assume the ideal compensator, the actual lter and actual source currents are replaced by their currents and respectively. Therefore, we get references (5) By summing the three phase currents, the following is obtained: (6)

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TABLE I VOLTAGES ACROSS INDUCTORS FOR VARIOUS SWITCHING COMBINATIONS

Fig. 3. Voltages (a) v , (b) v , (c) v , and (d) v during (0 60 ) system . voltage segment for specied switching combination keeping node b

=0

TABLE II CONTROLLED AND UNCONTROLLED SWITCHES FOR DIFFERENT SEGMENTS OF SYSTEM VOLTAGE

The above equations can be re-written as

(9)

By taking pseudo-inverse (which is valid here as , since and ), we have

(10)

Individually, these voltages may be expressed as

(11) In a similar manner, voltages across the interfacing inductors can be calculated for all the switching combinations. These are given in Table I. Now it is required to nd out whether it is possible to have one leg uncontrolled and if so, what is the potential at the mid point. It is necessary to nd out the duration for which such a potential can be maintained. Consequently the other legs can be controlled. In the following analysis, a balanced supply voltage of 381 V rms (LL) and dc link voltage of 850 V is considered. From the Table I, it is clear that the neutral leg cannot be left uncontrolled because when , is always negative and

, is always positive. Thus, we have to choose when an uncontrolled phase from the other three legs. For this we proceed as follows. We divide one cycle in six phase segments (intervals). For the interval 0-60 of the system voltage, it can is negative and its absolute be seen that the phase voltage value is the highest. Let us therefore investigate the possibility on and off and control the of keeping other phases. This would be possible if the four interfacing inductors have opposite polarities of voltage available across with the other available switch states. The voltages across inductors for various inverter states are shown in Fig. 3(a)(d). From these gures, it can be inferred that even if we x node at 0 in the entire (060 ) segment, switching states are available for each inductor voltage to attain alternate signs. For example, is positive in state and negative in state throughout the (060 ) interval. The switch states can be found , and . Hence in this for the other inductor voltages mode, the hysteresis controller has options to choose suitable switching states to track the four currents successfully. In a similar manner, it is important to show that for other cases (keeping at 1 or xing or at 0 or 1), switch states do not exist to make inductor voltages to attain alternate signs. Applying this logic to the , it other segments (60 120 ), (120 180 ) is possible to show that the uncontrolled phases may be chosen according to the scheme given in Table II. With these selections, Figs. 48 show that the states exist for the inductor voltages to

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Fig. 4. Voltages (a) v , (b) v , (c) v , and (d) v during (60 120 ) system voltage segment for specied switching combination keeping node a .

=1

Fig. 6. Voltages (a) v , (b) v , (c) v , and (d) v during (180 240 ) system voltage segment for specied switching combination keeping node b .

=1

Fig. 5. Voltages (a) v , (b) v , (c)v , and (d) v during (120 180 ) system voltage region for specied switching combination keeping node c .

=0

Fig. 7. Voltages (a) v , (b) v , (c) v , and (d) v during (240 300 ) systemvoltage segment for specied switching combination keeping node a .

=0

be made positive or negative. It can be observed that the phases having similar system voltage polarity in each 60 sector have been selected as controlled phase. The second stage in minimizing the switching operations is achieved by monitoring the current polarity. If the current is positive, then it is not necessary to control the bottom switch. It is sufcient to keep it off and let the anti-parallel diode of this switch conduct. Similarly if the phase current is negative, it is unnecessary to operate the top switch of the corresponding leg. For example, if a particular controlled phase current is positive and it is required to change the slope of current from positive to negative (to decrease the current), it is not necessary to

change the bottom switch from off to on as it cannot conduct current in negative direction. It is best to keep it off and let the freewheeling diode to conduct. In the uncontrolled phase also, switches may be kept on/off throughout each sector depending on the corresponding phase current polarity [19], [20]. III. SWITCHING LOGIC EXPRESSIONS The proposed control algorithm is a modied form of hysteresis control scheme in which the switching is governed by the system voltage sector and the reference current polarity. The system voltage sector decides the phases to be controlled by hysteresis and reference current polarity decides the switch in the

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Fig. 9. Block diagram of the proposed control strategy.

TABLE III SIMULATION PARAMETERS Fig. 8. Voltages (a) v , (b) v , (c) v , and (d) v during (300 360 ) system voltage segment for specied switching combination keeping node c .

=1

corresponding phase to be controlled. In this section, a unication of the above two propositions is presented in the form of Boolean expressions so that a single digital circuit can achieve the different modes of operation. As mentioned above, the different system voltage sectors considered for the purpose are (060 ), (60 120 ), (120 180 ), (180 240 ), (240 300 ) and (300 360 ). Let , , , , and be the Boolean variables denoting the above six segments. These variables are logic high in their sectors respectively and low if they fall outside their sectors. Let , , and be the phase- , , and variables which are high when the reference current for the corresponding phase is positive and low otherwise. The complimentary signals of , , and are denoted by , , and respectively. For example, is high in the system voltage region (060 ) and low is high when the reference outside this sector. The variable current for phase- is positive and low otherwise. Similarly, let , , and be correspond to the output switching signals of phases , , and , respectively, from the hysteresis controller. These can be described as and be the actual compensator and referfollowing. If ence current for phase respectively and be the value of hysis 1 (on) when and is 0 (off) teresis band, then . The signal will be complimentary to when . Whether these signal of hysteresis controller are used to trigger the device or not is governed by the sector identication ) and current polarity identication signals ( for , , , ) in the manner described in Secsignals ( for is to be controlled by hysteresis opertion II. For example, ation outside of (60 120 ) and (240 300 ) sectors and when . Thus, the actual switching phase- current is positive may be written as follows: signal to the device (12a)

Similarly, we can express the logic signals , and for the switches , , and , respectively, are given by

, ,

, ,

, ,

(12b) (13) (14) (15) From above equations, it can be noted that the mid point of the neutral leg is not xed in any of the system voltage segments and is controlled through hysteresis depending on current polarity only. IV. SIMULATION STUDY The described three-phase four-leg topology (refer Fig. 1) has been simulated using MATLAB/SIMULINK. Two switching control algorithms are considered; one with conventional hysteresis control of all three phase currents as well as neutral current and second with the proposed switching control. The block diagram illustrating the proposed control strategy is shown in Fig. 9. The simulation parameters of the system under consideration are given in Table III.

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Fig. 11. Logic signals (a) x (d) x , p . 

, s , p , (b) x

s , p , (c) x , p , and 

Fig. 10. (a) Source voltages. (b) Three-phase load currents. (c) Actual compensator currents. (d) Compensated source currents and neutral current. (e) Harmonic spectrum for load currents. (f) Harmonic spectrum for source currents.

The three-phase supply voltages and load currents are shown Fig. 10(a) and (b), respectively. The three-phase load currents are unbalanced and nonsinusoidal for the load given in Table III. For the load currents, the degree of unbalance is 30%. Three phase reference compensator currents are generated using (1). The reference current for the neutral phase is the negative sum of the three-phase load or reference currents as given in (7). The actual compensator currents are compared with their respective reference with the pre-dened hysteresis band using the proposed switching logic. The compensator output currents for phases- , , and are shown in Fig. 10(c). As seen from the gure, these waveforms have a small hysteresis band. Actual neutral current in this gure is scaled down by half for the sake of clarity. It is sinusoidal in nature as balanced distorted currents drawn by three-phase full bridge rectier do not affect the neutral current. Fig. 10(d) shows compensated three-phase source currents and neutral wire current ( ). The source currents are sinusoidal, balanced and in phase with supply voltages. The neutral wire current after compensation is zero. The harmonic spectrums for load and source currents are shown in Fig. 10(e) and (f), respectively. The total harmonic distortions (THDs) are 7.03%, 8.62% and 13.0% for load currents and 1.98%, 1.75% and , respecand 1.83% for source currents in phases tively. This ensures signicant improvement in the quality of the compensated source currents. and , Fig. 11(a) and (b) show the logic gate signals, and , respectively under the progiven to the switches, (shown posed control scheme. It can be observed that when

in Fig. 10(c) with same time frame) is positive, is operis negative, is operated. Further, during ated and when (120 180 ) and (240 300 ), system voltage segments the switches are not controlled. Since segment and polarity signals are logically ANDed, this has effect of reducing switching operations as shown by large gap between pulses in Fig. 11(a) and , for switches, and and (b). The gate signals, , are shown in Fig. 11(c) and (d) respectively. Here, similar is positive, is controlled and when to phase- when is negative, is controlled. There is no reduction in switching operations for the neutral leg through voltage phase segmentation as explained above. In order to compare the performance with that of conventional hysteresis control, the switching signals given to the gates of the switches in the VSI for the two cases have been further analyzed. The switching signals given to the gates were stored in the form of arrays. Then, changes in the status of gate signal, i.e., 1 to 0 or 0 to 1 were computed for both the cases. This would give an indication of how fast the gate signals have changed or how fast the switches have been operated in the two cases. Also, the instantaneous switching frequency can be averaged over one cycle of 50 Hz to obtain average switching frequency. Further, the instantaneous switching frequency has been calculated as the reciprocal of the time difference between two alternate similar changes in the gate signal. Switching frequency versus time plots for two cases are shown in Fig. 12(a)(d). From Fig. 12, it can be observed that for the proposed algorithm, the switching frequency for phase- reduces in the two (60 120 ) and (240 300 ) sectors. This is because phaseis xed by voltage segmentation. The current polarity brings further reduction of switching operations in both and phases. For the other legs and , switching frequency plots are similar to that of leg . The comparative study of switching frequency is given in Table IV. From the table, it is seen that the method reduces switching operations and average switching frequency to half to that of the conventional hysteresis control. It is also noted that the switching operations for the devices in the neutral phase are approximately double to that of the other

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TABLE V EXPERIMENTAL SET-UP PARAMETERS

Fig. 12. Variation of switching frequency with time for (a) Leg a for simple hysteresis control, (b) Leg a for the proposed switching control, (c) Leg nfor simple hysteresis control, and (d) Leg n for the proposed control. TABLE IV COMPARATIVE STUDY OF SWITCHING FREQUENCY IN THE TWO SIMULATED CONTROL ALGORITHMS

Due to sudden removal of load, there is an increase in the dc link voltage. The PI controller restores the dc link voltage to the , the reference value within approximately 10 cycles. At unbalanced load is switched on again. As a result, the average load power is changed to its previous value (8.4 kW). Due to sudden increase of the load, the dc link voltage falls below the reference value. However, the PI controller brings the dc link voltage to the reference value in about 10 cycles. Thus, the dc link controller provides proper regulation for the dc capacitor voltage. This ensures satisfactory performance of the compensator under load transients. V. EXPERIMENTAL RESULTS In order to observe the performance of the proposed control algorithm in actual conditions and to compare its performance with the conventional hysteresis control, an experimental set-up was built. The power circuit set-up is the same as shown in Fig. 1. The voltage and current quantities are converted to range using Hall Effect voltage and current transducers. With the help signal conditioning circuits, these low level signals are further converted to 0-3 V range which is compatible with the analog to digital channels of the digital signal processor (DSP) TMS320F2812. The DSP acquires samples of these signals and processes them in order to generate reference currents using instantaneous symmetrical component theory as given in , current polarity sig(1). Based on voltage sectors and hysteresis band signals , the nals Boolean logic expressions (12)(15) are executed to generate switching signals to the gates of the power switches through an opto-isolation driver circuit. The dc link voltage was maintained to a constant reference value by a PI controller which is implemented in DSP itself. The experimental system parameters are given in Table V. The three-phase source voltages are shown in Fig. 14(a). It can be observed that the source voltages available in the laboratory are slightly unbalanced and nonsinusoidal. This affects the compensation performance and hence the compensated source currents are also slightly unbalanced and nonsinusoidal. The load currents in three phases and neutral current shown in Fig. 14(b), are unbalanced and contain harmonics because of and rectier load (given in Table V). the unbalanced After compensation, the source currents in three phases and the current in the neutral wire are shown in Fig. 14(c). The compensated source currents are sinusoidal and in phase with

Fig. 13. DC link capacitor voltage during the load transients.

phases. This means that devices used in neutral phase requires high average switching frequency. The voltage regulation characteristic of dc link capacitor is load is switched off, shown in Fig. 13. The unbalanced leaving nonlinear rectier load only at . This is indicated by sudden change in average load power from 8.4 kW to 3.1 kW.

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Fig. 15. (a) Switching signals (x ; x ) under proposed control method, segment variables (s ; s ), actual compensator current for phase-a (i ). (b) Switching signals (x ; x ) under proposed control method, actual compensator current for phase-n (i ).

Fig. 14. (a) Three-phase source voltages. (b) Load currents in three phases and neutral current. (c) Compensated source currents in three phases and neutral wire. (d) Harmonic spectrum of load currents. (e) Harmonic spectrum of source currents.

their respective source voltages. The source neutral current is approximately zero. The harmonic spectrums of the load and source currents are shown in Fig. 14(d) and (e) respectively. The load current THDs are 7.8%, 10.9% and 17.8% while the source current THDs are 4.8%, 3.6% and 4.2% in phases and , respectively showing signicant reduction of harmonics in source currents. Hence, the experimental results closely follow the results those obtained from the simulation study.

Under the proposed control method, the switching signals are generated using (12)(15). For phase- and neutral, these switching signals are shown in Fig. 15(a) and (b). It can be obis served from Fig. 15(a) that the gate signal to the switch xed at 1 (high) during the phase segment (60 120 ), represented by variable and is controlled through hysteresis, only is positive. Similarly, the gate signal for switch when is xed at 1 (high) during the phase segment (240 300 ), represented by , and is controlled through hysteresis, only when is negative. For phases and , the gate signals are generated similar to the phase- . However for phase- , the gate signals are different and are shown in Fig. 15(b) along with the . Here, there is no voltage phase actual compensator current segmentation and minimization is achieved only by monitoring is positive, switch is the current polarity. Hence, when controlled and when is negative, switch is controlled through hysteresis band current control. obtained with the The gate signals for phases- and conventional hysteresis control technique, are shown in Fig. 16(a) and (b) respectively. It is observed that the switches are always operated through hysteresis current control irrespective of voltage phase segments or reference current polarity, unlike the gate signals for the proposed control. For phase- , there are some time intervals when the actual compensator currents follow the reference currents within the band without actually switching. Even then, the number of changes in the

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and the average switching frequency when compared to the conventional hysteresis current control method. VI. CONCLUSION In this paper, a minimally switched control algorithm has been proposed for three-phase four-leg VSI topology to compensate unbalanced and nonlinear loads. The conventional hysteresis and the proposed control schemes are compared and it is found that there is signicance reduction in switching operations of the power switches in the VSI over a given time period. In addition to the reduction in switching signals, the proposed control algorithm successfully compensates unbalanced and nonlinear load. Detailed simulation and experimental study presented, conrm the effectiveness of the algorithm. REFERENCES
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Fig. 16. (a) Switching signals (x ; x ) under simple hysteresis control and actual compensator current for phase-a. (b) Switching signals (x ; x ) under simple hysteresis control and actual compensator current for phase-n (i ). TABLE VI COMPARATIVE STUDY OF SWITCHING FREQUENCY WITH PROPOSED AND CONVENTIONAL SCHEMES: EXPERIMENTAL

gate signal obtained for simple tracking is found to be more than that obtained for the proposed control method. To observe the reduction in switching frequency using the proposed control method, the number of changes in the gate signals are counted for both the control algorithms and are given in Table VI. It can be observed that for experimental results, the numbers obtained are less than those in the simulation study. This is because the percentage of hysteresis band in hardware set-up is larger than the simulation study. However, the percentage of reduction in switching frequency using the proposed control method, compared to the conventional hysteresis control, is found to be similar with the simulation study. From the above discussion, it is clear that the proposed control scheme satisfactorily compensates the unbalanced and nonlinear load in three phase four wire system and reduces switching operations

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 4, JULY 2008

[18] C.-T. Pan, Y. S. Huang, and C. Y. Li, An error bounded current controller with constant sampling frequency, IEEE Trans. Power Electron., vol. 19, no. 3, pp. 739747, May 2004. [19] T. Jin and K. M. Smedley, Operation of one-cycle controlled threephase active power lter with unbalanced source and load, IEEE Trans. Power Electron., vol. 21, no. 5, pp. 14031412, Sep. 2006. [20] M. N. Kumar and K. Vasudevan, A novel hysteresis switching strategy for harmonic compensation, Int. J. Energy Technol. Policy (IJETP), vol. 4, no. 3/4, pp. 379393, 2006. [21] M. N. Kumar and K. Vasudevan, Bi-directional real and reactive power control using constant frequency hysteresis with reduced losses, Elect. Power Syst. Res., vol. 76, pp. 127135, Sep. 2005. [22] H. Akagi, Y. Kanazawa, and A. Nabae, Instantaneous reactive power compensators comprising switching devices without energy storage components, IEEE Trans. Ind. Applicat., vol. 20, no. 3, pp. 625630, May/Jun. 1984. [23] H. Kim, F. Blaabjerg, B. Bak-Jensen, and J. Choi, Instantaneous power compensation in three-phase systems by using p-q-r theory, IEEE Trans. Power Electron., vol. 17, no. 5, pp. 701710, Sep. 2002. [24] V. Soares, P. Verdelho, and G. D. Marques, An instantaneous active and reactive current component method for active lters, IEEE Trans. Power Electron., vol. 15, no. 4, pp. 660669, Jul. 2000. [25] K. Karthikeyan and M. K. Mishra, A novel load compensation algorithm under unbalanced and distorted supply voltages, Int. J. Emerging Elect. Power Syst. vol. 8, no. 5(1), pp. 116, Oct. 2007.

Mahesh K. Mishra (S00M02) received the B.Tech. degree from the College of Technology, Pantnagar, India in 1991, the M.E. degree from the University of Roorkee, Roorkee, India, in 1993, and the Ph.D. degree in electrical engineering from the Indian Institute of Technology, Kanpur, India, in 2002. He has 16 years of teaching and research experience. For about 10 year, he was a member of the faculty in the Electrical Engineering Department, Visvesvaraya National Institute of Technology, Nagpur, India. Currently, he is an Assistant Professor with the Electrical Engineering Department, Indian Institute of Technology Madras. His interests are in the areas of power distribution systems, power electronics, and control systems. Dr. Mahesh is Life Member of the Indian Society of Technical Education (ISTE).

Kottaisamy Karthikeyan received the B.Eng. degree in electrical and electronics engineering from Syed Ammal Engineering College Ramanathapuram, Madurai Kamaraj University, India, in 2002, the M.Eng. degree in power systems from the College of Engineering Guindy, Anna University, India, in 2004, and is currently pursuing the Ph.D. degree in the Power Systems Hardware Laboratory, Department of Electrical Engineering, Indian Institute of Technology Madras, India. His elds of interest include power quality and power electronics control in power system.

Piyush Lohia received the B.Tech. degree in electrical engineering and the M.Tech. degree in power systems and power electronics from the Indian Institute of Technology-Madras (IIT Madras) in 2007. Currently, he is a Consultant with Price Water House Coopers, Gurgaon, India, where he is involved in performance improvement of power utilities in India.

Krishna Vasudevan (M03) received the B.Tech. degree from the Indian Institute of Technology Madras (IIT Madras), Madras, India, in 1989, the M.E. degree from the Indian Institute of Science, Bangalore, in 1991, and the Ph.D. degree from the Indian Institute of Technology Madras, in 1996, all in electrical engineering. From 1991 to 1992, he was with the M/s Kirloskar Electric Company, Ltd. as a Senior Engineer in the R&D Section and was involved in the design and development of UPS systems. After working for about two and a half years with M/s Lucas TVS, Ltd. as a Senior Engineer involved in performance improvement of automotive alternators, he joined the Department of Electrical Engineering, IIT Madras, where he is currently Associate Professor. His research interests are in power electronics and drives.