1

IEEE TOPOLOGY REVIEW OF

DC/DC CONVERTERS
Louis Diana - MGTS
2
IEEE TOPOLOGY REVIEW
Buck converter theory of operation
Discontinuous vs. Continuous mode of operation
Voltage mode feedback and Current mode feedback
Design considerations
Boost converter theory of operation
Design considerations
Flyback converter theory of operation
Design considerations
SEPIC Converter theory of operation
Design considerations
3
Synchronous Buck
SR
PWM
VCC
COMP
GND
Z
Z
Z
Output
Synchronous
Rectifier
SW Node
Switch
Control Circuit
DC Input
Averaging Circuit
+
4
Synchronous Buck Waveforms
Continuous Conduction Mode
Verror amp
CLK RAMP
FET SOURCE
PWM
FET CURRENT
RECT. CURRENT
I OUT
Inductor current
5
Synchronous Buck Waveforms
Continuous Conduction Mode
Verror amp
CLK RAMP
FET SOURCE
As the load current goes down the converter becomes less continuous but D
is still equal to Vout /Vin
I OUT
IND CURRENT
I
I OUT
0A
Verror amp
CLK RAMP
FET SOURCE
I OUT
IND CURRENT
I
0A
FET CURRENT
RECT. CURRENT
FET CURRENT
RECT. CURRENT
6
Synchronous Buck Waveforms
Discontinuous Conduction Mode
Verror amp
CLK RAMP
FET SOURCE
I OUT
IND CURRENT
I
I OUT
0A
The load current has gone down the the point where the converter becomes
discontinuous D no longer equals Vout /Vin
FET CURRENT
RECT. CURRENT
7
Basic Relationships
out in
2
in
out O
out in
out
in
out on
V V V
V
Ts
I 2L
D
L
Ts D ) V (V
I
V
V
Ts
t
D

=

=
= =
Continuous Conduction Mode (CCM)
Discontinuous Conduction Mode (DCM)
8
Inductor Considerations
Benefits of low L values
Lower DCR
Higher Isat
Higher di/dt
Transient response improves
Less output capacitance required for given transient
performance
Benefits of high L values
Lower ripple current
Lower AC losses (skin effect, hysteresis)
Lower RMS current in FETs
Lower RMS capacitor current (mainly output)
Continuous inductor current over broader load range
Less C required for equivalent output ripple
B
Vrms 10
8

4.44 Ae N f
:=
9
General Inductor Guidelines
Size for I
L
to be 10% to 30% of full load current
Winding losses usually dominate
12
IL
I IL where RL IL PL
2
pp 2
out
2
RMS
2
RMS AVG

+ = =
10
Inductor and FETs
I
RIPPLE
/I
LOAD
(%)
0 10 20 30 40 50 60 70 80 90 100
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
N
o
r
m
a
l
i
z
e
d

S
w
i
t
c
h

a
n
d

S
R

P
o
w
e
r

L
o
s
s

(
W
)
Increasing ripple increases losses
Similar effect for capacitor ESR loss
11
MOSFETs
Both main switch and synchronous rectifier should be
N-type for best efficiency
Many interrelated issues
Output capacitance vs. switching loss
Gate capacitance vs. switching speed
Gate capacitance vs. driver power loss
Primary Tradeoffs
Package
Power loss
Cost
12
Switch FET
Losses vs. Frequency
0.00
0.05
0.15
0.20
0.25
0.35
100 k
0.10
0.30
10 M
S
w
i
t
c
h

L
o
s
s
e
s

(
W
)
f
SW
- Switching Frequency - Hz
Conduction
Gate
Switching
Output
Losses
Data for Si4866DY switch, Si4836DY rectifier, 2A ripple
current and 10A load
13
Rectifier FET
Losses vs. Frequency
0.00
0.05
0.15
0.20
0.25
0.35
100 k
0.10
0.30
10 M
S
w
i
t
c
h

L
o
s
s
e
s

(
W
)
f
SW
- Switching Frequency - Hz
Channel Conduction
Gate
Diode Conduction
Losses
Note rise in diode conduction loss as Fs rises.
Data assumes 20-ns of diode conduction time per SW edge
14
FET Selection
Compare different FETs in both positions
In general higher F and higher input voltage mean
Higher switching losses therefore use lower Qg switch
FET to cut switching losses
For rectifier FET, low R
DS(on)
is most important, but dont
ignore gate power
15
SW Node Ringing
Can affect converter operation
Worst on rising edge of SW
(highest di/dt transition)
Caused by parasitic L and C
L in the FET from the SW node to
Vin or GND
C from SW node to GND
High layout dependence
Bottom Gate (1 V/div)
SW (1 V/div)
dV/dt Bump
t - Time - 50 ns/div
16
SW Node Ringing Remedies
Improve layout
Minimize loop areas
Minimize trace inductance
Keep SW node area low (secondary effect, conflicts
with cooling rectifier FET)
Slow down SW node edge transitions
Series gate resistor in switch FET gate lead
Add a snubber
17
Power Capacitors
Selection Considerations
Power Dissipation
ESR
Ripple Performance
ESR
Transient Performance
ESR
Capacitance
ESL
Cost
Size
Reliability
18
Relative Capacitors Characteristics
Standard Al Electrolytic
High ESR
Low cost
Low current capability
Not really suited to DC/DC converters
OSCON
Low ESR
Medium cost
High current capability
19
Relative Capacitors Characteristics
Solid Polymer
Low ESR
Very high cost
Medium current capability
POSCAP
Low ESR
High cost
Medium current capability
20
Relative Capacitors Characteristics
Tantalum
Medium ESR
Medium cost
Medium low current capability
Ceramic
Very low ESR
Very high cost
High current capability in bulk
21
Capacitor Impedance
0.1 10000 1 10 100 1000
0.001
0.01
0.1
1
10
R
C
A
P

-

I
m
p
e
d
a
n
c
e

-

f - Frequency - kHz
470 F Tantalum
1000 F OSCON
180 F Solid Polymer
10 F Ceramic
22
Choosing Capacitor Size
Input Filter
Sized for AC current handling
Output Filter
Transient events on load
Output voltage ripple
23
Input Capacitor Current
+
Cin
Ic
(sw OFF)
Ic
(sw ON)
SW1
SW2
Lout
Cout
Iin
Iload
Isw = Ic + Iin
I
SWpp
Io
Io
( ) D 1 I D
12
I
) I (I I
ESR I P
2
avg in
2
pp
SW
2
avg in
pk
SW
RMS
cap
cap
2
RMS
cap cap
+
(
(

+ =
=
24
Input Ripple Voltage
Cin current
Switch current
ESR Voltage
C
ESL Voltage
Cin Ripple Voltage
Usually a secondary consideration
Contribution from ESR, ESL and capacitance value
25
Output Capacitor Criteria
Selection Considerations
Transient performance
Bulk capacitance
ESR
ESL
Output Ripple
ESR
Bulk value
ESL has minor effect
26
Transient Performance
Output
Currents
Vout
AC
Coupled
Iload
0 A
ESL
ESR
Cout &
ESR
Cout &
ESR
ESL
ESR
Iinductor
27
Output Capacitor
Selection Considerations
2A to 10A load step @ 15A/s
Use 470F SP: 15m, 3nH
To help reduce spikes, add two 10F ceramics
Yields
24.5mV undershoot
39mV overshoot
8mV spikes
21mV of ripple
28
AC VMC Model for Buck Converter
RTN
PWM
and
Drivers
V
REG
Oscillator
Ramp
Generator
+
VREF
PVCC
K
PWM
VDD
V
C FB
DIFFO
VOUT
GSNS
+
K
FB
K
EA
COMP
PGND
LDRV
BOOT
SW
HDRV
C
R
LOAD
V
IN
RTN
V
OUT
X
LC
SW
V
C
X
LC
V
OUT
K
FB
K
EA
V
REF
K
PWM
V
IN
SW
T
V
(s)
+
-
V
OUT
29
AC CMC Model for Buck Converter
Peak CMC PWM is the result of a comparison
between a control signal, a signal proportional to the
inductor current, and a fixed saw tooth (for slope
compensation)
Whether it is:
Current feedback and sawtooth vs. control signal
Current feedback and control signal vs. sawtooth
Control signal and sawtooth vs. current feedback
From a small signal standpoint, the resulting
modulation is the same!
Sawtooth
Control
Current
+
Modulator Output
30
AC CMC Model for Buck Converter
Vout
V
IN
RTN
RTN
HDRV
SW
LDRV
PGND
COMP
FB
DIFFO
VOUT
GSNS
PVCC
VDD
CS-
CS+
BOOT
+
+
+
+
Oscillator
Ramp
Generator
PWM
and
Drivers
VREG
Rload
C
L
SW
VREF
R
s
C
s
X
LC
K
FB
K
E
A
K
PWM
V
C
K
CS
+Vout
V
C
X
LC
V
OUT
K
FB
K
EA
V
REF
K
PWM
H
e
(s)
K
CS
X
I
V
IN
SW
T
V
(s)
T
I
(s)
I
L
+
-
+
-
V
C
X
LC
V
OUT
K
FB
K
EA
V
REF
K
PWM
H
e
(s)
K
CS
X
I
V
C
X
LC
V
OUT
K
FB
K
EA
V
REF
K
PWM
H
e
(s)
K
CS
X
I
V
IN
SW
T
V
(s)
T
I
(s)
I
L
+
-
+
-
31
DC/DC Boost Converter
TPS40210 controller operating ~700 kHz
9- to 18-V input (12-V nominal)
24-V output with 1-A capability
32
Assumptions in Steady-State Operation
1. Vs balance across the inductor
Energy in during a period equals energy out during the
same period
Net change of charge in a period is zero
2. Charge balance in the output capacitor
Energy in during a period equals energy out during the
same period
Net change of charge in a period is zero
3. Ripple voltage across the capacitor is small compared
to the output DC voltage
33
Basics of Operation
No switching: V
OUT
~ V
IN
SW turns ON:
Voltage across the inductor approaches ~ V
IN
Energy is stored as function of input voltage, L, t
ON
D is biased OFF, blocking discharge of the output capacitor
SW turns OFF:
Stored energy is released through D to the output
Non-pulsating input current Pulsating output current
Level of ripple determined by CCM or DCM operation
C
OUT
Load
Input Output
L
SW
D
+ -
Current
- +
34
Basics of Operation
No Switching: V
OUT
~ V
IN
SW turns ON:
Voltage across the inductor
approaches ~ V
IN
Energy is stored as function of input voltage, L, t
ON
D is biased OFF, blocking discharge of the output capacitor
SW turns OFF:
Stored energy is released through D to the output
Non-pulsating input current Pulsating output current
Level of ripple determined by CCM or DCM operation
C
OUT
Load
Input Output
L
SW
D
+ -
- +
Current
35
Right-Half-Plane Zero
The effect of any control
action during the ON time
is delayed until the switch
is turned OFF
Output response is initially
in the opposite direction of
the desired
correction
RHP Zero
C
OUT
Load
Input Output
L
SW
D
1 k 100 k 10 k
0
10
100
20 0
30
100
40
Frequency (Hz)
G
a
i
n

(
d
B
)
100 10
Gain
Phase LHP Zero
Phase RHP Zero
P
h
a
s
e

(
D
e
g
r
e
e
s
)
36
Continuous-Conduction Mode (CCM)
Switching cycle is composed of two intervals
1. When the switch is ON, stored energy builds in the
inductor
2. When the switch turns OFF, energy transfers to the
output through the rectifier
Inductor current
ON-time slope:
The inductor current
OFF-time slope:
The switch duty cycle:

IN
IL(ON)
V
m
L

IN OUT
IL(OFF)
V V
m
L
=
IN
CCM(ideal)
OUT
V
D 1
V
Inductor
Current
Rectifier
Current
Switch
Current
Switch-
Node
Voltage
Switch On
Switch
Off
I
L(OFF)
I
L(ON)
I
OUT_AVG
m
IL(ON)
m
IL(OFF)
V
OUT
37
Loss Elements in CCM
ON losses
Inductor DCR
MOSFET R
DS(ON)
Current sense resistor
OFF losses
Rectifier voltage drop
Inductor DCR
C
OUT
Load
Output
Voltage
L
Input
Voltage
R
L
ON Losses
OFF Losses
D1
R
ISENSE
R
DS(ON)
CCM
2
V I (R R ) V I (R R ) 4I (R R R ) (V V )
IN OUT DS(ON) ISENSE IN OUT DS(ON) ISENSE OUT L DS(ON) ISENSE OUT d
2(V V )
OUT d
D 1
+ + + + + + + +
+
=
(

IN
CCM(ideal)
OUT
V
V
=
If losses => zero
D 1
Reduces to
38
Discontinuous Conduction Mode (DCM)
Switching cycle is composed of three intervals
1. Energy is stored in the inductor during the ON time of the
switch
2. When the switch turns OFF, energy transfers to the output
through the rectifier
3. A third interval during which the energy in the inductor is zero
Inductor
Current
Rectifier
Current
Switch
Current
Switch-
Node
Voltage
Switch On
Switch
Off
Idle
period
V
OUT
I
OUT_AVG
V
IN
t
fall
I
L(OFF)
I
L(ON)
m
IL(ON)
m
IL(OFF)
There is essentially
no current flowing in
the power stage
during the third
interval
39
Designing for CCM or DCM
Given fixed-frequency operation, the only parameter to
adjust is the inductance
For a given L, this is the CCM/DCM boundary current
IN s
OUT_DCM CCM CCM
V T
I D (1 D )
2L

=
5
V (V)
IN
I

(
A
)
O
U
T
_
D
C
M
5 10 15 20 25
0
0.03
0.06
0.09
0.12
0.15
CCM
Operation
DCM
Operation
40
Current in CCM
Continuous
current flow in
inductor
Some pedestal
in diode and
switch current
Diode switching
and recovery
losses significant
in CCM
C
OUT
Load
Input Output
L
SW
D
6
4
2
0 I
n
d
u
c
t
o
r
C
u
r
r
e
n
t
(
A
)
6
4
2
0
D
i
o
d
e
C
u
r
r
e
n
t
(
A
)
6
4
2
0
S
w
i
t
c
h
C
u
r
r
e
n
t
(
A
)
CCM
I
Inductor
CCM
RMS =
2.1 A
CCM
I
Diode
CCM
AVG =
1.0 A
CCM
I
Switch
CCM
RMS =
1.5 A
0 2 4 6
Time (s)
41
Current in DCM
Large peaks in
all currents
RMS current is
higher
No reverse
recovery losses
in the rectifier
C
OUT
Load
Input Output
L
SW
D
6
4
2
0 I
n
d
u
c
t
o
r
C
u
r
r
e
n
t
(
A
)
6
4
2
0
S
w
i
t
c
h
C
u
r
r
e
n
t
(
A
)
6
4
2
0
D
i
o
d
e
C
u
r
r
e
n
t
(
A
)
DCM
I
Inductor
DCM
RMS =
3.0 A
DCM
I
Diode
DCM
AVG =
1.0 A
DCM
I
Switch
DCM
RMS =
2.2 A
0 2 4 6
Time (s)
42
CCM/DCM - Differences in Current
Peak and RMS
currents are larger in
DCM
Conduction losses
will be higher
Diode-switching and
recovery losses will
be higher in CCM
MOSFET turn-OFF
losses higher in DCM
For the diode rectifier,
the average current is
the same
C
OUT
Load
Input Output
L
SW
D
0 2 4 6
6
4
2
0 I
n
d
u
c
t
o
r
C
u
r
r
e
n
t
(
A
)
CCM
I
Inductor
DCM
I
Inductor
DCM
RMS =
3.0 A
CCM
RMS =
2.1 A
6
4
2
0
D
i
o
d
e
C
u
r
r
e
n
t
(
A
)
CCM
I
Diode
DCM
I
Diode
DCM
AVG =
1.0 A
CCM
AVG =
1.0 A
6
4
2
0
S
w
i
t
c
h
C
u
r
r
e
n
t
(
A
)
CCM
I
Switch
DCM
I
Switch
DCM
RMS =
2.2 A
CCM
RMS =
1.5 A
Time (s)
43
VMC CCM Small-Signal Model
Simplified small-signal
block diagram
F
m
G
vd
(s)
V
OUT
V
C
D
V
IN
K
EA
V
REF
+

K
FB
T (s)
v
Modulator gain, F
m
m
a s
1
F
m T
=

Oscillator
Sawtooth
Resulting
PWM
m
a
Control
Voltage
PWM
Oscillator Sawtooth
Control Voltage +

44
Peak-Current-Mode Control
Modulator gain
m
n s
1
F
m T
=

n IL(ON) ISENSE CS
m m R A =
Where
Switch
Current
Resulting
PWM
T
s
m
n
PWM
Switch
Current
Error
Amplifier
R
ISENSE
A
CS
Control Voltage
+
+

Control
Voltage
F
m
G
vd
(s) V
OUT
V
C
V
REF
D
+ +

V
IN
V
IN
K
EA
T
I
(s)
T
v
(s)
A R
CS ISENSE

K
FB
H
e
(s)
G
id
(s)
45
FLYBACK CONVERTER
+
+
46
FLYBACK CONVERTER
Verror amp
CLK RAMP
FET SOURCE
Discontinuous Waveforms
PRIMARY
CURRENT
SECONDARY
CURRENT
47
FLYBACK CONVERTER
Verror amp
CLK RAMP
FET DRAIN
PWM
PRIMARY
CURRENT
SECONDARY
CURRENT
CONTINUOUS WAVEFORMS
48
FLYBACK CONVERTER
FET DRAIN
PRIMARY
CURRENT
SECONDARY
CURRENT
A ring appears on the drain that is caused by the leakage inductance resonating with the Coss
of the switch FET the other ring is caused by the dead time when the transformer is reset and
waiting for the next on time.
49
FLYBACK CONVERTER
Discontinuous Continuous
Volt seconds in equals
volt seconds out
Volt seconds in equals
volt seconds out
tonmax
Vout 1 + ( ) Tr ( ) .9 T
Vinmin 1 ( ) Vout 1 + ( ) Tr +
tonmax
Vout 1 + ( ) Tr ( ) T
Vinmin 1 ( ) Vout 1 + ( ) Tr +
V L
dI
dT

V L
dI
dT

dI
Vl Ton
L
dI
Vl Ton
L
Lp
Vinmin tonmax ( )
2
2.5 T Pomax
Lp
Vinmin 1 ( ) Vinmin tonmax
2

2.5 Polow T
Ipri_p
Vinmin tonmax
Lp
Ipri_ramp
Vinmin tonmax
Lp
Icpr
Pin
Vinmin
ton
Tmax

Pin
1
2
Lp Ip
2

T
Ipri_peak .5 Ipri_ramp Icpr +
Ipri_step Ipri_peak Ipri_ramp
50
SEPIC CONVERTER
51
SEPIC CONVERTER
52
SEPIC CONVERTER
53
SEPIC CONVERTER
Design Equations
I
L1avg1
V
out
I
outmax

V
inmin

:=
Duty
Vout
Vout Vin +
:=
I
L1pk1
I
L1avg1
V
inmin
d
max

2 L
act1
f
s

+ :=
To find an inductor which will keep the converter in
the continuous conduction mode this value is used
for both inductors
L
Vin D
fs Io
Vo
Vin
1 +
|

\
|
.

>
54
4 SWITCH BUCK BOOST
Boost
Gate
Drive
Buck
Gate
Drive
PWM Ramp
Waveform
Boost
Buck
Vin Max
Vin Min
Vin = Vout