JOURNAL OF COMPUTING, VOLUME 4, ISSUE 2, FEBRUARY 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.

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An Improved Heuristic Algorithm to Minimize Complete Test Set of K-CNOT Circuits for Single and Multiple Stuck-at Fault Model
Muhammad Ibrahim, Ahsan Raja Chowdhury
Abstract We consider the problem of testing reversible circuits for a particular fault model: Stuck-at (SA) Fault Model. We propose a heuristic algorithm that produces the Complete Test Set (CTS) of a reversible circuit for Single Stuck-at Fault (SSF) and Multiple-Stuck-at Fault (MSF) models. Though our algorithm works only for an important subclass of reversible circuits the circuits consisting of k-CNOT gates (k = 2), any n-wire circuit having 0-CNOT or 1-CNOT gates can be converted into a (n + 2) wire circuit having only k-CNOT gates with k = 2 at some additional hardware cost. The problem of generating optimum CTS is NP-hard, so the CTS generated by our algorithm is not necessarily optimal, but minimizing the size of the complete test set is our key concern. We analyze time and space complexity of our algorithm to show that it is computationally feasible. We discuss the criteria for which our algorithm returns maximum and minimum CTS, i.e., n and 2 for an n-wire circuit respectively. Finally we provide experimental results after running our algorithm on some benchmarks circuits and compare it with existing methods to show how it outperforms almost all of the existing algorithms in terms of number of test vectors in CTS but is outperformed by some of the existing ones in terms of hardware cost. Index Terms Automatic Test Pattern Generation, Complete Test Set, Design for Test, Multiple Stuck at Fault, Single Stuck at Fault.

1 INTRODUCTION

HE more logic elements are packed in conventional computer, the more heat is dissipated. When a computational system erases a bit of information, it must dissipate ln 2xkT energy, where k is Boltzmann's constant and T is the temperature. In room temperature, this is about 2.9 x 10-21 joules [1], [2]. This is roughly the kinetic energy of a single air molecule at room temperature. As dissipating excessive heat creates manifold problems, people search for some alternatives. Reversible circuits satisfy us in this regard as they dissipate very low power. Moreover, reversible circuits are essential components of quantum logic [3]. Testing is one of the final phases of the production of a circuit and is one of the paramount issues the circuit manufacturers have to address in the production cycle as they must furnish as much flawless circuits as possible to customers. Testing strategy should be planned much before the final stage because it helps us to detect faults efficiently [4]. It is possible to test a circuit of n input wires with all possible 2 input combinations provided the concept of efficiency has not yet emerged! So the basic target while working with testing strategy is to minimize testing

Muhammad Ibrahim is a Lecturer in the Department of Computer Science and Engineering, Ahsanullah University of Science and Technology, Tejgaon, Dhaka-1208, Bangladesh.

cost both computational and hardware. A test set is a set of test vectors that are applied to the circuit in question to detect faults, if any. Though generating efficient test sets is hard for conventional irreversible circuits, it is significantly simpler for the case of reversible circuits. Agrawal [5] showed that fault detection probability is greatest when the information output of a circuit is maximized. This suggests that it may be easier to detect fault in reversible circuits which are information lossless. Two properties of reversibility simplify the test set generation problem for reversible circuits. The first is controllability; there is a test vector that will generate any given desired state on the wires at any level. The second one is observability, which means, any single fault that changes an intermediate state in the circuit will also change the output. Neither property holds in general for irreversible circuits [6]. In this paper, we propose a heuristic method which, like [7], exploits fixing property of digital circuit, to produce CTS for a given circuit: we apply a test vector at input of the circuit and observe if the output is same as the input. If it does, then we proceed to the next test vector. If it does not, then some wire(s) of the circuit must be faulty. Our target here is to reduce the size of the CTS to 2 (i.e. minimum) using some Design for Test (DFT) of the circuit if needed. We do not consider fault diagnosis in this paper.

Ahsan Raja Chowdhury is an Assistant Professor, Department of ComputRest of this paper is organized as follows: in section 2 er Science and Engineering, University of Dhaka, Dhaka-1000, Banglawe discuss the terms used in this paper with examples. desh.

We also elaborate the existing techniques a bit. In section 3 we provide a definition we introduced in this paper. Then we present our heuristic algorithm and analyze its

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time and space complexity. Then we show for which circuits our algorithm generates maximum and minimum number of test vectors. Finally in section 4 we provide some experimental results and compare them with the existing techniques. Section 5 concludes the paper.

w1 w2 w3 w4 w5

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2 DEFINITIONS AND LITERATURE REVIEW

In this section we discuss some terms and definitions used in this paper and results of some previous research in this field. k-CNOT Gates and k-CNOT Circuits. A k-CNOT gate has k + 1 input wires and k + 1 output wires. It transmits first k inputs unchanged (these inputs are called control inputs), and inverts the last input (this input is called inverting input) if and only if all first k inputs are 1. A circuit is said to be k-CNOT circuit if all of its gates are k-CNOT gates. Such a k-CNOT circuit can be constructed by starting with n wires and iteratively concatenating k-CNOT gates with these n or less than n wires [6], [7]. This iterative construction gives rise to the notion of levels in a circuit: the inputs to the circuit are at level 0, and the outputs of any gate are at one plus the highest level of any of its inputs [6]. Example 2.1 Example of different k-CNOT gates and a CNOT circuit are shown in Fig. 2.1. Design for Test (DFT). If a circuit is modified in terms of hardware to aid testability, while somehow retaining its original functionalities, then the modified circuit is called a Design for Test (DFT) for the original circuit. By doing so, Automatic Test Pattern Generation (ATPG) becomes much easier because DFT is constructed based on a particular fault model to ease the testability for that fault model. DFT often eases the controllability and observability of a circuit. However, some additional cost is incurred to construct a DFT if additional hardware is needed [8].
a

Fig. 2.2. (a) Original circuit, (b) A DFT of the original circuit

b
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ab

a1 a2 a3

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a1 a2 a3

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ak ak+1

ak

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a1 a2 ak ak+1

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Fig 2.1. (a) 0-CNOT (NOT) gate, (b) 1-CNOT gate, (c) k-CNOT gate, (d) Levels of a k-CNOT circuit

Example 2.2 Figure 2.2 (a) shows a k-CNOT circuit with k 0. To make it a k-CNOT circuit with k 2, a DFT corresponding to the original circuit is shown in Figure 2.2(b), which is constructed by adding two extra wires and by replacing all 0-CNOT and 1-CNOT gates by 2CNOT gates. The extra control input of 1-CNOT gates come from one of the newly introduced wires and two extra control inputs of 0-CNOT gates come from both of the two newly introduced wires. Now the reader can verify that if both of the newly added wires are set to 1, then the DFT functions just as the original circuit implying the DFT is a valid one.

Automatic Test Pattern Generator (ATPG). Automatic Test Pattern Generator (ATPG) is an automated tool that produces test vectors for a particular fault model. After applying these test patterns on a circuit, we can determine if any kind of that particular fault exists in the circuit, and in some cases we can localize that fault as well. A fault is said to be detected if we can distinguish between a faultless and faulty output by at least one test vector. The test vectors generated by the ATPG are generally used after manufacture phase of the production cycle because only at that time most of the faults take place. The efficiency of ATPG depends on the number of test vectors it generates, its computational time and computer memory space it requires, the range of faults it can handle, the percentage of faults it covers, the level of abstraction used to represent the circuit (gate level, registertransistor level, switch level) at hand etc. It is mention-worthy that ATPG problem is NPcomplete (by reduction from the Boolean Satisfiability problem) [9]. Fault Model. A defect or fault is an error introduced in a circuit during the manufacturing process. Faults that occur in a digital circuit can be categorized in different types. Some faults are permanent because their effect is permanent; while some others effects change depending on the environment (e.g. temperature, power supply voltage etc); some other faults occur randomly. A fault model describes the effect of a particular type of fault of a circuit. Sometimes ATPG is constructed based on a particular fault model because this strategy reduces the complexity of ATPG [10]. Single Stuck-at Fault (SSF) and Multiple Stuck-at Faults (MSF). Stuck-at Fault model is one of the most widely used fault models. In this model, one or more of the signal lines of a circuit is assumed to be stuck at a particular logic value (0 or 1) regardless of the input is being applied to the circuit. Hence, if a circuit has n signal lines, there can be potentially 2n stuck-at faults in that circuit, of which some can be viewed as being equivalent to others [6]. If we assume that there can be at most one stuck-at fault in the whole circuit, then we are working on single stuck-at fault (SSF) model. And if multiple stuck-at faults (MSF) are under our consideration, then we are working on multiple-stuck-at fault model [6[, [7], [11]. Example 2.3 This example delineates the effect of SSF on a 1-CNOT gate. Let the lower output wire of the circuit of Fig. 2.3 is stuck at 0. Then Table 2.1 shows the error-free output of the circuit and Table 2.2 shows the erroneous (due to stuck-at-0 fault of the lower output wire) output.
a b a a b

Fig. 2.3. 1-CNOT Gate

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TABLE 2.1 Truth table for fault-free 1-CNOT gate Input 0 0 0 1 1 0 1 1 Output 0 0 0 1 1 1 1 0

TABLE 2.2 Truth table for faulty 1-CNOT gate Input 0 0 0 1 1 0 1 1 Output 0 0 0 0 1 0 1 0

Complete Test Set (CTS). A test set is said to be complete for a particular fault model if it (i.e. the test vectors contained in it) can detect each fault of that fault model [6]. The goal here is, given a reversible circuit C and a fault model F, to generate a set of test vectors that can be used to detect all faults of F. We call such a test set complete. A complete test set with the fewest possible test vectors is called optimal CTS [6]. Example 2.4 Considering SSF model, a test set is complete for a circuit if by applying all of its test vectors, all wires at all levels are set to both 0 and 1. Fixing Property. If a vector v is applied to the input of a circuit and same vector is found in the output, then the circuit is said to be fixing the input vector v [6], [7]. Example 2.5 The circuit of Fig. 2.1(d) fixes the input vector <0 0 1 0 1> because if we apply this vector to its input, we get the same vector at the output. Assumption. We follow the following assumptions throughout the whole paper unless otherwise stated: (a) An n-wire reversible circuit consisting of m number of k-CNOT gates is given (k 2 and m 0). If we have 0CNOT and/or 1-CNOT gates in the original circuit, then a DFT can be constructed easily by adding at most 2 extra wires (so that 1-CNOT and 0-CNOT gates becomes 2CNOT gates having necessary extra control input(s) from the extra wire(s)); so number of wires becomes n + 2, and the DFT can behave just as the original circuit as mentined in example 2.2. Thus, without losing any generality, we assume that we have only k-CNOT gates with k 2. When we use any k-CNOT gates with k = 0 or 1, we shall specify it explicitly. (b) A test vector (TV) is a binary vector <t1 t2 , tn> where ti is ith bit. (c) We consider only SSF in this paper, and Proposition 2 (later it comes) says that, it is sufficient for MSF. (d) 0k (1k) means vector of k consecutive zeros (ones). (e) In spite of altering any bit in any level of the circuit except the last, if final output of the circuit is equal to the input, then the input vector is also fixed by definition. But this concept leads to some sort of extra complexity. So throughout the whole paper, when we say a vector is fixed by a circuit, we mean that no bit of the input vector is altered by any gate throughout the whole circuit. (f) The whole paper is fixing property oriented unless otherwise stated. For example, if we say a test vector is valid for a circuit, it tacitly means that this test vector is fixed by that circuit and vice versa. Literature Review. Research reported so far in the field of reversible circuit testing for stuck-at fault model is not bountiful. Below we briefly discuss some previous work in this field.

Patel et al. [6] proved the following two propositions. First one provides a simple necessary and sufficient condition for a test set to be complete for the stuck-at fault. Second one shows that SSF and MSF models are equivalent for reversible circuits. Proposition 1 [6]. Under the SSF model a test set is complete if and only if each of the wires at every level can be set to both 0 and 1 by the test set. Proposition 2 [6]. Any test set that is complete for the SSF model is complete for the MSF model. Authors of [6] then formulated the problem of constructing minimal test set as an integer linear program (ILP) with binary variables ti associated with each input vector; ti takes a value of one if the corresponding input vector is in the test set, and zero otherwise, as shown below. Authors of [6] ensured the completeness of the test set by a set of 2n(d + 1) linear inequality constraints. A minimal test set then determined by minimizing the sum of the tis. The technique is not feasible for large circuits, also used an algorithm which decomposes the circuit into smaller sub-circuits acting on fewer input/output bits, and uses the ILP formulation iteratively for these subcircuits combining the test vectors dynamically [6]. We state the following lemma extracted from [6], [7]: Lemma 1. If we fix a TV, then ith wire at all levels of the circuit is tested for SA- ti~ (ti inverse) fault for all i, 1 i n. Avik [7] showed that all stuck-at faults in an n-wire kCNOT circuit C(n) with k 2 can be detected using at most n TVs, namely, n weight-1 vectors. C(n) has a CTS of size n for MSFs. He proved this using fixing property. He has also shown that if an n-wire k-CNOT circuit (k 0) is modified by introducing an extra wire that feeds a new control input added to every k-CNOT gate, the resulting circuit has CTS of size 3 for MSFs. We draw the following two lemmas from [7]: Lemma 2. Every k-CNOT gate with k 2 fixes any weight-1 vector (the vector having all 0 is fixed by any circuit). Lemma 3. Proposition1 and Lemma 2 implies that we need at most n TVs to check all SSF in a k-CNOT circuit with k 2. Allen et al. [12] proposed an algorithm which detects and localizes all Missing Gate Fault (MGF), Lock Gate Fault (LGF) and SSF. The approach taken by them was based on a single signal vector that propagates through the circuit attempting to set a prioritized list of tests while maintaining the largest set of possible tests for the next stage. The signal vector moves forward and backward through the circuit setting appropriate bits for test and leaving as many of the lesser tested lines as possible in the dont care state. Ito et al. [13] showed that it is NP-hard to generate minimum CTS for stuck-at faults of a reversible circuit.

3 PROPOSED METHOD
Before introducing our method, we provide a definition used throughout this paper.

3.1 Description of a Gate and Description Table of a k-CNOT Circuit

Let a gate g has wire indices g1, g2, , gp as control inputs.

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Then we call the sequence g1, g2, , gp the description of the gate g. If g is 0-CNOT gate, then it has no description as we are concerned here with only the control inputs. If we construct a table where the rows are descriptions of the gates of a circuit, then we call this data structure Description Table of the circuit. Example 3.1 Fig. 3.1(b) shows the description table of the circuit shown in Fig. 3.1(a).
Gate Indices of Control Input 3 1 4 1 2 1 4 4 5 2 3 3

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1 2 3 4 5 6 (a) Original circuit

(b) Corresponding description table.

Fig.3.1. A sample circuit and its correcponding description table

3.2 Generating Minimum Number of Test Vectors

The following theorem shows that getting minimum |CTS| i.e. 2 for a circuit is not rarity there are more than 2 - 1 circuit configurations having |CTS| = 2 for an nwire k-CNOT (k 2) circuit. Theorem 1. Let an n-wire circuit consisting of m number of kCNOT (k 2) gates is given. Then for SSF: (a) Minimum size of CTS is 2. (This is also true for k 0), (b) If |CTS| = 2, then 2nd test vector, TV2 = inverse (1st test vector, TV1) and vice versa (inverse means ti is altered for all i) (This is also true for k 0), (c) There may be more than 2 - 1 circuit configurations where |CTS| = 2. Proof. (a) If m = 0 i.e. there is no gate in the circuit, then 2 TVs 0n and 1n suffice as CTS because they set all wires of all levels to both 0 and 1. Otherwise, we prove it by contradiction. Let |CTS| = 1. This means ti in TV1 is either 0 or 1, but not both. So we cannot test ith wire for stuck-at-ti fault (SA-ti fault) with mere TV1 (Lemma 1). Hence |CTS| cannot be 1. So to test ith wire for SA-ti fault, we need at least another TV such that ti in TV2 or in some other subsequent TV will be t i in TV1, thus completes the proof. (b) We prove it by contradiction. Let |CTS| = 2 and ti in TV2 is same as it was in TV1. This means ith wire is not tested for SA-ti fault, so at least another TV is needed, which is a contradiction of the assumption. (c) If m = 0, then TV1 = 0n and TV2 = 1n (or TV1 = 1n and TV2 = 0n) suffice as CTS. Let S be the set of the rest 2 - 2 input patterns. Now if we can show that for each input pattern inp_pattrn S, there exist at least one circuit where TV1 = inp_pattrn; TV2 = inverse (inp_pattrn) and |CTS| = 2, then the proof completes. Let S1 = {i1, i2, , ip} and S2 = {j1, j2, , jq}(1 p n-1, 1 q n-1, p + q = n and S1 S2 = ) where S1 be the set of positions in TV1 which are 1 and S2 be the set of positions in TV1 which are 0. Now if the circuit in question has |CTS| = 2, then, according to part (b), the second and last

TV, TV2 = inverse (TV1) and S1 be the set of positions in TV2 which are 0 and S2 be the set of positions in TV2 which are 1. Now we will show that there exists at least one circuit where all the above statements are true. We can easily find a circuit where any arbitrary input pattern, inp_pattrn S can be TV1 because what we need to make sure that there is no gate gi in the circuit such that gi S1. Likewise, for TV2 to be valid and to be the last TV of CTS, there can be no gi such that gi S2 for all i (1 i m). (If it be so, then the TV will not be fixed by the gate gi). The reader can easily verify that to find such a circuit is always possible because we have all the choices to select gates to construct a desirable circuit. Moreover, it is also imperative that we can have more than one circuit that has |CTS| = 2 with same TV1 and TV2 what we need is to just add as many gates as we wish without violating the rule that every gate has 0 in at least one of its control inputs. Now we provide some lemmas which will be utilized in the proposed method. Lemma 4. Let k 1. Then a k-CNOT gate which receives at least one 0 in any of its control input fixes the input vector. Proof. In a k-CNOT gate, inputs are (a1, a2, , ak, b) and b). So corresponding outputs are (a1, a2, , ak , a1a2ak if ai = 0 (1 i k), then output = input. Lemma 5. If ith wire is tested for both SA-0 and SA-1 faults by a subset of TVs in the CTS, then ti may be set to dont care in the following TVs, but choosing ti = 0 eases the effort of fixing Proof. To fix a TV across the total circuit, we need at least one control input wire of each k-CNOT gate of a circuit is 0. So the more number of 0s in the TV, the more chances that the TV will be fixed. Lemma 6. If m 0 and |CTS| = 2, then 0n and 1n as TV are not possible. Proof. We prove it by contradiction. If TV1 = 0n, all wires at all levels are tested for SA-1 fault. Then when the next and last TV, TV2 = 1n, the k-CNOT gates of the first level get all 1s in their control inputs, so they invert the inversion input from 1 to 0. This means these wires at level 1 are not tested for SA-0 fault, so the circuit needs more TV(s) in addition to these TV1 and TV2. Lemma 7. If 0-CNOT and 1-CNOT gates exist in a circuit, it cannot be tested for SSF model using mere fixing property. Proof. 0-CNOT gate has no way to fix its input. 1-CNOT gate fixes its input if and only if its single control input is 0. So we cannot test its control input for SA-0 fault using mere fixing property. Now exploiting the above lemmas, we present in the next section a heuristic algorithm that produces CTS for a given circuit. Our proposed algorithm works, briefly, as follows: it starts with a temporary (or tentative) TV, and changes appropriate bits of this TV from 1 to 0 in order to make sure that this TV be fixed by the entire circuit. To achieve this goal, it consults with the configuration (description table) of the circuit and ensures that at least one control input of each gate is set to 0. To achieve this goal, we choose the index of the first wire of the description of each gate and set the corresponding bit in the temporary TV to 0. The algorithm also keeps record of the stuck-at

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faults already tested. When all wires are tested for both SA-0 and SA-1 fault, it halts. It starts with a tentative TV 1n. To get the subsequent tentative TVs, the record of already tested faults is consulted and the tentative TV is set accordingly so that all untested faults are covered by it i.e. all bits are set to 0 except the indexes that are not tested for SA-0 fault ( these bits are set to 1). The basic target of this technique is to minimize the number of changes in the temporary TVs so that in the end |CTS| is minimized.

return TV. Algorithm 4: Efficient_Complete_Test_Set_Generator (ECTSG) Input: The configuration of a k-CNOT (k 1) circuit is in description table as input. Input pattern is as follows: each gate occupies 1 row in the description table. The elements of each row are the wire indices of a particular gate where this gate has control inputs. Inversion input wire index is not entered. Each row is terminated with a -1 value which works as sentinel. Output: A set CTS of TVs that constitute the CTS for the given circuit. CTS is initially empty. Step 1: (a) Initialize TV(temp) with all 1 i.e. 1n. (b) Initialize status table by filling all n entries of its both columns with 0. First and second columns represent SA-1 and SA-0 fault respectively. Step 2: call Process_description_table. Step3: for each gate g in description table do if g does not fix TV(temp), then do let w be the first wire index of this gate in description table i.e. first element of the row meant for this gate. Set tw in TV(temp) to 0. Step 4: Now after possible modification, TV(temp) is a valid TV of CTS. So include it in the set CTS. Step 5: call Adjust_status_table with TV(temp) as argument. Step 6: Check if status table is full or not i.e. if there is any element in any row is 0 still, indicating that this wire needs further testing. If no such element found, then algorithm halts, so go to step 8 then. Step 7: If the algorithm does not halt in step 6, it indicates that there exist some i such that ith wire is not tested for SA-0 and/or SA-1 fault. So we need at least one more TV. (a) Call Get_New_TV(temp). The retuned TV by Get_New_TV(temp) is the TV(temp) for the next iteration. (b) Go to step 3. Step 8: Return CTS. Now we provide some examples in order to show how our proposed algorithm works.

3.3 The Algorithm

In our algorithm, we use description table, status table and TV(temp) ( Temporary Test Vector). Description table has already been defined. The status table is an n x 2 array. Each row holds the current test status for both SA-0 and SA-1 faults of ith wire. (For example, 0 if not tested, 1 if tested) TV(temp) is an n element array. This is the tentative TV of which our algorithm converts some of its 1 bits to 0. The algorithm and its procedures are given below: ___________________________________________________ Algorithm 1: Process_description_table Input: Description table of a circuit. Output: Description table of the circuit with some sorting applied (the rationale behind sorting is discussed later in this section). Step 1: Sort each row of the description table in increasing order of their elements. Step 2: Treat a row of a description table as a single element and then sort all rows in decreasing or der of their first element. return Description table. The following procedure adjusts the status table as follows: for all i (1 i n), if ti of TV(temp) is 0, then set first element of ith row in status table to 1, indicating that ith wire is tested for SA-1 fault. Otherwise i.e. if ti of TV(temp) is 1, then set second element of ith row in status table to 1, indicating that ith wire is tested for SA-0 fault. ___________________________________________________ Algorithm 2: Adjust_status_table Input: Status table and a TV Output: Adjusted status table. Step 1: Adjust status table as follows: for all i in {1, 2, , n}, do if ith bit of TV is 0, then set 1st eleth row of the status table to 1. ment of i else set 1st element of ith row of the status table to 0. return Status table. ___________________________________________________ Algorithm 3: Get_New_TV Input: Status table. Output: A TV that acts as the TV(temp) for the next iteration. Step 1: Calculate the TV as follows: for all i in {1, 2, , n}, do if ith row of status table has 0 in the se cond element, set ti to 1. else set ti to 0.

w1 w2 w3 w4 w5 w6

Gate

Indices of Control Input 1 1 1 1 1 3 4 5 6 7

1 2 3 4 5

(a) (b) Fig. 3.2(a) Circuit, (b) Corresponding Description Table after sorting

Example 3.2(a): Figure 3.2 shows an example where idel|CTS| is 2, i.e. optimal. The TVs generated by ouralgorithm are: TV1(temp) = (1 1 1 1 1 1 1), TV1 = (0 0 0 0 0 0 1), TV2(temp) = (1 0 0 0 0 0 0), TV2 = (1 0 0 0 0 0 0) So, |CTS| generated by ECTSG is also 2.

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Gate 1 2 3 4 5 6 7 8

Indices of Control Input 3 2 2 2 1 1 1 1 4 3 3 4 4 3 2 2 4 4

Gate 1 2 3 4 5 6

Indices of Control Input Gate 4 3 2 1 1 1 5 4 3 2 4 3

(a)

(b)

Fig. 3.3 (a) Circuit (b) Corresponding Description Table after sorting

Example 3.2(b) Figure 3.3 shows an example circuit where ideal |CTS| = n (=4). Here TV1(temp) = 1 1 1 1, TV1 = (0 0 0 1), TV2(temp) = (1 1 1 0), TV2 = (0 0 1 0), TV3(temp) = (1 1 0 0), TV3 = (0 1 0 0), TV4(temp) = (1 0 0 0), TV4 = (1 0 0 0). So |CTS| generated by ECTSG is also 4. Example 3.2(c) And finally, Figure 3.4 shows an example circuit where |CTS| generated by ECTSG is not optimal. Here optimal solution is TV1 = (0 1 1 0 0 1), TV2 = (1 0 0 1 1 0) i.e.|CTS| = 2. But ECTSG generates TV1 = (0 1 0 1 0 1), TV2 = (1 0 0 0 1 0), TV3 = (0 0 1 0 0 0) i.e. |CTS| = 3. w1 w2 w3 w4 w5 w6
Gate Indices of Control Input 5 3 3 1 6 4 5 2

(c) Fig. 3.5 (a) Original description_table for the sample circuit shown in Fig. 3.1(a), (b) Rows sorted in increasing order of the first elements and each row is also sorted in increasing order (c) Rows sorted in decreasing order of the first elements each row is also sorted in increasing order.

Now we assume that ECTSG does not call Process_description_table in Step 2 rather works directly on the input description table. Table 3.1 shows that the sorting approach adopted in Fig. 3.5 (c) yields most efficient result i.e. |CTS| = 3 that is less than the other two. Table 3.1 Comparison of different sorting styles on description tables shown in Fig. 3.9
|CTS| 4 5 3 CTS (0 1 0 0 1), (1 0 0 0 0), (0 0 0 1 0), (0 0 1 0 0) (0 0 0 0 1), (0 0 0 1 0), (0 0 1 0 0), (0 1 0 0 0), (1 0 0 0 0) (0 0 1 0 1) , (0 1 0 1 0) , (1 0 0 0 0)

Description Table Fig. 3.5 (a) Fig. 3.5 (b) Fig. 3.5 (c)

1 2 3 4

(a) (b) Fig. 3.4 (a) Circuit (b) Corresponding Description Table after sorting

Why sorting was performed: If no sorting is performed on the description table i.e. if Process_description_table is not called in step 2 of ECTSG, the correctness of the proposed method will not be hampered, but possibly different CTS will be generated. So what is the rationale for sorting? To be convinced, consider the following arguments. In the first place, we sort each row of description_table in increasing order of its elements. Now we will investigate the effect of sorting the rows of description_table by the first element of the row, i.e., description_table[i][1]. Consider the description table of Fig. 3.5(b) and Fig. 3.5(c) where the rows of description_table are sorted by increasing and decreasing order of the description_table[i][1] respectively (1 i m). Fig. 3.5(a) shows the original description table.
Gate Indices of Control Input Gate 3 1 4 1 2 1 4 4 5 2 3 3 (b) Gate 1 2 3 4 5 6 Indices of Control Input Gate 1 1 1 2 3 4 2 3 4 3 4 5

The reason is: in both (fig 3.5. (b) and (c)) cases we choose the first control input k of a gate (i.e. first element of a row in description_table i.e. description_table[i][1] ) to set tk in TV(temp) to 0 if it is not already 0. In the first case of our example given above, the abovementioned first control input k may appear only in the rows where description_table[i][1] is the first element possibly few because it is not natural to have all the gates connected with 1st wire. But in the second case, the first control input k may appear throughout all subsequent rows in the description_table, therefore possibly reducing the total number of changes in TV(temp) (Lemma 5). Recall that ECTSG algorithms basic target is to retain TV(temp) as much as possible in a pass to generate the corresponding actual TV. To convince the reader more, we give a couple of more examples that demonstrate the positive effect (i.e. less number of gates need to be replaced) of sorting in the description table.
Ga te 1 2 3 4 5 6 Indices of Control Input 2 2 3 1 1 1 3 3 4 2 3 4 4 Ga te 1 2 3 4 5 6 Indices of Control Input 3 2 2 1 1 1 4 3 3 2 3 4 4

1 2 3 4 5 6 (a)

Fig. 3.6 (a) Rows sorted in increasing order of the first elements and each row is also sorted in increasing order (b) Rows sorted in decreasing order of the first elements each row is also sorted in increasing order.

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Example 3.3 (a) Consider the description tables of Fig. 3.6 (a) and 3.6 (b) where (b) is sorted according to the approach mentioned above. From Table 3.2 it is evident that this sorting approach yields more efficient result in terms of |CTS|. Table 3.2 Comparison of different sorting styles on description tables shown in Fig. 3.6
Description Table Fig. 3.6 (a) Fig. 3.6 (b) |CTS| 4 3 CTS (0 0 0 1), (0 0 1 0), (0 1 0 0), (1 0 0 0) (0 1 0 1), (0 0 1 0), (1 0 0 0)

Gate

Indices of Control Input Gate 2 3 2 1 1 1 4 3 3 4

Gate

Indices of Control Input Gate 3 2 1 1 1 4 3 3 4 2

1 2 3 4 5

1 2 3 4 5

Figure 3.7 (a) Rows sorted in increasing order of the first elements and each row is also sorted in increasing order (b) Rows sorted in decreasing order of the first elements each row is also sorted in increasing order.

Example 3.3(b): Consider the description tables of Fig. 3.7 (a) and (b) where (b) is sorted according to the approach mentioned above. From Table 3.3 it is evident that this approach yields more efficient result in terms |CTS|. Table 3.3 Comparison of different sorting styles on description tables shown in Fig. 3.7
Description Table Fig. 3.7 (a) Fig. 3.7 (b) |CTS| 4 3 CTS (0 0 0 1), (0 0 1 0), (1 0 0 0), (0 1 0 0) (0 1 0 1), (0 0 1 0), (1 0 0 0)

We can conclude from the above discussion that ECTSG with sorting according to the discussed approach should outperform ECTSG without sorting.

3.3 Evaluation of Proposed Method

Now we evaluate ECTSG from different perspectives. 3.3.1. Optimality of ECTSG ECTSG does not necessarily return optimal result (as in example 3.3 (c)) but it does in many cases as our experimental results have shown. We mentioned earlier that it is NP-hard to generate a minimum complete test set for stuck-at faults on a set of wires of a reversible circuit [13]. 3.3.2. Time complexity analysis The following theorem helps us to estimate the maximum size of the table description_table used in ECTSG. Theorem 2. Let an n-wire circuit consisting of m number of kCNOT (k 2) gates is given and C2 + C3 + Cn-1 = q; qP1 + qP + + qP = p. Then: 2 q (a) There are total p number of different circuits Ci where each k-CNOT gate appears at most once, and then max (mi) = q = O (2); mi is the number of gates in circuit Ci (1 i p).

(b) If we allow more than one occurrence of a gate that have same control input wires in a circuit, then max (mi) = . Proof. (a) As k-CNOT gate has maximum k control inputs and the number of wires is n, so k (n 1). We can have C2 number of 2-CNOT gates, C3 number of 3-CNOT gates, , Cn-1 number of (n 1)-CNOT gates in a n-wire k-CNOT circuit with k 2. So the total number of possible gates are C2 + C3 + + Cn-1 = 2 n 2 = q. Now if we build a circuit where all of the above mentioned gates are used exactly once, then m = q. If some of these gates are not used but the used gates have exactly one occurrence as before, then m < q. Now we can permute these q gates to get a circuit, so the total number of circuits comprised of these q gates is: qP1 + qP2 + + qPq = p. (b) If a circuit is allowed to have more than one instance of any gate, then m may be raised to because we can append as many gates as we wish, but use of some of these gates may be redundant. The following lemma allows us to eliminate identical rows of description_table in ECTSG to keep its size small. Lemma 8. We can confine the size of the description_table of ECTSG algorithm to maximum q = O (2) (q ). Proof. We impose a condition that the same ordering of values of the rows of the description_table should be adopted while taking input for example, if (1, 3) is entered as description of a gate then (3, 1) is considered as a repeated gate and vice versa as these two descriptions are in fact the same from ECTSGs viewpoint. The reason is: if the circuit has gates having same wires as control inputs, then they will have identical rows in the description_table because we do not store the index of inversion input wire. As we use these rows to fix the TV(temp) in ECTSG algorithm, once we have checked a row, there is no need to check another identical row. Hence we can keep only one row in case of duplicity, which completes the proof with the help of the findings of Theorem 2. Time complexity of ECTSG algorithm is O(|CTS|mn ). We come to this conclusion through a step by step calculation. Table 3.3 shows how complexity of ECTSG without step 2 differs with different values of |CTS| and different number of gates. We here exclude step 2 because its complexity will be separately examined later. Table 3.4 Variation of running time of ECTSG without step 2 due to variation of |CTS| and number of gates (m)
|CTS| n n logn logn m O(nc) O(2) (Lemma 8) O(nc) O(2) (Lemma 8) Time Complexity O( nc+2 ) O( 2n ) O( nc + 1logn ) O(2nlogn )

Since any standard sorting algorithm takes O(nlogn) time, so step 2 of ECTSG requires O(mnlogn) + O(mlogm). Hence time complexity of ECTSG is O(|CTS|mn) + O(mnlogn) + O(mlogm). If m = nc, O(nlogn) = O(logm) because logm = lognc = clogn. If m = O(2) (Theorem 2), then logm = log2 = nlog2 = n = O(n) O(nlogn). So roughly complexity of ECTSG is O(|CTS|mn) + O(mnlogn) = O(|CTS|mn), as max|CTS|= n.

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3.3.3. Analysis of Space Complexity The size of description_table and status_table are m x (n 1) and n x 2 respectively. Sizes of other variables are negligible and hence the required space is O(mn). We can conclude from the analysis of time and space complexity that ECTSG is computationally feasible. 3.3.4 Generation of Maximum |CTS| (i.e. n) Now we state the requirement of a circuit to get n TVs (i.e., maximum (Lemma 3)) as CTS generated by ECTSG . Theorem 3. Let an n-wire circuit consisting of m number of kCNOT gates (k 2) is given. ECTSG algorithm generates n test vectors, namely, n weight-1 vectors if and only if the circuit has the n(n 1)/2 gates having corresponding rows in the description_table as follows: {(n 1, n), (n 2, n 1), (n 3, n), (n 3, n 1), (n 3, n 2), , (1, n), (1, n 1), (1, n 2), , (1, 2)}. The circuit may have additional gates. Proof. We prove it by showing that the condition mentioned in the statement is both necessary and sufficient. Sufficient condition (i.e. the if part of the statement): We prove it by contradiction, i.e., we will let a TV is generated by the ECTSG algorithm which has 1s in more than one position and then will show that it is not possible to get such a TV if the statement of the theorem is true. We argue for the case of two bits that are 1 in a TV; it suffices for the cases where more than two bits are set to 1. Let two bits, tp and tq, of a TV generated by the ECTSG algorithm are 1. It means that there is no gate gi in the circuit which has description (p, q) or (q, p); which contradicts the statement of the theorem which mentions that we have all the gates of all combinations of 2 digits. The ECTSG algorithm also never generates all 0 TV, so it continues to generate weight-1 (i.e., having exactly one 1) TVs. As there can be at most n weight-1 vectors for n-wire circuit, so the ECTSG algorithm generates all these vectors and then ends (because status_table will be full by the end of generating n weight-1 TVs), which completes the proof. Note that this proof is valid no matter what type of sorting is performed on the elements of description_table. Necessary condition (i.e. only if part of the statement): We offer constructive proof. Let a circuit (i) have all the gates mentioned in the statement except one gate (p, q), and (ii) this gate is the first missing gate in case of multiple missing gates, i.e. all gates having description_table[i][1] > p (which remain up from the expected position of (p, q) in the description_table) meet the condition mentioned in the statement. It should be kept in mind that according to the statement, the circuit may have additional gates. Now if we can prove that there must be a TV where tp and tq is 1 and all other tis are dont care, then this implies that we do not have n-weight 1 TVs implying that |CTS| < n so proof will be complete then. Now let us investigate whether tp in the said TV can be set to 0. By considering two cases we can wrap up this job. Case 1: Let some gate (r, , p, ) and/or (r, , p) exists. Our algorithms set a bit tx of TVtemp from 1 to 0 if and only if x is the first element in some row of the description_table. So this gate has no chance to cause to set tp to 0 because p is not the first element here.

Case 2: Let some gate (p, ) exists. We consider two sub cases here. Case a: If p be the index of the maximum or penultimate wire, then this (p, ) gate cannot exist because of the sorting structure of the description_table. More specifically, maximum value never appears as a first element. And as (p, q) is the first missing gate in case of multiple missing gates, so being p the penultimate wire, is also not possible. Case b: We consider two sub cases here. Case b1: let some (k -CNOT) gate (p, ) exists with k 3, i.e. p has at least 2 followers in (p, ). As all followers are greater than p according to the sorting style of the description_table, so they are up in the position of the description_table (again according to the sorting style). As our algorithms scan description_table from top to bottom, so the gates composed of the followers of the gate (p, ) are already resolved (i.e. at least one index of wire of them are set to 0 in the current TVtemp). This implies when (p, ) is scanned, p in TVtemp never set to 0. Case b2: let some gate (p, r). We consider two sub cases. Case b2a: r < p. this is not possible because each row in description_table are sorted in increasing order of their elements. Case b2b: r > p. In this case, r of (p, r) (in current TVtemp) is already set to 0 just before the gate (p, r) is scanned, because the missing gate (p, q) was the topmost missing gate i.e. all other gates that are in upper positions than the expected position of (p, q) in description_table are according to the statement. For further clarity, let we have the gates (r, r + 1), (r + 1, r + 2), (max 1, max) over (p, r). Now it is easy to verify that when (p, r) is scanned, r is already set to 0 for the existence of the just-said gates.
Gate Indices of Control Input Gate 3 2 2 1 1 1 4 4 3 4 3 2

1 2 3 4 5 6

(a) (b) Fig. 3.8 (a) Original circuit (b) Corresponding description table

Example 3.4 Consider the 4-wire circuit of Fig. 3.8 (a) and its corresponding description_table shown in Fig. 3.8 (b). ECTSG generates n weight-1 TVs as CTS for this circuit. Given an n-wire circuit, ECTSG algorithm will generate n test vectors, namely, n weight-1 vectors if and only if the circuit has the n(n 1)/2 gates having corresponding rows in the description_table as follows: { (n 1, n), (n 2, n 1), (n 3, n), (n 3, n 1), (n 3, n 2), , (1, n), (1, n 1), (1, n 2), , (1, 2)}. The circuit may have additional gates. Let us arrange all the gates like: S1 = {(1, n), (2, n), , (n 1, n)}; S2 = {(1, n 1), (2, n 1), , (n 2, n 1 }; Si = {(1, n i + 1), (2, n i + 1), , (n i, n i + 1)};

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Sn 1 = {(1, 2)}; Now we propose the following Lemma considering the above statements. Lemma 9: Let = (i, j); i < j n. If there is exactly one i such that not in Si, then ECTSG generates |CTS|= n 1. Proof: Immediate from the proof of Theorem 3. 3.3.5 Generating Minimum |CTS| In this subsection, we state the requirement of a circuit to have 2 TVs, which is minimum (proved in theorem 1), as CTS by ECTSG algorithm. The following theorem describes the conditions needed for a circuit to be fulfilled in order to have minimum |CTS|, i.e., 2 generated by ECTSG algorithm. Theorem 4. Let an n-wire circuit consisting of m number of kCNOT (k 2) gates is given. Let S = {}. S is built as follows: if sj gi, then S S { gi1} for all i and j (1 j |S|, 1 i m). Now if there exists no gate gi such that gi S, then ECTSG algorithm generates 2 test vectors as CTS. Proof. According to Theorem 1, |CTS| is 2 and in that case, TV2 = inverse (TV1) and vice versa. Actually S (mentioned in the statement) is the set of positions of the 1st TV where ti is 0. This means ith wire is tested for SA-1 fault, so they are needed to be tested for SA-0 fault, so these si will be 1 in the 2nd TV(temp). Now we must retain these TV(temp) to generate original 2nd and last TV, otherwise if any change is allowed, then we have to go for further TVs resulting |CTS| > 2. So to retain 2nd TV(temp), we must make sure that every gates fixes 2nd TV(temp) i.e. each gate contains at least one control input which is 0 i.e. there should be no gate such that gi S i.e. at least one bit of every gate gi must be in the set S = {1, 2, , n} S; S is the set of positions where 2nd TV(temp) has 0 . Here we show an example of Theorem 4.
Gate 1 2 3 4 5 6 7 Indices Input 5 3 3 3 2 2 1 of 6 4 5 6 4 6 2 Control

(a)

(b)

Fig. 3.9 (a) Original circuit (b) Corresponding description table

Example 3.5 Consider the circuit of Fig. 3.9(a) and its corresponding description_table in Fig. 3.9(b). Here S = {2, 3, 5}. We see that no gate has gi = {2, 3} or {2, 5} or {2, 3, 5} or {3, 5} i.e. no gi S,. So Theorem 4 says that, ECTSG algorithm generates 2 TVs for the CTS of this circuit. The 2 TVs are: 1 0 0 1 0 1 and 0 1 1 0 1 0.

4 EXPERIMENTAL RESULTS
We have implemented ECTSG using C programming language in an Intel Pentium 4 Desktop PC having CPU 1.7 GHz, 256 MB RAM with Microsoft Windows XP and tested a number of benchmark circuits with it. The result is depicted in Table 4.1. The designs of the benchmark

circuits are taken from [14]. We see that for an n-wire circuit, sometimes |CTS| = logn, sometimes |CTS| n/2, sometimes |CTS| = n. One thing stems out from this resulting Table 4.1 the more the number of gates, the more the possibility of fulfilling the conditions of theorem 3, therefore the more possibility of being |CTS| = n. Another thing is that ECTSG algorithm may be incorporated in a GUI, like [12], because taking the description of a circuit manually is not feasible as there may be many gates in a circuit. We used machine-readable versions of the designs of the benchmark circuits as some circuits have thousands of gates, and then we customized the descriptions of these designs according to the configuration of ECTSG algorithm; for example, we do not need any information about the inversion input of a gate. It is important to note that the machine-readable versions posted on [14] have a characteristic: all the elements (discarding the inversion input of a gate) of a row are sorted in increasing order. So result shown in Table 4.1 produced by ECTSG algorithm is based on this structure, but actually ECTSG not necessarily needs the rows to be sorted. Table 4.1 also contains a column to show the result of ECTSG without the sorting approach described in Section 3.2. From this column we notice that our conjecture mentioned in Section 3.2 holds true for all the benchmark circuits because no result is found to be better than the result got with sorting but converse is true for many cases. Comparison With Other Methods: We used fixing property of reversible circuits as the key technique. Here lies the similarity between [7] and us. As we said earlier that [7] showed that the size of CTS can be reduced to only 3 for any circuit consisting of k-CNOT gates (k 0) but always needs modification of the circuit by adding one extra wire and replacing every k-CNOT gate by (k +1)-CNOT gate, i.e., always needs to construct a DFT. As there may be hundreds of thousands of gates in a realworld circuit, it may be beneficial to opt for ECTSG algorithm instead of the algorithm of [7] because ECTSG may need to construct DFT by adding maximum two extra wires and to replace only the k-CNOT gates having k = 0 and 1 by (k + 2)-CNOT and (k + 1)-CNOT gates respectively. This means that if the original circuit has k 0, then we have to add 2 extra wires and all 0-CNOT and 1CNOT gates are replaced by 2-CNOT gates, and the original circuit has k 1, then we have to add 1 extra wire and all 1-CNOT gates are replaced by 2-CNOT gates, and if k 2 then there is no need to construct DFT. Obviously, the less the number of control inputs in k-CNOT gate, the cheaper the gate is [15]. Moreover, in our case |CTS| may be 2, i.e., optimal, but minimum |CTS| produced by [7] is 3 for the same circuit at hand. The other method of [7] generates n TVs, namely, n weight-1 vectors, for nwire k-CNOT (k 2) circuit regardless the number of gates. In Table 4.1 we show the number of TVs of the proposed is better than the method of [7] which generates exactly n TVs as CTS for an n-wire k-CNOT circuit (k 2). Some other researchers, specifically, Patel et al. [6] and Allen et al [12] did not use fixing property. Both the algorithms of [6] and [12] outperform ECTSG in terms of the requirement of modification of the original circuit (i.e.

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hardware cost) because none of their technique requires to construct DFT like ECTSG; but as we said earlier that cost of 2-CNOT gates, which ECTSG requires to be added in a circuit where 0-CNOT and/or 1-CNOT gates exist, are normally nominal [15]. Moreover, ECTSG algorithm is superior to [12] in most cases in terms of |CTS|, equal in a small number of cases, and worse in a very rare case as shown in Table 4.1. And lastly, in [12], minimum |CTS| is 3 in table 4.1 but it is reduced by ECTSG to 2.

http://www.zyvex.com/nanotech/reversible.html [3] http://paginas.fe.up.pt/~jmf/hibu2k2/contents/btc/btcintro.htm [4] V.D. Agrawal, An information theoretic approach to digital fault testing, IEEE Trans. Con Comp. (1981) 582-587. [5] K.N. Patel, J.P. Hayes, I. L. Markov, Fault testing for reversible circuits, VLSI Test Symposium, 21 (2003) 410 416. [6] A. Chakraborty, Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays, 18th International Conference on VLSI Design (2005) 249-254. [7] http://en.wikipedia.org/wiki/Design_for_test [8] http://en.wikipedia.org/wiki/Automatic_test_pattern_generation [9] http://en.wikipedia.org/wiki/Fault_model
[10] http://paginas.fe.up.pt/~jmf/hibu2k2/contents/btc/btc-tvg.htm

CONCLUSION

Utilizing fixing property, we have presented a heuristic algorithm which generates complete test set for stuck-at model for reversible circuits consisting of k-CNOT gates with k 2. The limitation k 2 can be lifted because any nwire k-CNOT circuit with k 0 can be easily converted to a (n + 2)-wire k-CNOT circuit with k 2. We have discussed when our algorithm yields complete test set of maximum and minimum size n and 2 respectively for a n-wire circuit. We also provided experimental results and discussed comparison between our algorithm and the existing methods.

[11] J.S. Allen, Jacob D. Biamonte, Marek A. Perkowski, ATPG for Reversible Circuits using Technology-Related Fault Models, International Symposium on Representations and Methodologies for Emergent Computing Technologies, Tokyo, Japan, September (2005). [12] I. Shigeru, I. Yusuke, T. Satoshi, U. Shuichi, On the Complexity of Fault Testing for Reversible Circuits, IEIC Technical Report (Institute of Electronics, Info.and Comm. Engineers) 105 (2005) 13-16. [13] D. Maslov, G. Dueck, and N. Scott, Reversible Logic Synthesis BenchmarksPage.http://webhome.cs.uvic.ca/~dmaslov/ [14] J. P. Hayes, I. Polian, B. Becker, Testing for Missing Gate Faults in Reversible Circuits, Asian Test Symposium (1004) 100 105 Muhammad Ibrahim Muhammad Ibrahim has received his MS and BSc(Hons) degree in Computer Science and Engineering (CSE) from the University of Dhaka, Bangladesh. At present he is a Lecturer in the Department of CSE at the Ahsanullah University of Science and Technology, Dhaka, Bangladesh. His research interests include Reversible Logic, Text Mining, and Information Retrieval. Ahsan Raja Chowdhury Ahsan Raja Chowdhury is working as an Assistant Professor in Dept. of CSE, University of Dhaka, Bangladesh. He has received his BSc (Hons) and MS from the same institution. His research interests include Artificial Intelligence, Fuzzy Logic, Reversible Logic, Bioinformatics. Number of TVs ECTSG without sorting* # of TVs by proposed ECTSG* Number of TVs in [6]* Number of TVs in [7]**

REFERENCES
[1] [2]

C. Bennett, Logical reversibility of computation, IBM Journal of Research and Development 17 (1973) 525532. R. Landauer, Irreversibility and heat generation in the computational process, IBM Journal of Research Development 5 (1961) 183191. Table 4.1 Experimental Results Benchmark Circuits Model Bits of original circuit Bits of DFT Number of gates

2of5 GT 6 8 18 2 2 8 4 4 49 GT 4 6 16 4 4 6 4 3 17 NCT 3 5 6 3 3 5 4 6sym NCT 10 11 20 6 4 11 5 9sym NCT 12 13 28 8 4 13 5 Cycle 10 2 GT 12 13 19 2 2 13 5 Cycle 17 3 GT 20 21 48 2 2 21 6 Gray code function N/A 6 7 5 2 2 7 N/G Ham 3 NCT 3 4 5 3 3 4 N/G Ham7 GT 7 8 23 3 3 8 4 Ham 15 GT 15 16 132 5 5 16 12 Hwb4 GT 4 5 17 4 4 5 4 Hwb5 GT 5 6 55 6 6 6 7 Hwb6 GT 6 7 126 7 7 7 11 Hwb7 GT 7 8 289 8 8 8 13 Hwb8 GT 8 10 637 9 9 10 N/G Hwb9 GT 9 10 1544 10 9 10 N/G Hwb10 GT 10 11 3631 11 11 11 N/G Hwb11 GT 11 12 9314 12 12 12 N/G Mod5 NCT 5 6 8 3 3 6 N/G Mod5adder GT 6 8 21 3 3 8 4 Mod1024adder GT 20 21 55 3 3 21 N/G Mod 1048576adder GT 40 41 210 3 3 41 N/G Rd32 NCT 4 5 4 3 3 5 3 Rd53 GT 7 9 30 3 3 9 N/G Rd73 NCT 10 11 20 7 4 11 4 Rd84 NCT 15 16 28 8 4 16 6 Xor5 NCT 5 6 4 2 2 6 N/G * means this case works on DFT, i.e. needs the same number of bits as DFT. ** means this case works on original circuit, i.e. needs the same number of bits as original circuit. N/G and N/A stands for Not Given in this paper and Not Applicable respectively