A 5.

8-GHz High Efficient, Low Power, Low Phase Noise

CMOS VCO for IEEE 802.11a
Sau-Mou Wu, Ron-Yi Liu
+
and Wei-Liang Chen
The Graduated School of Electrical Engineering, Yuan-Ze University
135 Yuan-Tong Road, Chung-Li, Taiwan, ROC.
+
Telecommunication Labs., Yang-Mei, Taoyuan, Taiwan, ROC
eesmwu@saturn.yzu.edu.tw
Abstract
A high efficient, low power and low phase noise 5.8GHz
LC voltage-controlled oscillator (VCO) for IEEE 802.11a
WLAN applications is designed and fabricated in TSMC
0.25um 1P5M CMOS process. With single 2.5V supply, it
has a tuning range of 240MHz and a phase noise of -
115dBc/Hz at 1MHz offset from center frequency
throughout the tuning range. The total power
consumption is 6.23mW while the VCO core consumes
only 2.62mW. Compared with the recent proposed works
by using the power-frequency-normalized (PFN) figure of
merit, it shows a superior phase noise performance while
with very low power consumption.
1. Introduction
Due to the ever-increasing demands for
telecommunication market, there is a clear trend toward
full integration of the radio-frequency (RF) front end in a
single chip for the low cost and power considerations
[1,2]. A major challenge for full integration is the local
oscillator (LO) frequency synthesizer, especially for the
very high frequency requests. The most important
building block that dominates the performance of a
frequency synthesizer is the voltage-controlled oscillator
(VCO).
For monolithic integration, high-frequency operation
with reasonable power consumption, wider tuning range,
good phase noise performance and a smaller chip area are
the general considerations for VCO designs. Focusing on
high operation frequency of several GHz where low
phase noise requirement and low power consumption are
the major concerns, resonance LC-tank is the preferred
oscillator structure than its ring counterpart for the
modern telecommunication standards [3]. This is reflected
in the enormous amount of research on LC based
oscillator, circuit design optimization and theoretical
analysis, especially for cross-coupled differential LC
structure [3-10].
In this paper, complementary cross-coupled structure
is used for a low power, low phase noise LC VCO design.
The center frequency of the VCO is targeted at 5.8GHz
and the simulated result shows superior phase noise
performance throughout the 240MHz tuning range with
very low power consumption. It meets the specification
for 5.725-5.825 GHz band of the IEEE 802.11a WLAN
standard.
2. Circuit design
The 100MHz bandwidth for use is 5.725-5.825GHz.
For the highest data-rate of 54Mb/s, the IEEE 802.11a
uses 64-QAM with OFDM in a 20MHz channel
bandwidth. With the requirement of -65dBm receiver
sensitivity and an adjacent -40dB unwanted signal. The
phase noise request for the VCO of at least -110dBc/Hz at
1MHz offset can be derived [10].
Figure 1. Schematic of VCO
The circuit schematic of the VCO is shown in Fig. 1.
A negative resistance is formed by the double cross-
connection of an NMOS (M1, M2) and a PMOS (M3,
M4) differential pairs in positive feedback. Contrast to the
NMOS only structure, this allows using the supply
current twice for amplification in the same supply
V
Bias
M3 M4
M5
M1
M2
M6
V
C

Proceedings of The 3rd IEEE International Workshop on System-on-Chip
for Real-Time Applications ISBN 0-7695-1929-6/03 $17.00 2003 IEEE
voltage. Transistors M5 and M6 form a simple common-
source output buffer for measurement consideration. A
drawback of this configuration is the larger parasitic
capacitance of the PMOS which will result in a slight
decrease in the available tuning range. The tuning of the
VCO is done through the varactor which is composed of
p+/n-well junctions with the control voltage V
C
and the
maximum frequency will be obtained with the highest
tuning voltage of 2.5V. For low power consideration, a
low value for V
GS
V
T
is designed; which gives a good
transconductance to current ratio and hence power
consumption can be reduced. The coil and its model used
in this design are depicted in Fig. 2. Unlike the
symmetrical shape as in [5], the standard square inductor
used here will encounter slightly unbalance problem in
differential signal output; however, this can be solved by
combining two identical inductors for one equivalent
inductor [10]. Note that, in this design only single-end
output will be used.
Figure 2. Planar square shape inductor
3. Theoretical analysis
For the sake of higher resonance frequency, lower
noise contribution, and lower power consumption, the
series resistance of the inductor must be as low as
possible corresponding to the smaller inductance.
According to the following formula proposed by [3], the
above statement can be proved.
{ }
( )
( )
| |
2 /
1
2
2
0
2 / 1
2 / 1
2
0
0
amp
eff
f f
f f
out
V
w
w
A R kT
power signal
dV
f L
|
.
|

\
|
A
+
=
= A
)
+ A +
A +
(1)
( )
( )
2
0
2
0
L w
R
C w R G
eff
eff M
= = (2)
where the L{f} is the phase noise at f offset from f
o
; R
eff
, w, and A represent effective resistance of the LC-tank,
frequency offset from carrier, and noise from the active
device of oscillator amplifier respectively. The G
M
term is
used to estimate the required negative resistance, formed
by the cross-coupled pair, for compensating the power
loss in R
eff
in order to sustain oscillation of the VCO.
In this design, the inductance is about 2.17nH and its
series resistance is about 3.42 ohm. In general, R
eff
is
approximately equal to the series resistance and the
required negative conductance can be predicted by Eq. (2).
( )
mS
nH GHz
G
M
547 . 0
17 . 2 8 . 5 2
42 . 3
2
~

O
=
t
(3)
However, in practical situation, the transconductance
will be larger. This can be due to a phase shift in the
transconductor, or a safety margin for the oscillator.
Assume the safety factor to be 2.5; each transistor (M1-
M4) must have a transconductance more than
mS mS 3675 . 1 5 . 2 547 . 0 = . In this design, the resulting
output amplitude is 0.8V such that according to Eq. (1),
the expected phase noise at 1MHz offset is about
{ }
( )
Hz dBc
V
MHz
GHz
kT
MH L
/ 87 . 112
10 16 . 5
2 / 8 . 0
1
8 . 5
5 . 2 1 423 . 3
1
12
2
2
=
=
|
.
|

\
|
+ O
=

(4)
which is about 3dB better than the required specification.
In order for a fast estimation, the above estimation does
not take into account the losses in junction capacitors and
transistors. A more accurate estimation will be given by
simulation in section 5.
4. Layout consideration
Figure 3. Physical layout of VCO
The physical layout of the VCO is shown in Fig. 3.
Owing to the high sensitivity to parasitics for RF circuits,
the circuit layout should be done with special care.
Several useful techniques will be reminded as follow.
First, also in general analog circuit, the layout symmetry
C
sub1 R
sub1
C
sub2 R
sub2
R
s L
C
ox2
C
ox1
C
s
(a) Coil Shape (b) Equivalent circuit
Proceedings of The 3rd IEEE International Workshop on System-on-Chip
for Real-Time Applications ISBN 0-7695-1929-6/03 $17.00 2003 IEEE
is needed to minimize the even-order distortion in output
waveform; common centroid, multi-finger and extra
dummy placements are all valid techniques which can
improve the device matching against the process gradient.
Second, the interconnection lines should be as short as
possible and the cross line must be avoided so as to
reduce the parasitic inductance and capacitance. Also, the
too thin or too wide line is not recommended, which will
produce large parasitic resistance or capacitance
respectively. Finally, let passive element, inductor in this
design, far away from active devices and p+ guard ring
should be used to reduce the substrate noise coupling.
5. Simulation result
Fig. 4 shows the frequency response of the VCO at
5.8GHz with the corner model variation (SS, TT, FF) and
the variation of tuning range is depicted in Fig. 5.
Figure 4. Frequency response
Figure 5. VCO tuning characteristic
Shown in Fig. 6 is the phase noise simulated by using
SpectreRF. The simulated phase noise performance is
about -115dBc/Hz at 1MHz offset which is 5dB better
than the specification and 2dB better than the manual
calculation in section 3. The overall performance is
tabulated in Table1.
Figure 6. Phase noise performance
Table 1. Performance summary of the VCO
Items Specification Performance
Power Supply 2.5V 2.5V
Center
Frequency
5.8GHz 5.8GHz
Tuning Range 5.725-5.825GHz 5.65-5.89GHz
Phase Noise -
110dBc/Hz@1MHz
-
115dBc/Hz@1MHz
Power
Consumption
- 6.32mW (total)
2.62mW (core)
Chip Area - 0.951 0.515mm
2
(pad frame)
In order to compare the performance with other recently
proposed works in terms of center frequency, phase noise
and power consumption, the power-frequency-normalized
(PFN) figure of merit is defined as [7]
( )
off
off
f S
f
f
P
kT
PFN
|

(
(

|
|
.
|

\
|
=
2
0
sup
log 10 (5)
where P
sup
is the total dc power consumption in the VCO,
f
off
is the offset frequency from the carrier and ) (
off
f S
|
is
0
M
a
g
n
i
t
u
d
e

(
d
B
)

-20
-40
-60
-80
-100
-120
5 10
Frequency (GHz)
FF
TT
SS
5.90
F
r
e
q
u
e
n
c
y

(
G
H
z
)

5.85
5.80
5.75
5.70
5.65
5.60
5.55
0 0.5 1 1.5 2 2.5
Control Voltage (V)
-30
P
h
a
s
e

N
o
i
s
e

(
d
B
c
/
H
z
)

-50
-70
-90
-110
-130
0 0.4 0.8 1.2 1.6 2
Offset frequency (MHz)
o
-115dBc/Hz@1MHz offset
FF (5.81GHz)
TT (5.80GHz)
SS (5.74GHz)
Proceedings of The 3rd IEEE International Workshop on System-on-Chip
for Real-Time Applications ISBN 0-7695-1929-6/03 $17.00 2003 IEEE
the phase noise. The comparison results are tabulated in
Table in which a larger value of PFN means a better
design.
Table 2. Performance comparison of VCOs
Design Center
Frequency
(GHz)
Power
Consumption
(mW)
PFN
Ref. [5] 1.8 11 4.21
Ref. [6] 1.8 6 3.76
Ref. [7] 2.6 10 3.74
Ref. [8] 5.2 12.5 -20.13
Ref. [9] 5.35 7 9.2
Ref. [10] 5.8 5 6.27
This work 5.8 2.62 12.2
From Table 2, we can find that this work achieves a
superior phase noise performance with effective low
power consumption.
6. Conclusions
In this paper, we demonstrate a 5.8GHz high efficient,
low power, and low phase noise VCO that is suitable for
IEEE 802.11a WLAN applications. It has a tuning range
of 240MHz and -115dBc/Hz at 1MHz offset from center
frequency throughout the tuning range. The total power
consumption is 6.23mW while the VCO core consumes
only 2.62mW with a 2.5V power supply. By using the
PFN figure of merit, the comparison with recent works
shows that this work achieves a superior phase noise with
low power consumption. The designed chip is fabricated
in TSMC 0.25um CMOS process.
7. Acknowledgement
The authors would like to thank Chip Implementation
Center (CIC), National Science Council, Taiwan, ROC,
for fabricating the chip.
8. References
[1] T. H. Lee, H. Samavati, and H. R. Rategh, 5-GHz
CMOS Wireless LAN, IEEE Trans. Microwave Theory
and Techniques, vol. 50, pp. 268-280, Jan. 2002.
[2] M. Steyaert et al., A 2-V CMOS cellular transceiver
front-end, IEEE J. Solid-State Circuits, vol. 35, pp.
1895-1907, Dec. 2000.
[3] J. Craninckx and M. Steyaert, Low-noise voltage-
controlled oscillators using enhanced LC-tanks, IEEE
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[7] D. Ham and A. Hajimiri, Concepts and methods in
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[8] C. Lam and B. Razavi, A 2.6-GHz/5.2-GHz frequency
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[10] J. Bhattacharjee et al., A 5.8 GHz fully integrated low
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Proceedings of The 3rd IEEE International Workshop on System-on-Chip
for Real-Time Applications ISBN 0-7695-1929-6/03 $17.00 2003 IEEE