Topics

Latch up Role of DNW

Latch up
Majority GR
GND VDD

Minority GR
GND

Majority GR
VDD

N+

P+

N+

N+

P+

N+

P+

N+

P+

P+

N+

e-

h+

N-WELL

N-well

P-WELL e-

N-well

N-WELL

DNW

DNW e-

DNW

This DNW acts like a minority GR which traps h+ the stray electron escaping towards the P device. It is more effective vs the shallow N+/Nwell structure also it repels the stray hole that came from the P device that was heading towards the N device, this was not possible without DNW

These resistors we P-WELL want smaller so the base current to BJTs can be reduced and these resistors we want larger so the feedback can be reduced e-

N-well N-WELL

DNW This DNW reduces the gain of h+ this vertical PNP by increasing its base area. But this DNW also increases the parasitic resistor from base to emitter thereby increasing the base current for the VPNP (which is not desired)

e-

h+

h+

P-SUB

Role of DNW
Electrons originating from N-device and going towards and P-device and holes originating from P-device and heading towards N-device is what causes latchup. Vertical devices have the higher gain vs the lateral (because of the smaller base area), the DNW definitely increases the base area of the vertical device (if we add DNW under the N-well) thereby reducing the gain() of this parasitic BJT. The DNW around the N device (minority GR) becomes more effective because of increased depth and also now it is effective against the stray holes that are coming towards the N device. Think it is a good idea to put DNW under P-well as well as N-well. But not connect the DNW under P-well with DNW under N-well. The minority GR (N+/Nwell/DNW) around N-device can be made to abut the DNW under the N-device so the N-device can be completely encapsulated in its own private P-well (as shown) isolated from the P-sub by the N+/Nwell/DNW GR. This is probably a good isolation from latch-up. N-wells are more resistive than P-well. What this means is that the vertical devices get more base current. My guess is that the DNW does not help reduce the base current because now we have more N-well area (because of DNW under N-well). Although this is not applicable if we dont put DNW under the Nwell. I think the majority GR (substrate contacts) inside the N-well should help reduce this effect. Also it may be a good idea to have more well contacts for Nwell to reduce this effect

Additional notes
A few additional things to consider:
fabs recommends using double guardrings (both N+/PSUB and P+/NW) for isolating sensitive circuits. I suggest that including DNW in the P+/NW guardring will also help as long as the DNW in the guard ring is isolated from any other DNW or NW. Isolating both the P and N devices is the best for noise isolation, but may not always be practical for area concerns due to DNW/NW spacing. Unfortunately, the PSUB bulk is relatively low resistance (vs. with an epi-wafer) so increase spacing will have only minimal effect . More distance will always help though. We dont always have isolated ground pins, so eventually the PWell is connected to the substrate at some point on-chip (especially in small pin count chips). The goal is to make that gnd tie to PWell connection as resistive and isolated as possible.

I dont think there is much we can do to increase the substrate resistance. But, by ensuring that the parasitic base current is small, we greatly reduce the chance that the feedback path is turned on.